Lines Matching refs:pipe_stats
924 u32 pipe_stats[I915_MAX_PIPES] = { 0 };
943 pipe_stats[pipe] = I915_READ(reg);
948 if (pipe_stats[pipe] & 0x8000ffff) {
949 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
952 I915_WRITE(reg, pipe_stats[pipe]);
958 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
961 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
981 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2984 u32 pipe_stats[2] = { 0 };
3009 pipe_stats[pipe] = I915_READ(reg);
3014 if (pipe_stats[pipe] & 0x8000ffff) {
3015 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3018 I915_WRITE(reg, pipe_stats[pipe]);
3031 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
3035 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
3158 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES] = { 0 };
3182 pipe_stats[pipe] = I915_READ(reg);
3185 if (pipe_stats[pipe] & 0x8000ffff) {
3186 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3189 I915_WRITE(reg, pipe_stats[pipe]);
3224 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3388 u32 pipe_stats[I915_MAX_PIPES] = { 0 };
3415 pipe_stats[pipe] = I915_READ(reg);
3420 if (pipe_stats[pipe] & 0x8000ffff) {
3421 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3424 I915_WRITE(reg, pipe_stats[pipe]);
3461 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&