112 	enum pipe pipe;
116 	for_each_pipe(pipe) {
117 		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
129 	enum pipe pipe;
132 	for_each_pipe(pipe) {
133 		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
143 						 enum pipe pipe, bool enable)
146 	uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
179 	uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
215  * @pipe: pipe
219  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
220  * reporting for one pipe may also disable all the other CPU error interruts for
227 					   enum pipe pipe, bool enable)
230 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
245 		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
257  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
273 	enum pipe p;
318 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
320 	u32 reg = PIPESTAT(pipe);
333 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
335 	u32 reg = PIPESTAT(pipe);
347  * i915_pipe_enabled - check if a pipe is enabled
349  * @pipe: pipe to check
351  * Reading certain registers when the pipe is disabled can hang the chip.
352  * Use this routine to make sure the PLL is running and the pipe is active
356 i915_pipe_enabled(struct drm_device *dev, int pipe)
362 		struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
367 		return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
372  * we use as a pipe index
374 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
381 	if (!i915_pipe_enabled(dev, pipe)) {
383 				"pipe %c\n", pipe_name(pipe));
387 	high_frame = PIPEFRAME(pipe);
388 	low_frame = PIPEFRAMEPIXEL(pipe);
406 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
409 	int reg = PIPE_FRMCOUNT_GM45(pipe);
411 	if (!i915_pipe_enabled(dev, pipe)) {
413 				 "pipe %c\n", pipe_name(pipe));
420 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
429 								      pipe);
431 	if (!i915_pipe_enabled(dev, pipe)) {
433 				 "pipe %c\n", pipe_name(pipe));
444 		position = I915_READ(PIPEDSL(pipe));
456 		position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
488 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
495 	if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
496 		DRM_ERROR("Invalid crtc %d\n", pipe);
501 	crtc = intel_get_crtc_for_pipe(dev, pipe);
503 		DRM_ERROR("Invalid crtc %d\n", pipe);
508 		DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
513 	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
923 	int pipe;
941 		for_each_pipe(pipe) {
942 			int reg = PIPESTAT(pipe);
943 			pipe_stats[pipe] = I915_READ(reg);
948 			if (pipe_stats[pipe] & 0x8000ffff) {
949 				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
950 					DRM_DEBUG_DRIVER("pipe %c underrun\n",
951 							 pipe_name(pipe));
952 				I915_WRITE(reg, pipe_stats[pipe]);
957 		for_each_pipe(pipe) {
958 			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
959 				drm_handle_vblank(dev, pipe);
961 			if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
962 				intel_prepare_page_flip(dev, pipe);
963 				intel_finish_page_flip(dev, pipe);
999 	int pipe;
1027 		for_each_pipe(pipe)
1028 			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1029 					 pipe_name(pipe),
1030 					 I915_READ(FDI_RX_IIR(pipe)));
1101 	int pipe;
1126 		for_each_pipe(pipe)
1127 			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1128 					 pipe_name(pipe),
1129 					 I915_READ(FDI_RX_IIR(pipe)));
1825 	int i, pipe;
1833 	/* Account for pipe specific data like PIPE*STAT */
1870 		for_each_pipe(pipe)
1871 			error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1960 	int pipe;
2011 		for_each_pipe(pipe)
2012 			DRM_DEBUG("pipe %c stat: 0x%08x\n",
2013 			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2100 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2103 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2147  * we use as a pipe index
2149 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2154 	if (!i915_pipe_enabled(dev, pipe))
2159 		i915_enable_pipestat(dev_priv, pipe,
2162 		i915_enable_pipestat(dev_priv, pipe,
2173 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2178 	if (!i915_pipe_enabled(dev, pipe))
2182 	ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
2189 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
2194 	if (!i915_pipe_enabled(dev, pipe))
2199 				    DE_PIPEA_VBLANK_IVB << (5 * pipe));
2205 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2211 	if (!i915_pipe_enabled(dev, pipe))
2216 	if (pipe == 0)
2221 	i915_enable_pipestat(dev_priv, pipe,
2229  * we use as a pipe index
2231 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2240 	i915_disable_pipestat(dev_priv, pipe,
2246 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2252 	ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
2257 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
2264 				     DE_PIPEA_VBLANK_IVB << (pipe * 5));
2268 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2275 	i915_disable_pipestat(dev_priv, pipe,
2278 	if (pipe == 0)
2595 	int pipe;
2616 	for_each_pipe(pipe)
2617 		I915_WRITE(PIPESTAT(pipe), 0xffff);
2854 	int pipe;
2861 	for_each_pipe(pipe)
2862 		I915_WRITE(PIPESTAT(pipe), 0xffff);
2867 	for_each_pipe(pipe)
2868 		I915_WRITE(PIPESTAT(pipe), 0xffff);
2909 	int pipe;
2913 	for_each_pipe(pipe)
2914 		I915_WRITE(PIPESTAT(pipe), 0);
2951 			       int pipe, u16 iir)
2954 	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2956 	if (!drm_handle_vblank(dev, pipe))
2962 	intel_prepare_page_flip(dev, pipe);
2973 	intel_finish_page_flip(dev, pipe);
2986 	int pipe;
3007 		for_each_pipe(pipe) {
3008 			int reg = PIPESTAT(pipe);
3009 			pipe_stats[pipe] = I915_READ(reg);
3014 			if (pipe_stats[pipe] & 0x8000ffff) {
3015 				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3016 					DRM_DEBUG_DRIVER("pipe %c underrun\n",
3017 							 pipe_name(pipe));
3018 				I915_WRITE(reg, pipe_stats[pipe]);
3048 	int pipe;
3050 	for_each_pipe(pipe) {
3052 		I915_WRITE(PIPESTAT(pipe), 0);
3053 		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3063 	int pipe;
3073 	for_each_pipe(pipe)
3074 		I915_WRITE(PIPESTAT(pipe), 0);
3126 			       int plane, int pipe, u32 iir)
3131 	if (!drm_handle_vblank(dev, pipe))
3148 	intel_finish_page_flip(dev, pipe);
3163 	int pipe, ret = IRQ_NONE;
3180 		for_each_pipe(pipe) {
3181 			int reg = PIPESTAT(pipe);
3182 			pipe_stats[pipe] = I915_READ(reg);
3185 			if (pipe_stats[pipe] & 0x8000ffff) {
3186 				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3187 					DRM_DEBUG_DRIVER("pipe %c underrun\n",
3188 							 pipe_name(pipe));
3189 				I915_WRITE(reg, pipe_stats[pipe]);
3219 		for_each_pipe(pipe) {
3220 			int plane = pipe;
3224 			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3225 			    i915_handle_vblank(dev, plane, pipe, iir))
3258 	int pipe;
3268 	for_each_pipe(pipe) {
3270 		I915_WRITE(PIPESTAT(pipe), 0);
3271 		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3282 	int pipe;
3290 	for_each_pipe(pipe)
3291 		I915_WRITE(PIPESTAT(pipe), 0);
3391 	int ret = IRQ_NONE, pipe;
3413 		for_each_pipe(pipe) {
3414 			int reg = PIPESTAT(pipe);
3415 			pipe_stats[pipe] = I915_READ(reg);
3420 			if (pipe_stats[pipe] & 0x8000ffff) {
3421 				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3422 					DRM_DEBUG_DRIVER("pipe %c underrun\n",
3423 							 pipe_name(pipe));
3424 				I915_WRITE(reg, pipe_stats[pipe]);
3460 		for_each_pipe(pipe) {
3461 			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3462 			    i915_handle_vblank(dev, pipe, pipe, iir))
3463 				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3495 	int pipe;
3506 	for_each_pipe(pipe)
3507 		I915_WRITE(PIPESTAT(pipe), 0);
3511 	for_each_pipe(pipe)
3512 		I915_WRITE(PIPESTAT(pipe),
3513 			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);

Indexes created Tue Jul 24 14:28:13 CEST 2018