Lines Matching defs:enable
143 enum pipe pipe, bool enable)
149 if (enable)
156 bool enable)
160 if (enable) {
175 bool enable)
182 if (enable)
192 bool enable)
196 if (enable) {
213 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
216 * @enable: true if we want to report FIFO underrun errors, false otherwise
218 * This function makes us disable or enable CPU fifo underruns for a specific
221 * the other pipes, due to the fact that there's just one interrupt mask/enable
227 enum pipe pipe, bool enable)
239 if (enable == ret)
242 intel_crtc->cpu_fifo_underrun_disabled = !enable;
245 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
247 ivybridge_set_fifo_underrun_reporting(dev, enable);
255 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
258 * @enable: true if we want to report FIFO underrun errors, false otherwise
260 * This function makes us disable or enable PCH fifo underruns for a specific
264 * one interrupt mask/enable bit for all the transcoders.
270 bool enable)
301 if (enable == ret)
304 intel_crtc->pch_fifo_underrun_disabled = !enable;
307 ibx_set_fifo_underrun_reporting(intel_crtc, enable);
309 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
2534 * is enabled - instead we unconditionally enable all PCH interrupt
2686 /* enable kind of interrupts always enabled */
2738 /* enable kind of interrupts always enabled */
2778 /* Our enable/disable rps functions may touch these registers so
2808 *Leave vblank interrupts masked initially. enable/disable will
2840 /* ack & enable invalid PTE error interrupts */
3051 /* Clear enable bits; then clear status bits */
3269 /* Clear enable bits; then clear status bits */
3364 /* enable bits are the same for all generations */