Lines Matching refs:part2
712 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
719 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
773 &dtd->part2, sizeof(dtd->part2));
815 dtd->part2.h_sync_off = h_sync_offset & 0xff;
816 dtd->part2.h_sync_width = h_sync_len & 0xff;
817 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
819 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
823 dtd->part2.dtd_flags = 0x18;
825 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
827 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
829 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
831 dtd->part2.sdvo_flags = 0;
832 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
833 dtd->part2.reserved = 0;
841 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
842 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
843 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
844 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
851 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
852 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
853 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
855 (dtd->part2.v_sync_off_width & 0xf);
856 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
863 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
865 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
867 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1049 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1211 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1267 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1330 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1335 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)