Lines Matching refs:val
147 u32 val = I915_READ(VIDEO_DIP_CTL);
150 if (!(val & VIDEO_DIP_ENABLE))
153 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
154 val |= g4x_infoframe_index(frame);
156 val &= ~g4x_infoframe_enable(frame);
158 I915_WRITE(VIDEO_DIP_CTL, val);
170 val |= g4x_infoframe_enable(frame);
171 val &= ~VIDEO_DIP_FREQ_MASK;
172 val |= VIDEO_DIP_FREQ_VSYNC;
174 I915_WRITE(VIDEO_DIP_CTL, val);
188 u32 val = I915_READ(reg);
190 if (!(val & VIDEO_DIP_ENABLE))
193 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
194 val |= g4x_infoframe_index(frame);
196 val &= ~g4x_infoframe_enable(frame);
198 I915_WRITE(reg, val);
210 val |= g4x_infoframe_enable(frame);
211 val &= ~VIDEO_DIP_FREQ_MASK;
212 val |= VIDEO_DIP_FREQ_VSYNC;
214 I915_WRITE(reg, val);
228 u32 val = I915_READ(reg);
230 if (!(val & VIDEO_DIP_ENABLE))
233 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
234 val |= g4x_infoframe_index(frame);
239 val &= ~g4x_infoframe_enable(frame);
241 I915_WRITE(reg, val);
253 val |= g4x_infoframe_enable(frame);
254 val &= ~VIDEO_DIP_FREQ_MASK;
255 val |= VIDEO_DIP_FREQ_VSYNC;
257 I915_WRITE(reg, val);
271 u32 val = I915_READ(reg);
273 if (!(val & VIDEO_DIP_ENABLE))
276 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
277 val |= g4x_infoframe_index(frame);
279 val &= ~g4x_infoframe_enable(frame);
281 I915_WRITE(reg, val);
293 val |= g4x_infoframe_enable(frame);
294 val &= ~VIDEO_DIP_FREQ_MASK;
295 val |= VIDEO_DIP_FREQ_VSYNC;
297 I915_WRITE(reg, val);
312 u32 val = I915_READ(ctl_reg);
317 val &= ~hsw_infoframe_enable(frame);
318 I915_WRITE(ctl_reg, val);
330 val |= hsw_infoframe_enable(frame);
331 I915_WRITE(ctl_reg, val);
392 u32 val = I915_READ(reg);
406 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
409 if (!(val & VIDEO_DIP_ENABLE))
411 val &= ~VIDEO_DIP_ENABLE;
412 I915_WRITE(reg, val);
429 if (port != (val & VIDEO_DIP_PORT_MASK)) {
430 if (val & VIDEO_DIP_ENABLE) {
431 val &= ~VIDEO_DIP_ENABLE;
432 I915_WRITE(reg, val);
435 val &= ~VIDEO_DIP_PORT_MASK;
436 val |= port;
439 val |= VIDEO_DIP_ENABLE;
440 val &= ~VIDEO_DIP_ENABLE_VENDOR;
442 I915_WRITE(reg, val);
457 u32 val = I915_READ(reg);
463 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
466 if (!(val & VIDEO_DIP_ENABLE))
468 val &= ~VIDEO_DIP_ENABLE;
469 I915_WRITE(reg, val);
489 if (port != (val & VIDEO_DIP_PORT_MASK)) {
490 if (val & VIDEO_DIP_ENABLE) {
491 val &= ~VIDEO_DIP_ENABLE;
492 I915_WRITE(reg, val);
495 val &= ~VIDEO_DIP_PORT_MASK;
496 val |= port;
499 val |= VIDEO_DIP_ENABLE;
500 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
503 I915_WRITE(reg, val);
517 u32 val = I915_READ(reg);
522 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
525 if (!(val & VIDEO_DIP_ENABLE))
527 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
528 I915_WRITE(reg, val);
534 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
535 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
538 I915_WRITE(reg, val);
552 u32 val = I915_READ(reg);
557 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
560 if (!(val & VIDEO_DIP_ENABLE))
562 val &= ~VIDEO_DIP_ENABLE;
563 I915_WRITE(reg, val);
568 val |= VIDEO_DIP_ENABLE;
569 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
572 I915_WRITE(reg, val);
586 u32 val = I915_READ(reg);
596 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
599 I915_WRITE(reg, val);
962 uint64_t val)
970 ret = drm_object_property_set_value(&connector->base, property, val);
975 enum hdmi_force_audio i = (enum hdmi_force_audio) val;
999 switch (val) {
1039 u32 val;
1045 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1046 val = 0;
1048 val |= (1<<21);
1050 val &= ~(1<<21);
1051 val |= 0x001000c4;
1052 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);