Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching refs:frame
72 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
74 	uint8_t *data = (uint8_t *)frame;
78 	frame->checksum = 0;
79 	frame->ecc = 0;
81 	for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
84 	frame->checksum = 0x100 - sum;
87 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
89 	switch (frame->type) {
95 		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
100 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
102 	switch (frame->type) {
108 		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
113 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
115 	switch (frame->type) {
121 		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
126 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame,
129 	switch (frame->type) {
135 		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
141 				struct dip_infoframe *frame)
144 	uint32_t *data = (uint32_t *)frame;
148 	unsigned i, len = DIP_HEADER_SIZE + frame->len;
154 	val |= g4x_infoframe_index(frame);
156 	val &= ~g4x_infoframe_enable(frame);
170 	val |= g4x_infoframe_enable(frame);
179 				struct dip_infoframe *frame)
182 	uint32_t *data = (uint32_t *)frame;
187 	unsigned i, len = DIP_HEADER_SIZE + frame->len;
194 	val |= g4x_infoframe_index(frame);
196 	val &= ~g4x_infoframe_enable(frame);
210 	val |= g4x_infoframe_enable(frame);
219 				struct dip_infoframe *frame)
222 	uint32_t *data = (uint32_t *)frame;
227 	unsigned i, len = DIP_HEADER_SIZE + frame->len;
234 	val |= g4x_infoframe_index(frame);
238 	if (frame->type != DIP_TYPE_AVI)
239 		val &= ~g4x_infoframe_enable(frame);
253 	val |= g4x_infoframe_enable(frame);
262 				     struct dip_infoframe *frame)
265 	uint32_t *data = (uint32_t *)frame;
270 	unsigned i, len = DIP_HEADER_SIZE + frame->len;
277 	val |= g4x_infoframe_index(frame);
279 	val &= ~g4x_infoframe_enable(frame);
293 	val |= g4x_infoframe_enable(frame);
302 				struct dip_infoframe *frame)
305 	uint32_t *data = (uint32_t *)frame;
310 	u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->config.cpu_transcoder);
311 	unsigned int i, len = DIP_HEADER_SIZE + frame->len;
317 	val &= ~hsw_infoframe_enable(frame);
330 	val |= hsw_infoframe_enable(frame);
336 				struct dip_infoframe *frame)
340 	intel_dip_infoframe_csum(frame);
341 	intel_hdmi->write_infoframe(encoder, frame);