Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching defs:reg
151 		DRM_ERROR("Writing DIP with CTL reg disabled\n");
186 	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
188 	u32 val = I915_READ(reg);
191 		DRM_ERROR("Writing DIP with CTL reg disabled\n");
198 	I915_WRITE(reg, val);
214 	I915_WRITE(reg, val);
215 	POSTING_READ(reg);
226 	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
228 	u32 val = I915_READ(reg);
231 		DRM_ERROR("Writing DIP with CTL reg disabled\n");
241 	I915_WRITE(reg, val);
257 	I915_WRITE(reg, val);
258 	POSTING_READ(reg);
269 	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
271 	u32 val = I915_READ(reg);
274 		DRM_ERROR("Writing DIP with CTL reg disabled\n");
281 	I915_WRITE(reg, val);
297 	I915_WRITE(reg, val);
298 	POSTING_READ(reg);
391 	u32 reg = VIDEO_DIP_CTL;
392 	u32 val = I915_READ(reg);
412 		I915_WRITE(reg, val);
413 		POSTING_READ(reg);
432 			I915_WRITE(reg, val);
433 			POSTING_READ(reg);
442 	I915_WRITE(reg, val);
443 	POSTING_READ(reg);
456 	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
457 	u32 val = I915_READ(reg);
469 		I915_WRITE(reg, val);
470 		POSTING_READ(reg);
492 			I915_WRITE(reg, val);
493 			POSTING_READ(reg);
503 	I915_WRITE(reg, val);
504 	POSTING_READ(reg);
516 	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
517 	u32 val = I915_READ(reg);
528 		I915_WRITE(reg, val);
529 		POSTING_READ(reg);
538 	I915_WRITE(reg, val);
539 	POSTING_READ(reg);
551 	u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
552 	u32 val = I915_READ(reg);
563 		I915_WRITE(reg, val);
564 		POSTING_READ(reg);
572 	I915_WRITE(reg, val);
573 	POSTING_READ(reg);
585 	u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
586 	u32 val = I915_READ(reg);
591 		I915_WRITE(reg, 0);
592 		POSTING_READ(reg);
599 	I915_WRITE(reg, val);
600 	POSTING_READ(reg);