Lines Matching refs:RADEON_READ
827 return (RADEON_READ(RADEON_CLOCK_CNTL_DATA));
833 return (RADEON_READ(RADEON_PCIE_DATA));
840 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
842 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
844 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
846 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
848 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
850 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
852 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
854 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
869 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
874 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) &
895 int slots = (RADEON_READ(RADEON_RBBM_STATUS) &
922 if (!(RADEON_READ(RADEON_RBBM_STATUS) &
991 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
1045 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1074 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1085 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1095 (void) RADEON_READ(RADEON_RBBM_SOFT_RESET);
1104 (void) RADEON_READ(RADEON_RBBM_SOFT_RESET);
1162 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1207 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1217 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1290 RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
1335 tmp = RADEON_READ(RADEON_AIC_CNTL);
1562 dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION) &
1565 ((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
1620 RADEON_READ(RADEON_CONFIG_APER_SIZE);