Lines Matching defs:ring
1048 dev_priv->ring.tail = cur_read_ptr;
1110 /* Reset the CP ring */
1161 /* Initialize the ring buffer's read and write pointers */
1165 dev_priv->ring.tail = cur_read_ptr;
1183 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1188 /* Set ring buffer size */
1191 dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1193 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1204 * We simply put this behind the ring read pointer, this works
1408 * We don't support anything other than bus-mastering ring mode,
1409 * but the ring can be in either AGP or PCI space for the ring
1491 DRM_ERROR("could not find cp ring region, offset=0x%lx\n",
1498 DRM_ERROR("could not find ring read pointer, offset=0x%lx\n",
1637 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1638 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle +
1640 dev_priv->ring.size = init->ring_size;
1641 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1643 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof (u32)) - 1;
1645 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1982 /* Just reset the CP ring. Called as part of an X Server engine reset. */
2169 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2176 ring->space = (head - ring->tail) * sizeof (u32);
2177 if (ring->space <= 0)
2178 ring->space += ring->size;
2179 if (ring->space > n)