Lines Matching defs:dev_priv
824 drm_radeon_private_t *dev_priv = dev->dev_private;
830 static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
837 static void radeon_status(drm_radeon_private_t *dev_priv)
862 static int radeon_do_pixcache_flush(drm_radeon_private_t *dev_priv)
867 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
873 for (i = 0; i < dev_priv->usec_timeout; i++) {
883 radeon_status(dev_priv);
888 static int radeon_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
892 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
894 for (i = 0; i < dev_priv->usec_timeout; i++) {
904 dev_priv->usec_timeout);
906 radeon_status(dev_priv);
911 static int radeon_do_wait_for_idle(drm_radeon_private_t *dev_priv)
915 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
917 ret = radeon_do_wait_for_fifo(dev_priv, 64);
921 for (i = 0; i < dev_priv->usec_timeout; i++) {
924 (void) radeon_do_pixcache_flush(dev_priv);
931 dev_priv->usec_timeout);
934 radeon_status(dev_priv);
944 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
948 (void) radeon_do_wait_for_idle(dev_priv);
952 if (dev_priv->microcode_version == UCODE_R200) {
960 } else if (dev_priv->microcode_version == UCODE_R300) {
984 static void radeon_do_cp_flush(drm_radeon_private_t *dev_priv)
998 radeon_do_cp_idle(drm_radeon_private_t *dev_priv)
1011 return (radeon_do_wait_for_idle(dev_priv));
1015 static void radeon_do_cp_start(drm_radeon_private_t *dev_priv)
1019 (void) radeon_do_wait_for_idle(dev_priv);
1021 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1023 dev_priv->cp_running = 1;
1040 static void radeon_do_cp_reset(drm_radeon_private_t *dev_priv)
1047 SET_RING_HEAD(dev_priv, cur_read_ptr);
1048 dev_priv->ring.tail = cur_read_ptr;
1056 static void radeon_do_cp_stop(drm_radeon_private_t *dev_priv)
1062 dev_priv->cp_running = 0;
1068 drm_radeon_private_t *dev_priv = dev->dev_private;
1072 (void) radeon_do_pixcache_flush(dev_priv);
1111 radeon_do_cp_reset(dev_priv);
1114 dev_priv->cp_running = 0;
1123 radeon_cp_init_ring_buffer(drm_device_t *dev, drm_radeon_private_t *dev_priv)
1135 if (!dev_priv->new_memmap)
1137 ((dev_priv->gart_vm_start - 1) & 0xffff0000) |
1138 (dev_priv->fb_location >> 16));
1141 if (dev_priv->flags & RADEON_IS_AGP) {
1144 (((dev_priv->gart_vm_start - 1 +
1145 dev_priv->gart_size) & 0xffff0000) |
1146 (dev_priv->gart_vm_start >> 16)));
1148 ring_start = dev_priv->cp_ring->offset -
1149 dev->agp->base + dev_priv->gart_vm_start;
1152 ring_start = (dev_priv->cp_ring->offset -
1154 dev_priv->gart_vm_start);
1164 SET_RING_HEAD(dev_priv, cur_read_ptr);
1165 dev_priv->ring.tail = cur_read_ptr;
1168 if (dev_priv->flags & RADEON_IS_AGP) {
1170 dev_priv->ring_rptr->offset -
1171 dev->agp->base + dev_priv->gart_vm_start);
1178 tmp_ofs = dev_priv->ring_rptr->offset -
1191 dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1193 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1197 dev_priv->writeback_works = 0;
1210 dev_priv->scratch = ((__volatile__ u32 *)
1211 dev_priv->ring_rptr->handle +
1220 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1221 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1223 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1225 dev_priv->sarea_priv->last_dispatch);
1227 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1228 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1230 (void) radeon_do_wait_for_idle(dev_priv);
1241 static void radeon_test_writeback(drm_radeon_private_t *dev_priv)
1250 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1253 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1254 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1260 tmp = dev_priv->usec_timeout;
1262 if (tmp < dev_priv->usec_timeout) {
1263 dev_priv->writeback_works = 1;
1266 dev_priv->writeback_works = 0;
1270 dev_priv->writeback_works = 0;
1281 dev_priv->writeback_works = 0;
1284 if (!dev_priv->writeback_works) {
1297 static void radeon_set_pciegart(drm_radeon_private_t *dev_priv, int on)
1299 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1303 dev_priv->gart_vm_start,
1304 (long)dev_priv->gart_info.bus_addr,
1305 dev_priv->gart_size);
1307 dev_priv->gart_vm_start);
1309 dev_priv->gart_info.bus_addr);
1311 dev_priv->gart_vm_start);
1313 dev_priv->gart_vm_start + dev_priv->gart_size - 1);
1326 static void radeon_set_pcigart(drm_radeon_private_t *dev_priv, int on)
1330 if (dev_priv->flags & RADEON_IS_PCIE) {
1331 radeon_set_pciegart(dev_priv, on);
1342 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1345 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1346 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start +
1347 dev_priv->gart_size - 1);
1360 drm_radeon_private_t *dev_priv = dev->dev_private;
1363 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1370 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1372 dev_priv->flags &= ~RADEON_IS_AGP;
1373 } else if (!(dev_priv->flags &
1377 dev_priv->flags |= RADEON_IS_AGP;
1380 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1386 dev_priv->usec_timeout = init->usec_timeout;
1387 if (dev_priv->usec_timeout < 1 ||
1388 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1395 dev_priv->microcode_version = UCODE_R200;
1398 dev_priv->microcode_version = UCODE_R300;
1401 dev_priv->microcode_version = UCODE_R100;
1404 dev_priv->do_boxes = 0;
1405 dev_priv->cp_mode = init->cp_mode;
1421 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1425 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1428 dev_priv->front_offset = init->front_offset;
1429 dev_priv->front_pitch = init->front_pitch;
1430 dev_priv->back_offset = init->back_offset;
1431 dev_priv->back_pitch = init->back_pitch;
1435 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1439 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1442 dev_priv->depth_offset = init->depth_offset;
1443 dev_priv->depth_pitch = init->depth_pitch;
1451 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1452 (dev_priv->color_fmt << 10) |
1453 (dev_priv->microcode_version ==
1456 dev_priv->depth_clear.rb3d_zstencilcntl =
1457 (dev_priv->depth_fmt |
1464 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1478 dev_priv->ring_offset = init->ring_offset;
1479 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1480 dev_priv->buffers_offset = init->buffers_offset;
1481 dev_priv->gart_textures_offset = init->gart_textures_offset;
1483 if (!dev_priv->sarea) {
1489 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1490 if (!dev_priv->cp_ring) {
1496 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1497 if (!dev_priv->ring_rptr) {
1513 dev_priv->gart_textures =
1515 if (!dev_priv->gart_textures) {
1523 dev_priv->sarea_priv = (drm_radeon_sarea_t *)(uintptr_t)
1524 ((u8 *)(uintptr_t)dev_priv->sarea->handle +
1528 if (dev_priv->flags & RADEON_IS_AGP) {
1529 drm_core_ioremap(dev_priv->cp_ring, dev);
1530 drm_core_ioremap(dev_priv->ring_rptr, dev);
1532 if (!dev_priv->cp_ring->handle ||
1533 !dev_priv->ring_rptr->handle ||
1538 dev_priv->cp_ring->handle,
1539 dev_priv->ring_rptr->handle,
1547 dev_priv->cp_ring->handle =
1548 (void *)(intptr_t)dev_priv->cp_ring->offset;
1549 dev_priv->ring_rptr->handle =
1550 (void *)(intptr_t)dev_priv->ring_rptr->offset;
1554 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1555 dev_priv->cp_ring->handle);
1556 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1557 dev_priv->ring_rptr->handle);
1562 dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION) &
1564 dev_priv->fb_size =
1566 - dev_priv->fb_location;
1568 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1569 ((dev_priv->front_offset + dev_priv->fb_location) >> 10));
1571 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1572 ((dev_priv->back_offset + dev_priv->fb_location) >> 10));
1574 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1575 ((dev_priv->depth_offset + dev_priv->fb_location) >> 10));
1577 dev_priv->gart_size = init->gart_size;
1580 if (dev_priv->new_memmap) {
1591 if (dev_priv->flags & RADEON_IS_AGP) {
1594 if ((base + dev_priv->gart_size - 1) >=
1595 dev_priv->fb_location &&
1596 base < (dev_priv->fb_location +
1597 dev_priv->fb_size - 1)) {
1606 base = dev_priv->fb_location + dev_priv->fb_size;
1607 if (base < dev_priv->fb_location ||
1608 ((base + dev_priv->gart_size) &
1610 base = dev_priv->fb_location -
1611 dev_priv->gart_size;
1613 dev_priv->gart_vm_start = base & 0xffc00000u;
1614 if (dev_priv->gart_vm_start != base)
1616 base, dev_priv->gart_vm_start);
1619 dev_priv->gart_vm_start = dev_priv->fb_location +
1624 if (dev_priv->flags & RADEON_IS_AGP)
1625 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset -
1626 dev->agp->base + dev_priv->gart_vm_start);
1629 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset -
1630 (unsigned long)dev->sg->virtual + dev_priv->gart_vm_start);
1632 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1633 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1634 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1635 dev_priv->gart_buffers_offset);
1637 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1638 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle +
1640 dev_priv->ring.size = init->ring_size;
1641 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1643 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof (u32)) - 1;
1645 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1648 if (dev_priv->flags & RADEON_IS_AGP) {
1650 radeon_set_pcigart(dev_priv, 0);
1655 if (dev_priv->pcigart_offset) {
1656 dev_priv->gart_info.bus_addr =
1657 dev_priv->pcigart_offset + dev_priv->fb_location;
1658 dev_priv->gart_info.mapping.offset =
1659 dev_priv->gart_info.bus_addr;
1660 dev_priv->gart_info.mapping.size =
1663 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1664 dev_priv->gart_info.addr =
1665 dev_priv->gart_info.mapping.handle;
1667 dev_priv->gart_info.is_pcie =
1668 !!(dev_priv->flags & RADEON_IS_PCIE);
1669 dev_priv->gart_info.gart_table_location =
1673 dev_priv->gart_info.addr, dev_priv->pcigart_offset);
1675 dev_priv->gart_info.gart_table_location =
1677 dev_priv->gart_info.addr = NULL;
1678 dev_priv->gart_info.bus_addr = 0;
1679 if (dev_priv->flags & RADEON_IS_PCIE) {
1687 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1694 radeon_set_pcigart(dev_priv, 1);
1697 radeon_cp_load_microcode(dev_priv);
1698 radeon_cp_init_ring_buffer(dev, dev_priv);
1700 dev_priv->last_buf = 0;
1703 radeon_test_writeback(dev_priv);
1710 drm_radeon_private_t *dev_priv = dev->dev_private;
1721 if (dev_priv->flags & RADEON_IS_AGP) {
1722 if (dev_priv->cp_ring != NULL) {
1723 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1724 dev_priv->cp_ring = NULL;
1726 if (dev_priv->ring_rptr != NULL) {
1727 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1728 dev_priv->ring_rptr = NULL;
1738 if (dev_priv->gart_info.bus_addr) {
1740 radeon_set_pcigart(dev_priv, 0);
1741 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1745 if (dev_priv->gart_info.gart_table_location ==
1747 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1748 dev_priv->gart_info.addr = 0;
1752 (void) memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1767 drm_radeon_private_t *dev_priv = dev->dev_private;
1769 if (!dev_priv) {
1777 if (dev_priv->flags & RADEON_IS_AGP) {
1779 radeon_set_pcigart(dev_priv, 0);
1784 radeon_set_pcigart(dev_priv, 1);
1787 radeon_cp_load_microcode(dev_priv);
1788 radeon_cp_init_ring_buffer(dev, dev_priv);
1859 drm_radeon_private_t *dev_priv = dev->dev_private;
1863 if (dev_priv->cp_running) {
1866 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1868 dev_priv->cp_mode);
1872 radeon_do_cp_start(dev_priv);
1886 drm_radeon_private_t *dev_priv = dev->dev_private;
1894 if (!dev_priv->cp_running)
1902 radeon_do_cp_flush(dev_priv);
1910 ret = radeon_do_cp_idle(dev_priv);
1920 radeon_do_cp_stop(dev_priv);
1931 drm_radeon_private_t *dev_priv = dev->dev_private;
1934 if (dev_priv) {
1935 if (dev_priv->cp_running) {
1937 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1954 radeon_do_cp_stop(dev_priv);
1960 if (dev_priv->mmio)
1963 if (dev_priv->mmio) { /* remove all surfaces */
1974 radeon_mem_takedown(&(dev_priv->gart_heap));
1975 radeon_mem_takedown(&(dev_priv->fb_heap));
1988 drm_radeon_private_t *dev_priv = dev->dev_private;
1992 if (!dev_priv) {
1997 radeon_do_cp_reset(dev_priv);
2000 dev_priv->cp_running = 0;
2010 drm_radeon_private_t *dev_priv = dev->dev_private;
2014 return (radeon_do_cp_idle(dev_priv));
2076 drm_radeon_private_t *dev_priv = dev->dev_private;
2082 if (++dev_priv->last_buf >= dma->buf_count)
2083 dev_priv->last_buf = 0;
2085 start = dev_priv->last_buf;
2087 for (t = 0; t < dev_priv->usec_timeout; t++) {
2095 dev_priv->stats.requested_bufs++;
2104 dev_priv->stats.freelist_loops++;
2117 drm_radeon_private_t *dev_priv = dev->dev_private;
2122 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
2124 if (++dev_priv->last_buf >= dma->buf_count)
2125 dev_priv->last_buf = 0;
2127 start = dev_priv->last_buf;
2128 dev_priv->stats.freelist_loops++;
2136 dev_priv->stats.requested_bufs++;
2152 drm_radeon_private_t *dev_priv = dev->dev_private;
2155 dev_priv->last_buf = 0;
2167 radeon_wait_ring(drm_radeon_private_t *dev_priv, int n)
2169 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2171 u32 last_head = GET_RING_HEAD(dev_priv);
2173 for (i = 0; i < dev_priv->usec_timeout; i++) {
2174 u32 head = GET_RING_HEAD(dev_priv);
2182 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2194 radeon_status(dev_priv);
2304 drm_radeon_private_t *dev_priv;
2307 dev_priv = drm_alloc(sizeof (drm_radeon_private_t), DRM_MEM_DRIVER);
2308 if (dev_priv == NULL)
2311 (void) memset(dev_priv, 0, sizeof (drm_radeon_private_t));
2312 dev->dev_private = (void *)dev_priv;
2313 dev_priv->flags = (int)flags;
2323 dev_priv->flags |= RADEON_HAS_HIERZ;
2331 dev_priv->flags |= RADEON_IS_AGP;
2333 dev_priv->flags |= RADEON_IS_PCIE;
2335 dev_priv->flags |= RADEON_IS_PCI;
2349 drm_radeon_private_t *dev_priv = dev->dev_private;
2351 /* dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; */
2355 _DRM_READ_ONLY, &dev_priv->mmio);
2377 drm_radeon_private_t *dev_priv = dev->dev_private;
2380 drm_free(dev_priv, sizeof (*dev_priv), DRM_MEM_DRIVER);