Lines Matching refs:hw
71 * Some member variables of the hw struct have been eliminated
88 static struct e1000_hw hw;
100 static int e1000_setup_link(struct e1000_hw *hw);
101 static int e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
102 static int e1000_setup_copper_link(struct e1000_hw *hw);
103 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
104 static void e1000_config_collision_dist(struct e1000_hw *hw);
105 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
106 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
107 static int e1000_check_for_link(struct e1000_hw *hw);
108 static int e1000_wait_autoneg(struct e1000_hw *hw);
109 static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex);
110 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
111 static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
112 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
113 static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
114 static void e1000_phy_hw_reset(struct e1000_hw *hw);
115 static int e1000_phy_reset(struct e1000_hw *hw);
116 static int e1000_detect_gig_phy(struct e1000_hw *hw);
171 e1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
177 e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
182 static inline void e1000_pci_set_mwi(struct e1000_hw *hw)
184 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
187 static inline void e1000_pci_clear_mwi(struct e1000_hw *hw)
189 pci_write_config_word(hw->pdev, PCI_COMMAND,
190 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
196 * hw - Struct containing variables accessed by shared code
200 e1000_raise_ee_clk(struct e1000_hw *hw,
207 E1000_WRITE_REG(hw, EECD, *eecd);
208 E1000_WRITE_FLUSH(hw);
209 udelay(hw->eeprom.delay_usec);
215 * hw - Struct containing variables accessed by shared code
219 e1000_lower_ee_clk(struct e1000_hw *hw,
226 E1000_WRITE_REG(hw, EECD, *eecd);
227 E1000_WRITE_FLUSH(hw);
228 udelay(hw->eeprom.delay_usec);
234 * hw - Struct containing variables accessed by shared code
239 e1000_shift_out_ee_bits(struct e1000_hw *hw,
243 struct e1000_eeprom_info *eeprom = &hw->eeprom;
252 eecd = E1000_READ_REG(hw, EECD);
269 E1000_WRITE_REG(hw, EECD, eecd);
270 E1000_WRITE_FLUSH(hw);
274 e1000_raise_ee_clk(hw, &eecd);
275 e1000_lower_ee_clk(hw, &eecd);
283 E1000_WRITE_REG(hw, EECD, eecd);
289 * hw - Struct containing variables accessed by shared code
292 e1000_shift_in_ee_bits(struct e1000_hw *hw,
306 eecd = E1000_READ_REG(hw, EECD);
313 e1000_raise_ee_clk(hw, &eecd);
315 eecd = E1000_READ_REG(hw, EECD);
321 e1000_lower_ee_clk(hw, &eecd);
330 * hw - Struct containing variables accessed by shared code
336 e1000_acquire_eeprom(struct e1000_hw *hw)
338 struct e1000_eeprom_info *eeprom = &hw->eeprom;
341 eecd = E1000_READ_REG(hw, EECD);
344 if(hw->mac_type > e1000_82544) {
346 E1000_WRITE_REG(hw, EECD, eecd);
347 eecd = E1000_READ_REG(hw, EECD);
352 eecd = E1000_READ_REG(hw, EECD);
356 E1000_WRITE_REG(hw, EECD, eecd);
367 E1000_WRITE_REG(hw, EECD, eecd);
371 E1000_WRITE_REG(hw, EECD, eecd);
375 E1000_WRITE_REG(hw, EECD, eecd);
385 * hw - Struct containing variables accessed by shared code
388 e1000_standby_eeprom(struct e1000_hw *hw)
390 struct e1000_eeprom_info *eeprom = &hw->eeprom;
393 eecd = E1000_READ_REG(hw, EECD);
399 E1000_WRITE_REG(hw, EECD, eecd);
400 E1000_WRITE_FLUSH(hw);
405 E1000_WRITE_REG(hw, EECD, eecd);
406 E1000_WRITE_FLUSH(hw);
411 E1000_WRITE_REG(hw, EECD, eecd);
412 E1000_WRITE_FLUSH(hw);
417 E1000_WRITE_REG(hw, EECD, eecd);
418 E1000_WRITE_FLUSH(hw);
423 E1000_WRITE_REG(hw, EECD, eecd);
424 E1000_WRITE_FLUSH(hw);
427 E1000_WRITE_REG(hw, EECD, eecd);
428 E1000_WRITE_FLUSH(hw);
436 * hw - Struct containing variables accessed by shared code
439 e1000_release_eeprom(struct e1000_hw *hw)
443 eecd = E1000_READ_REG(hw, EECD);
445 if (hw->eeprom.type == e1000_eeprom_spi) {
449 E1000_WRITE_REG(hw, EECD, eecd);
451 udelay(hw->eeprom.delay_usec);
452 } else if(hw->eeprom.type == e1000_eeprom_microwire) {
458 E1000_WRITE_REG(hw, EECD, eecd);
462 E1000_WRITE_REG(hw, EECD, eecd);
463 E1000_WRITE_FLUSH(hw);
464 udelay(hw->eeprom.delay_usec);
468 E1000_WRITE_REG(hw, EECD, eecd);
469 E1000_WRITE_FLUSH(hw);
470 udelay(hw->eeprom.delay_usec);
474 if(hw->mac_type > e1000_82544) {
476 E1000_WRITE_REG(hw, EECD, eecd);
483 * hw - Struct containing variables accessed by shared code
486 e1000_spi_eeprom_ready(struct e1000_hw *hw)
498 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
499 hw->eeprom.opcode_bits);
500 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
523 * hw - Struct containing variables accessed by shared code
529 e1000_read_eeprom(struct e1000_hw *hw,
534 struct e1000_eeprom_info *eeprom = &hw->eeprom;
549 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
556 if(e1000_spi_eeprom_ready(hw)) {
557 e1000_release_eeprom(hw);
561 e1000_standby_eeprom(hw);
568 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
569 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
577 word_in = e1000_shift_in_ee_bits(hw, 16);
583 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
585 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
590 data[i] = e1000_shift_in_ee_bits(hw, 16);
591 e1000_standby_eeprom(hw);
596 e1000_release_eeprom(hw);
604 * hw - Struct containing variables accessed by shared code
611 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
619 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
638 * hw - Struct containing variables accessed by shared code
641 e1000_read_mac_addr(struct e1000_hw *hw)
651 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
655 hw->mac_addr[i] = eeprom_data & 0xff;
656 hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
658 if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
659 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
661 hw->mac_addr[5] ^= 1;
668 * hw - Struct containing variables accessed by shared code
675 e1000_init_rx_addrs(struct e1000_hw *hw)
685 addr_low = (hw->mac_addr[0] |
686 (hw->mac_addr[1] << 8) |
687 (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
689 addr_high = (hw->mac_addr[4] |
690 (hw->mac_addr[5] << 8) | E1000_RAH_AV);
692 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
693 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
698 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
699 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
706 * hw - Struct containing variables accessed by shared code
709 e1000_clear_vfta(struct e1000_hw *hw)
714 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
720 * hw - Struct containing variables accessed by shared code
723 void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value){
724 uint32_t io_addr = hw->io_base;
725 uint32_t io_data = hw->io_base + 4;
726 e1000_io_write(hw, io_addr, offset);
727 e1000_io_write(hw, io_data, value);
731 * Set the phy type member in the hw struct.
733 * hw - Struct containing variables accessed by shared code
736 e1000_set_phy_type(struct e1000_hw *hw)
740 switch(hw->phy_id) {
744 hw->phy_type = e1000_phy_m88;
747 hw->phy_type = e1000_phy_igp;
751 hw->phy_type = e1000_phy_undefined;
761 * hw - Struct containing variables accessed by shared code
764 e1000_phy_init_script(struct e1000_hw *hw)
770 if(hw->phy_init_script) {
772 if((hw->mac_type == e1000_82541) ||
773 (hw->mac_type == e1000_82547) ||
774 (hw->mac_type == e1000_82541_rev_2) ||
775 (hw->mac_type == e1000_82547_rev_2)) {
779 e1000_write_phy_reg(hw,0x0000,0x0140);
783 if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
784 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
786 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
788 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
790 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
792 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
794 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
796 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
798 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
800 e1000_write_phy_reg(hw, 0x2010, 0x0008);
802 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
805 e1000_write_phy_reg(hw, 0x0000, 0x3300);
808 if(hw->mac_type == e1000_82547) {
812 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
815 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
830 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
831 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
839 * Set the mac type member in the hw struct.
841 * hw - Struct containing variables accessed by shared code
844 e1000_set_mac_type(struct e1000_hw *hw)
848 switch (hw->device_id) {
850 switch (hw->revision_id) {
852 hw->mac_type = e1000_82542_rev2_0;
855 hw->mac_type = e1000_82542_rev2_1;
864 hw->mac_type = e1000_82543;
870 hw->mac_type = e1000_82544;
877 hw->mac_type = e1000_82540;
881 hw->mac_type = e1000_82545;
886 hw->mac_type = e1000_82545_rev_3;
891 hw->mac_type = e1000_82546;
896 hw->mac_type = e1000_82546_rev_3;
900 hw->mac_type = e1000_82541;
905 hw->mac_type = e1000_82541_rev_2;
908 hw->mac_type = e1000_82547;
911 hw->mac_type = e1000_82547_rev_2;
924 * hw - Struct containing variables accessed by shared code
927 e1000_set_media_type(struct e1000_hw *hw)
933 if(hw->mac_type != e1000_82543) {
935 hw->tbi_compatibility_en = FALSE;
938 switch (hw->device_id) {
941 hw->media_type = e1000_media_type_internal_serdes;
944 if(hw->mac_type >= e1000_82543) {
945 status = E1000_READ_REG(hw, STATUS);
947 hw->media_type = e1000_media_type_fiber;
949 hw->tbi_compatibility_en = FALSE;
951 hw->media_type = e1000_media_type_copper;
955 hw->media_type = e1000_media_type_fiber;
963 * hw - Struct containing variables accessed by shared code
966 e1000_reset_hw(struct e1000_hw *hw)
976 if(hw->mac_type == e1000_82542_rev2_0) {
978 e1000_pci_clear_mwi(hw);
983 E1000_WRITE_REG(hw, IMC, 0xffffffff);
989 E1000_WRITE_REG(hw, RCTL, 0);
990 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
991 E1000_WRITE_FLUSH(hw);
994 hw->tbi_compatibility_on = FALSE;
1001 ctrl = E1000_READ_REG(hw, CTRL);
1004 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1005 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
1016 switch(hw->mac_type) {
1025 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
1030 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
1033 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1041 switch(hw->mac_type) {
1048 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1050 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1051 E1000_WRITE_FLUSH(hw);
1069 if(hw->mac_type >= e1000_82540) {
1070 manc = E1000_READ_REG(hw, MANC);
1072 E1000_WRITE_REG(hw, MANC, manc);
1075 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1076 e1000_phy_init_script(hw);
1081 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1084 icr = E1000_READ_REG(hw, ICR);
1087 if(hw->mac_type == e1000_82542_rev2_0) {
1089 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1091 e1000_pci_set_mwi(hw);
1098 * hw - Struct containing variables accessed by shared code
1107 e1000_init_hw(struct e1000_hw *hw)
1121 e1000_set_media_type(hw);
1125 E1000_WRITE_REG(hw, VET, 0);
1127 e1000_clear_vfta(hw);
1130 if(hw->mac_type == e1000_82542_rev2_0) {
1132 e1000_pci_clear_mwi(hw);
1133 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1134 E1000_WRITE_FLUSH(hw);
1141 e1000_init_rx_addrs(hw);
1144 if(hw->mac_type == e1000_82542_rev2_0) {
1145 E1000_WRITE_REG(hw, RCTL, 0);
1146 E1000_WRITE_FLUSH(hw);
1149 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1151 e1000_pci_set_mwi(hw);
1157 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1164 if(hw->dma_fairness) {
1165 ctrl = E1000_READ_REG(hw, CTRL);
1166 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1170 switch(hw->mac_type) {
1175 if (hw->mac_type >= e1000_82543) {
1177 status = E1000_READ_REG(hw, STATUS);
1184 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
1185 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
1195 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
1202 ret_val = e1000_setup_link(hw);
1205 if(hw->mac_type > e1000_82544) {
1206 ctrl = E1000_READ_REG(hw, TXDCTL);
1208 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1217 e1000_clear_hw_cntrs(hw);
1226 * hw - Struct containing variables accessed by shared code.
1229 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1236 if(hw->media_type != e1000_media_type_internal_serdes)
1239 switch(hw->mac_type) {
1247 if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
1255 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
1266 * hw - Struct containing variables accessed by shared code
1275 e1000_setup_link(struct e1000_hw *hw)
1288 * control setting, then the variable hw->fc will
1291 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
1296 if(hw->fc == e1000_fc_default) {
1298 hw->fc = e1000_fc_none;
1301 hw->fc = e1000_fc_tx_pause;
1303 hw->fc = e1000_fc_full;
1310 if(hw->mac_type == e1000_82542_rev2_0)
1311 hw->fc &= (~e1000_fc_tx_pause);
1315 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1317 if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
1319 hw->fc &= (~e1000_fc_rx_pause);
1322 hw->original_fc = hw->fc;
1325 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1334 if(hw->mac_type == e1000_82543) {
1337 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1341 ret_val = (hw->media_type == e1000_media_type_copper) ?
1342 e1000_setup_copper_link(hw) :
1343 e1000_setup_fiber_serdes_link(hw);
1355 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1356 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1357 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1359 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1361 E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
1370 if(!(hw->fc & e1000_fc_tx_pause)) {
1371 E1000_WRITE_REG(hw, FCRTL, 0);
1372 E1000_WRITE_REG(hw, FCRTH, 0);
1378 if(hw->fc_send_xon) {
1379 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1380 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1382 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1383 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1386 E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
1387 E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
1396 * hw - Struct containing variables accessed by shared code
1403 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1420 ctrl = E1000_READ_REG(hw, CTRL);
1421 if(hw->media_type == e1000_media_type_fiber)
1422 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1424 if((ret_val = e1000_adjust_serdes_amplitude(hw)))
1432 if((ret_val = e1000_set_vco_speed(hw)))
1436 e1000_config_collision_dist(hw);
1453 switch (hw->fc) {
1491 E1000_WRITE_REG(hw, TXCW, txcw);
1492 E1000_WRITE_REG(hw, CTRL, ctrl);
1493 E1000_WRITE_FLUSH(hw);
1495 hw->txcw = txcw;
1504 if(hw->media_type == e1000_media_type_internal_serdes ||
1505 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1509 status = E1000_READ_REG(hw, STATUS);
1514 hw->autoneg_failed = 1;
1520 if((ret_val = e1000_check_for_link(hw))) {
1524 hw->autoneg_failed = 0;
1526 hw->autoneg_failed = 0;
1538 * hw - Struct containing variables accessed by shared code
1541 e1000_setup_copper_link(struct e1000_hw *hw)
1550 ctrl = E1000_READ_REG(hw, CTRL);
1555 if(hw->mac_type > e1000_82543) {
1558 E1000_WRITE_REG(hw, CTRL, ctrl);
1561 E1000_WRITE_REG(hw, CTRL, ctrl);
1562 e1000_phy_hw_reset(hw);
1566 if((ret_val = e1000_detect_gig_phy(hw))) {
1570 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1572 if(hw->mac_type <= e1000_82543 ||
1573 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1575 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1576 hw->phy_reset_disable = FALSE;
1578 if(!hw->phy_reset_disable) {
1580 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
1582 if (hw->phy_type == e1000_phy_igp) {
1584 if((ret_val = e1000_phy_reset(hw))) {
1594 if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
1600 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1604 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1605 hw->dsp_config_state = e1000_dsp_config_disabled;
1609 hw->mdix = 1;
1612 hw->dsp_config_state = e1000_dsp_config_enabled;
1615 switch (hw->mdix) {
1628 if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1633 e1000_ms_type phy_ms_setting = hw->master_slave;
1635 if(hw->ffe_config_state == e1000_ffe_config_active)
1636 hw->ffe_config_state = e1000_ffe_config_enabled;
1638 if(hw->dsp_config_state == e1000_dsp_config_activated)
1639 hw->dsp_config_state = e1000_dsp_config_enabled;
1645 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1647 if((ret_val = e1000_read_phy_reg(hw,
1652 if((ret_val = e1000_write_phy_reg(hw,
1657 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1661 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1666 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1672 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1693 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1698 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1714 switch (hw->mdix) {
1740 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1747 if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1754 if (hw->phy_revision < M88E1011_I_REV_4) {
1761 if((ret_val = e1000_write_phy_reg(hw,
1768 if((ret_val = e1000_phy_reset(hw))) {
1791 /* Perform some bounds checking on the hw->autoneg_advertised
1794 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1799 if(hw->autoneg_advertised == 0)
1800 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1803 if((ret_val = e1000_phy_setup_autoneg(hw))) {
1812 if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
1816 if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
1823 if(hw->wait_autoneg_complete) {
1824 if((ret_val = e1000_wait_autoneg(hw))) {
1833 if((ret_val = e1000_wait_autoneg(hw))) {
1838 } /* !hw->phy_reset_disable */
1844 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1846 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1858 if(hw->mac_type >= e1000_82544) {
1859 e1000_config_collision_dist(hw);
1861 if((ret_val = e1000_config_mac_to_phy(hw))) {
1866 if((ret_val = e1000_config_fc_after_link_up(hw))) {
1871 if(hw->phy_type == e1000_phy_igp) {
1872 if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
1891 * hw - Struct containing variables accessed by shared code
1894 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1903 if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1908 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
1925 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1928 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1934 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1940 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1946 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1952 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1957 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1978 switch (hw->fc) {
1993 *hw's ability to send PAUSE frames.
2015 if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
2021 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
2030 * hw - Struct containing variables accessed by shared code
2036 e1000_config_collision_dist(struct e1000_hw *hw)
2040 tctl = E1000_READ_REG(hw, TCTL);
2045 E1000_WRITE_REG(hw, TCTL, tctl);
2046 E1000_WRITE_FLUSH(hw);
2052 * hw - Struct containing variables accessed by shared code
2059 e1000_config_mac_to_phy(struct e1000_hw *hw)
2070 ctrl = E1000_READ_REG(hw, CTRL);
2077 if (hw->phy_type == e1000_phy_igp) {
2078 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
2085 e1000_config_collision_dist(hw);
2097 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
2104 e1000_config_collision_dist(hw);
2115 E1000_WRITE_REG(hw, CTRL, ctrl);
2122 * hw - Struct containing variables accessed by shared code
2131 e1000_force_mac_fc(struct e1000_hw *hw)
2138 ctrl = E1000_READ_REG(hw, CTRL);
2146 * according to the "hw->fc" parameter.
2158 switch (hw->fc) {
2179 if(hw->mac_type == e1000_82542_rev2_0)
2182 E1000_WRITE_REG(hw, CTRL, ctrl);
2189 * hw - Struct containing variables accessed by shared code
2198 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2213 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2214 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed))) {
2215 if((ret_val = e1000_force_mac_fc(hw))) {
2226 if(hw->media_type == e1000_media_type_copper) {
2231 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
2233 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
2243 if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2246 if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2293 if(hw->original_fc == e1000_fc_full) {
2294 hw->fc = e1000_fc_full;
2296 if(hw->fc == e1000_fc_full) {
2300 hw->fc = e1000_fc_rx_pause;
2316 hw->fc = e1000_fc_tx_pause;
2331 hw->fc = e1000_fc_rx_pause;
2355 else if(hw->original_fc == e1000_fc_none ||
2356 hw->original_fc == e1000_fc_tx_pause) {
2358 else if(hw->fc == e1000_fc_none)
2360 else if(hw->fc == e1000_fc_tx_pause) {
2362 hw->fc = e1000_fc_none;
2365 hw->fc = e1000_fc_rx_pause;
2373 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2376 hw->fc = e1000_fc_none;
2381 if((ret_val = e1000_force_mac_fc(hw))) {
2395 * hw - Struct containing variables accessed by shared code
2400 e1000_check_for_link(struct e1000_hw *hw)
2417 if(hw->media_type == e1000_media_type_fiber)
2418 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2420 ctrl = E1000_READ_REG(hw, CTRL);
2421 status = E1000_READ_REG(hw, STATUS);
2422 rxcw = E1000_READ_REG(hw, RXCW);
2431 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2433 if(hw->media_type == e1000_media_type_copper) {
2440 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2442 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2447 hw->get_link_status = FALSE;
2462 if(hw->mac_type >= e1000_82544)
2463 e1000_config_collision_dist(hw);
2465 if((ret_val = e1000_config_mac_to_phy(hw))) {
2475 if((ret_val = e1000_config_fc_after_link_up(hw))) {
2489 if(hw->tbi_compatibility_en) {
2490 if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2501 if(hw->tbi_compatibility_on) {
2503 rctl = E1000_READ_REG(hw, RCTL);
2505 E1000_WRITE_REG(hw, RCTL, rctl);
2506 hw->tbi_compatibility_on = FALSE;
2514 if(!hw->tbi_compatibility_on) {
2515 hw->tbi_compatibility_on = TRUE;
2516 rctl = E1000_READ_REG(hw, RCTL);
2518 E1000_WRITE_REG(hw, RCTL, rctl);
2530 else if((((hw->media_type == e1000_media_type_fiber) &&
2532 (hw->media_type == e1000_media_type_internal_serdes)) &&
2535 if(hw->autoneg_failed == 0) {
2536 hw->autoneg_failed = 1;
2542 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2545 ctrl = E1000_READ_REG(hw, CTRL);
2547 E1000_WRITE_REG(hw, CTRL, ctrl);
2550 if((ret_val = e1000_config_fc_after_link_up(hw))) {
2560 else if(((hw->media_type == e1000_media_type_fiber) ||
2561 (hw->media_type == e1000_media_type_internal_serdes)) &&
2565 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2566 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2572 else if((hw->media_type == e1000_media_type_internal_serdes) &&
2573 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2576 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2578 hw->serdes_link_down = FALSE;
2582 hw->serdes_link_down = TRUE;
2593 * hw - Struct containing variables accessed by shared code
2598 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2606 if(hw->mac_type >= e1000_82543) {
2607 status = E1000_READ_REG(hw, STATUS);
2636 * hw - Struct containing variables accessed by shared code
2639 e1000_wait_autoneg(struct e1000_hw *hw)
2653 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2655 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2670 * hw - Struct containing variables accessed by shared code
2674 e1000_raise_mdi_clk(struct e1000_hw *hw,
2680 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2681 E1000_WRITE_FLUSH(hw);
2688 * hw - Struct containing variables accessed by shared code
2692 e1000_lower_mdi_clk(struct e1000_hw *hw,
2698 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2699 E1000_WRITE_FLUSH(hw);
2706 * hw - Struct containing variables accessed by shared code
2713 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2727 ctrl = E1000_READ_REG(hw, CTRL);
2741 E1000_WRITE_REG(hw, CTRL, ctrl);
2742 E1000_WRITE_FLUSH(hw);
2746 e1000_raise_mdi_clk(hw, &ctrl);
2747 e1000_lower_mdi_clk(hw, &ctrl);
2756 * hw - Struct containing variables accessed by shared code
2761 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2774 ctrl = E1000_READ_REG(hw, CTRL);
2780 E1000_WRITE_REG(hw, CTRL, ctrl);
2781 E1000_WRITE_FLUSH(hw);
2787 e1000_raise_mdi_clk(hw, &ctrl);
2788 e1000_lower_mdi_clk(hw, &ctrl);
2792 e1000_raise_mdi_clk(hw, &ctrl);
2793 ctrl = E1000_READ_REG(hw, CTRL);
2796 e1000_lower_mdi_clk(hw, &ctrl);
2799 e1000_raise_mdi_clk(hw, &ctrl);
2800 e1000_lower_mdi_clk(hw, &ctrl);
2809 * hw - Struct containing variables accessed by shared code
2813 e1000_read_phy_reg(struct e1000_hw *hw,
2821 if(hw->phy_type == e1000_phy_igp &&
2823 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2828 ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2835 e1000_read_phy_reg_ex(struct e1000_hw *hw,
2850 if(hw->mac_type > e1000_82543) {
2859 E1000_WRITE_REG(hw, MDIC, mdic);
2864 mdic = E1000_READ_REG(hw, MDIC);
2881 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2897 e1000_shift_out_mdi_bits(hw, mdic, 14);
2903 *phy_data = e1000_shift_in_mdi_bits(hw);
2911 * hw - Struct containing variables accessed by shared code
2916 e1000_write_phy_reg(struct e1000_hw *hw,
2924 if(hw->phy_type == e1000_phy_igp &&
2926 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2931 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2938 e1000_write_phy_reg_ex(struct e1000_hw *hw,
2953 if(hw->mac_type > e1000_82543) {
2963 E1000_WRITE_REG(hw, MDIC, mdic);
2968 mdic = E1000_READ_REG(hw, MDIC);
2981 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2994 e1000_shift_out_mdi_bits(hw, mdic, 32);
3003 * hw - Struct containing variables accessed by shared code
3006 e1000_phy_hw_reset(struct e1000_hw *hw)
3014 if(hw->mac_type > e1000_82543) {
3018 ctrl = E1000_READ_REG(hw, CTRL);
3019 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3020 E1000_WRITE_FLUSH(hw);
3022 E1000_WRITE_REG(hw, CTRL, ctrl);
3023 E1000_WRITE_FLUSH(hw);
3028 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3031 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3032 E1000_WRITE_FLUSH(hw);
3035 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3036 E1000_WRITE_FLUSH(hw);
3044 * hw - Struct containing variables accessed by shared code
3049 e1000_phy_reset(struct e1000_hw *hw)
3056 if(hw->mac_type != e1000_82541_rev_2) {
3057 if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
3061 if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
3065 } else e1000_phy_hw_reset(hw);
3067 if(hw->phy_type == e1000_phy_igp)
3068 e1000_phy_init_script(hw);
3076 * hw - Struct containing variables accessed by shared code
3079 e1000_detect_gig_phy(struct e1000_hw *hw)
3088 if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
3091 hw->phy_id = (uint32_t) (phy_id_high << 16);
3093 if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
3096 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3098 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3101 switch(hw->mac_type) {
3103 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3106 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3113 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3119 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3122 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3125 phy_init_status = e1000_set_phy_type(hw);
3128 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3131 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3136 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3139 * hw - Struct containing variables accessed by shared code
3142 e1000_init_eeprom_params(struct e1000_hw *hw)
3144 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3145 uint32_t eecd = E1000_READ_REG(hw, EECD);
3150 switch (hw->mac_type) {
3219 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
3254 e1000_reset(struct e1000_hw *hw)
3261 if(hw->mac_type < e1000_82547) {
3266 E1000_WRITE_REG(hw, PBA, pba);
3270 hw->fc_high_water = FC_DEFAULT_HI_THRESH;
3271 hw->fc_low_water = FC_DEFAULT_LO_THRESH;
3272 hw->fc_pause_time = FC_DEFAULT_TX_TIMER;
3273 hw->fc_send_xon = 1;
3274 hw->fc = hw->original_fc;
3277 e1000_reset_hw(hw);
3278 if(hw->mac_type >= e1000_82544)
3279 E1000_WRITE_REG(hw, WUC, 0);
3280 return e1000_init_hw(hw);
3293 e1000_sw_init(struct pci_device *pdev, struct e1000_hw *hw)
3298 pci_read_config_word(pdev, PCI_VENDOR_ID, &hw->vendor_id);
3299 pci_read_config_word(pdev, PCI_DEVICE_ID, &hw->device_id);
3300 pci_read_config_byte(pdev, PCI_REVISION, &hw->revision_id);
3303 &hw->subsystem_vendor_id);
3304 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
3307 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
3311 result = e1000_set_mac_type(hw);
3319 e1000_init_eeprom_params(hw);
3322 if((hw->mac_type == e1000_82541) ||
3323 (hw->mac_type == e1000_82547) ||
3324 (hw->mac_type == e1000_82541_rev_2) ||
3325 (hw->mac_type == e1000_82547_rev_2))
3326 hw->phy_init_script = 1;
3329 e1000_set_media_type(hw);
3332 if(hw->mac_type < e1000_82543)
3333 hw->report_tx_early = 0;
3335 hw->report_tx_early = 1;
3337 hw->wait_autoneg_complete = FALSE;
3339 hw->tbi_compatibility_en = TRUE;
3341 hw->adaptive_ifs = TRUE;
3345 if(hw->media_type == e1000_media_type_copper) {
3346 hw->mdix = AUTO_ALL_MODES;
3347 hw->disable_polarity_correction = FALSE;
3348 hw->master_slave = E1000_MASTER_SLAVE;
3362 E1000_WRITE_REG (&hw, RDT, rx_tail);
3376 E1000_WRITE_REG (&hw, TDBAL, virt_to_bus(tx_base));
3377 E1000_WRITE_REG (&hw, TDBAH, 0);
3378 E1000_WRITE_REG (&hw, TDLEN, 128);
3382 E1000_WRITE_REG (&hw, TDH, 0);
3383 E1000_WRITE_REG (&hw, TDT, 0);
3389 tctl = E1000_READ_REG(&hw, TCTL);
3400 E1000_WRITE_REG (&hw, TCTL, tctl);
3402 e1000_config_collision_dist(&hw);
3407 E1000_WRITE_REG (&hw, RCTL, 0);
3415 E1000_WRITE_REG (&hw, RDBAL, virt_to_bus(rx_base));
3416 E1000_WRITE_REG (&hw, RDBAH, 0);
3418 E1000_WRITE_REG (&hw, RDLEN, 128);
3421 E1000_WRITE_REG (&hw, RDH, 0);
3422 E1000_WRITE_REG (&hw, RDT, 0);
3424 E1000_WRITE_REG (&hw, RCTL,
3494 E1000_WRITE_REG (&hw, TDT, tx_tail);
3509 E1000_WRITE_REG (&hw, TDH, 0);
3510 E1000_WRITE_REG (&hw, TDT, 0);
3513 E1000_WRITE_REG (&hw, RDH, 0);
3514 E1000_WRITE_REG (&hw, RDT, 0);
3517 E1000_WRITE_REG (&hw, CTRL, E1000_CTRL_RST);
3520 E1000_WRITE_REG (&hw, RCTL, 0);
3521 E1000_WRITE_REG (&hw, TCTL, 0);
3525 iounmap(hw.hw_addr);
3560 /* Initialize hw with default values */
3561 memset(&hw, 0, sizeof(hw));
3562 hw.pdev = p;
3566 hw.fc = e1000_fc_none;
3568 hw.original_fc = e1000_fc_none;
3570 hw.autoneg_failed = 0;
3572 hw.get_link_status = TRUE;
3578 hw.hw_addr = ioremap(mmio_start, mmio_len);
3584 hw.io_base = pci_bar_start(p, i);
3598 if (e1000_sw_init(p, &hw) < 0) {
3599 iounmap(hw.hw_addr);
3605 if (e1000_validate_eeprom_checksum(&hw) < 0) {
3607 iounmap(hw.hw_addr);
3613 e1000_read_mac_addr(&hw);
3614 memcpy (nic->node_addr, hw.mac_addr, ETH_ALEN);
3620 ret_val = e1000_reset(&hw);
3628 iounmap(hw.hw_addr);