Cross Reference: /osnet-11/usr/src/grub/grub-0.97/netboot/e1000.c

Lines Matching defs:ctrl
968 	uint32_t ctrl;
1001 	ctrl = E1000_READ_REG(hw, CTRL);
1005 		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
1025 			E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
1030 			E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
1033 			E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1109 	uint32_t ctrl, status;
1165 		ctrl = E1000_READ_REG(hw, CTRL);
1166 		E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1206 		ctrl = E1000_READ_REG(hw, TXDCTL);
1207 		ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1208 		E1000_WRITE_REG(hw, TXDCTL, ctrl);
1405 	uint32_t ctrl;
1420 	ctrl = E1000_READ_REG(hw, CTRL);
1428 	ctrl &= ~(E1000_CTRL_LRST);
1492 	E1000_WRITE_REG(hw, CTRL, ctrl);
1543 	uint32_t ctrl;
1550 	ctrl = E1000_READ_REG(hw, CTRL);
1556 		ctrl |= E1000_CTRL_SLU;
1557 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1558 		E1000_WRITE_REG(hw, CTRL, ctrl);
1560 		ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1561 		E1000_WRITE_REG(hw, CTRL, ctrl);
2061 	uint32_t ctrl;
2070 	ctrl = E1000_READ_REG(hw, CTRL);
2071 	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2072 	ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2082 		if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
2083 		else ctrl &= ~E1000_CTRL_FD;
2092 			ctrl |= E1000_CTRL_SPD_1000;
2095 			ctrl |= E1000_CTRL_SPD_100;
2101 		if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
2102 		else ctrl &= ~E1000_CTRL_FD;
2110 			ctrl |= E1000_CTRL_SPD_1000;
2112 			ctrl |= E1000_CTRL_SPD_100;
2115 	E1000_WRITE_REG(hw, CTRL, ctrl);
2133 	uint32_t ctrl;
2138 	ctrl = E1000_READ_REG(hw, CTRL);
2160 		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2163 		ctrl &= (~E1000_CTRL_TFCE);
2164 		ctrl |= E1000_CTRL_RFCE;
2167 		ctrl &= (~E1000_CTRL_RFCE);
2168 		ctrl |= E1000_CTRL_TFCE;
2171 		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2180 		ctrl &= (~E1000_CTRL_TFCE);
2182 	E1000_WRITE_REG(hw, CTRL, ctrl);
2403 	uint32_t ctrl;
2420 	ctrl = E1000_READ_REG(hw, CTRL);
2531 	        ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2545 		ctrl = E1000_READ_REG(hw, CTRL);
2546 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2547 		E1000_WRITE_REG(hw, CTRL, ctrl);
2562 		(ctrl & E1000_CTRL_SLU) &&
2566 		E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2671 * ctrl - Device control register's current value
2675                     uint32_t *ctrl)
2680 	E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2689 * ctrl - Device control register's current value
2693                     uint32_t *ctrl)
2698 	E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2717 	uint32_t ctrl;
2727 	ctrl = E1000_READ_REG(hw, CTRL);
2730 	ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2738 		if(data & mask) ctrl |= E1000_CTRL_MDIO;
2739 		else ctrl &= ~E1000_CTRL_MDIO;
2741 		E1000_WRITE_REG(hw, CTRL, ctrl);
2746 		e1000_raise_mdi_clk(hw, &ctrl);
2747 		e1000_lower_mdi_clk(hw, &ctrl);
2763 	uint32_t ctrl;
2774 	ctrl = E1000_READ_REG(hw, CTRL);
2777 	ctrl &= ~E1000_CTRL_MDIO_DIR;
2778 	ctrl &= ~E1000_CTRL_MDIO;
2780 	E1000_WRITE_REG(hw, CTRL, ctrl);
2787 	e1000_raise_mdi_clk(hw, &ctrl);
2788 	e1000_lower_mdi_clk(hw, &ctrl);
2792 		e1000_raise_mdi_clk(hw, &ctrl);
2793 		ctrl = E1000_READ_REG(hw, CTRL);
2795 		if(ctrl & E1000_CTRL_MDIO) data |= 1;
2796 		e1000_lower_mdi_clk(hw, &ctrl);
2799 	e1000_raise_mdi_clk(hw, &ctrl);
2800 	e1000_lower_mdi_clk(hw, &ctrl);
3008 	uint32_t ctrl, ctrl_ext;
3018 		ctrl = E1000_READ_REG(hw, CTRL);
3019 		E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3022 		E1000_WRITE_REG(hw, CTRL, ctrl);