Lines Matching refs:register_hint

4134 Interval* Interval::register_hint(bool search_split_child) const {
4559 out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
5372 Interval* register_hint = cur->register_hint();
5373 if (register_hint != NULL) {
5374 hint_reg = register_hint->assigned_reg();
5375 hint_regHi = register_hint->assigned_regHi();
5377 if (allocator()->is_precolored_cpu_interval(register_hint)) {
5381 TRACE_LINEAR_SCAN(4, tty->print(" hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print());
5679 Interval* register_hint = cur->register_hint(false);
5680 if (register_hint == NULL) {
5681 // cur is not the target of a move, otherwise register_hint would be set
5684 assert(register_hint->is_split_parent(), "register hint must be split parent");
5686 if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5699 if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5700 // cur and register_hint are not connected with two moves
5704 Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5705 Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5707 // register_hint must be split, otherwise the re-writing of use positions does not work
5717 // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5720 assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5722 // modify intervals such that cur gets the same stack slot as register_hint
5724 cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());