Cross Reference: /openjdk7/hotspot/src/share/vm/c1/c1

Lines Matching refs:assigned_regHi
1711     if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1829   int regHi = interval->assigned_regHi();
2052     assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2060         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2066         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2075         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2083         int assigned_regHi = interval->assigned_regHi();
2086                (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2088         assert(assigned_reg != assigned_regHi, "invalid allocation");
2089         assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2091         assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2093           assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2100         return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2102         return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2112           assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2118         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2126           assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2133         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2134         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2135         LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2138         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2139         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2140         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2143         assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2392     assert(interval->assigned_regHi() == any_reg, "oop must be single word");
3208     if (i1->assigned_reg() == i1->assigned_regHi()) {
3240       int r1Hi = i1->assigned_regHi();
3242       int r2Hi = i2->assigned_regHi();
3446       if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3447         input_state->at_put(interval->assigned_regHi(), interval);
3599         has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3605           state_put(input_state, interval->assigned_regHi(), NULL);
3644         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3659         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3729         if (it->assigned_regHi() != LinearScan::any_reg) {
3730           assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3731           used_regs.set_bit(it->assigned_regHi());
3743     if (it->assigned_regHi() != LinearScan::any_reg) {
3744       assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3745       used_regs.set_bit(it->assigned_regHi());
3765 // mark assigned_reg and assigned_regHi of the interval as blocked
3772   reg = it->assigned_regHi();
3779 // mark assigned_reg and assigned_regHi of the interval as unblocked
3786   reg = it->assigned_regHi();
3793 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3799     from_regHi = from->assigned_regHi();
3808   reg = to->assigned_regHi();
3851   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3862   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr("  to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3980   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3989   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4548         (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4834   exclude_from_use(i->assigned_regHi());
4853     set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4871     set_block_pos(i->assigned_regHi(), i, block_pos);
5375     hint_regHi = register_hint->assigned_regHi();
5388   assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5750     assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");