Lines Matching refs:bus
88 uint8_t bus;
119 static void enumerate_bus_devs(uchar_t bus, int config_op);
120 static void create_root_bus_dip(uchar_t bus);
133 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id);
136 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
139 static void populate_bus_res(uchar_t bus);
155 /* set non-zero to force PCI peer-bus renumbering */
199 * If not a PCI root-bus, ignore this device and continue
222 * bus 0 _BBNs being found, so we need to handle duplicate
223 * bus 0 gracefully. However, broken _BBN does not
262 * Root-bridge for bus 0 may not have a _BBN object.
292 * of the "index value" of the PCI root-bus and the value is
296 * root-buses ordered by physical bus number; first PCI bus is 0,
476 * one more bus at the high end, which implements the ISA
477 * compatibility bus. We don't care about that.
479 * Note: In the old (bootconf) enumeration, the peer bus
480 * address did not use the bus number, and there were
482 * used to maintain the old peer bus address assignment.
501 pci_bbn_present(int bus)
507 if (pci_bus_res[bus].dip == NULL)
511 if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) {
528 * Return non-zero if any PCI bus in the system has an associated
576 * Initial enumeration of the physical PCI bus hierarchy can
577 * leave 'gaps' in the order of peer PCI bus unit-addresses.
578 * Systems with more than one peer PCI bus *must* have an ACPI
579 * _BBN object associated with each peer bus; use the presence
581 * PCI bus unit-addresses - only peer busses with an associated
637 * bridge from the bus's resources lists, because they're not available, and
695 setup_bus_res(int bus)
699 if (pci_bus_res[bus].dip == NULL) /* unused bus */
705 if (pci_bus_res[bus].bus_avail == NULL) {
706 ASSERT(pci_bus_res[bus].sub_bus >= bus);
707 memlist_insert(&pci_bus_res[bus].bus_avail, bus,
708 pci_bus_res[bus].sub_bus - bus + 1);
711 ASSERT(pci_bus_res[bus].bus_avail != NULL);
714 * Remove resources from parent bus node if this is not a
715 * root bus.
717 par_bus = pci_bus_res[bus].par_bus;
721 pci_bus_res[bus].bus_avail);
725 (void) memlist_remove(&pci_bus_res[bus].bus_avail, bus, 1);
729 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
735 * Skip root(peer) buses in multiple-root-bus systems when
748 break; /* root bus already */
759 memlist_free_all(&pci_bus_res[bus].io_avail);
760 memlist_free_all(&pci_bus_res[bus].io_used);
763 memlist_insert(&pci_bus_res[bus].io_avail, addr, size);
771 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
777 * Skip root(peer) buses in multiple-root-bus systems when
790 break; /* root bus already */
803 memlist_free_all(&pci_bus_res[bus].mem_avail);
804 memlist_free_all(&pci_bus_res[bus].mem_used);
807 memlist_insert(&pci_bus_res[bus].mem_avail, addr, size);
818 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id)
829 status = pci_getw(bus, dev, func, PCI_CONF_STAT);
833 cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
837 curcap = pci_getb(bus, dev, func, cap_id_loc);
843 cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1);
894 uchar_t bus, dev, func;
914 /* some entries may be empty due to discontiguous bus numbering */
928 bus = (uchar_t)PCI_REG_BUS_G(physhi);
933 cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E);
935 cmd_reg = pci_getw(bus, dev, func,
940 bus, dev, func);
945 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
947 ASSERT(parbus == bus);
948 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM);
951 * If we have a Cardbus bridge, but no bus space
961 * Try to find and allocate a bus-range starting at subbus+1
968 break; /* find bus range resource at parent */
975 pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus);
978 cmn_err(CE_NOTE, "!reprogram bus-range on ppb"
979 "[%x/%x/%x]: %x ~ %x\n", bus, dev, func,
986 * If bus io_size is zero, we are going to assign 512 bytes per bus,
988 * bus io_size. The size needs to be 4K aligned.
1004 * If bus mem_size is zero, we are going to assign 1M bytes per bus,
1006 * bus mem_size. The size needs to be 1M aligned.
1053 bus, dev, func, (uint32_t)addr,
1070 bus, dev, func, (uint32_t)addr,
1080 * parent bus needed reprogramming and so do we, or because I/O space is
1083 io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
1084 io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
1137 /* get new io ports from parent bus */
1148 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
1150 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
1152 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
1153 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
1158 bus, dev, func, io_base, io_limit);
1166 mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
1168 mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
1218 /* get new mem resource from parent bus */
1230 pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE,
1232 pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT,
1247 pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW,
1249 pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW,
1251 pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH,
1253 pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH,
1261 bus, dev, func, mem_base, mem_limit);
1271 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg);
1279 int bus;
1296 for (bus = 0; bus <= pci_bios_maxbus; bus++) {
1298 if ((pci_bus_res[bus].par_bus != (uchar_t)-1) ||
1299 (pci_bus_res[bus].dip == NULL))
1303 if (pci_bus_res[bus].root_addr != new_addr) {
1305 pci_regs[0] = pci_bus_res[bus].root_addr =
1308 DDI_DEV_T_NONE, pci_bus_res[bus].dip,
1320 * Do root-bus resource discovery
1322 for (bus = 0; bus <= pci_bios_maxbus; bus++) {
1324 if (pci_bus_res[bus].par_bus != (uchar_t)-1)
1328 * 1. find resources associated with this root bus
1330 populate_bus_res(bus);
1334 * 2. Remove used PCI and ISA resources from bus resource map
1337 memlist_remove_list(&pci_bus_res[bus].io_avail,
1338 pci_bus_res[bus].io_used);
1339 memlist_remove_list(&pci_bus_res[bus].mem_avail,
1340 pci_bus_res[bus].mem_used);
1341 memlist_remove_list(&pci_bus_res[bus].pmem_avail,
1342 pci_bus_res[bus].pmem_used);
1343 memlist_remove_list(&pci_bus_res[bus].mem_avail,
1344 pci_bus_res[bus].pmem_used);
1345 memlist_remove_list(&pci_bus_res[bus].pmem_avail,
1346 pci_bus_res[bus].mem_used);
1348 memlist_remove_list(&pci_bus_res[bus].io_avail,
1350 memlist_remove_list(&pci_bus_res[bus].mem_avail,
1356 * in ACPI resource producer entries for PCI root bus.
1363 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 0, 0x100000);
1364 (void) memlist_remove(&pci_bus_res[bus].pmem_avail,
1371 /* add bus-range property for root/peer bus nodes */
1373 /* create bus-range property on root/peer buses */
1377 /* setup bus range resource on each bus */
1416 * populate bus resources
1419 populate_bus_res(uchar_t bus)
1423 pci_bus_res[bus].pmem_avail = find_bus_res(bus, PREFETCH_TYPE);
1424 pci_bus_res[bus].mem_avail = find_bus_res(bus, MEM_TYPE);
1425 pci_bus_res[bus].io_avail = find_bus_res(bus, IO_TYPE);
1426 pci_bus_res[bus].bus_avail = find_bus_res(bus, BUSRANGE_TYPE);
1432 if (pci_bus_res[bus].bus_avail != NULL) {
1436 entry = pci_bus_res[bus].bus_avail;
1439 if (current > pci_bus_res[bus].sub_bus)
1440 pci_bus_res[bus].sub_bus = current;
1445 if (bus == 0) {
1447 * Special treatment of bus 0:
1464 add_ranges_prop(bus, 0);
1469 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0...
1472 create_root_bus_dip(uchar_t bus)
1477 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1);
1486 pci_regs[0] = pci_bus_res[bus].root_addr;
1491 * If system has PCIe bus, then create different properties
1493 if (create_pcie_root_bus(bus, dip) == B_FALSE)
1498 pci_bus_res[bus].dip = dip;
1507 enumerate_bus_devs(uchar_t bus, int config_op)
1514 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus);
1516 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus);
1518 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus);
1521 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
1526 pci_bus_res[bus].io_reprogram ||
1527 pci_bus_res[bus].mem_reprogram) {
1529 (void) add_reg_props(entry->dip, bus,
1534 pci_bus_res[bus].privdata = NULL;
1545 venid = pci_getw(bus, dev, func, PCI_CONF_VENID);
1552 header = pci_getb(bus, dev, func, PCI_CONF_HEADER);
1575 process_devfunc(bus, dev, func, header,
1582 /* percolate bus used resources up through parents to root */
1586 par_bus = pci_bus_res[bus].par_bus;
1589 pci_bus_res[bus].io_size;
1591 pci_bus_res[bus].mem_size;
1593 if (pci_bus_res[bus].io_used)
1594 memlist_merge(&pci_bus_res[bus].io_used,
1597 if (pci_bus_res[bus].mem_used)
1598 memlist_merge(&pci_bus_res[bus].mem_used,
1601 if (pci_bus_res[bus].pmem_used)
1602 memlist_merge(&pci_bus_res[bus].pmem_used,
1605 bus = par_bus;
1717 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn,
1728 newundo->bus = bus;
1745 * For each bus, apply needed fixes to the appropriate devices.
1760 uint8_t bus, dev, fn;
1768 bus = undolist->bus;
1772 (*(undolist->undofn))(bus, dev, fn);
1781 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn)
1785 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1791 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1795 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn)
1799 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1811 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1813 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix);
1817 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func)
1825 status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1829 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
1831 cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR);
1833 cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
1839 cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID);
1841 pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR);
1844 pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr);
1847 cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR);
1856 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header,
1874 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID);
1878 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID);
1879 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID);
1882 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID);
1883 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID);
1884 /* Record the # of cardbus bridges found on the bus */
1886 pci_bus_res[bus].num_cbb++;
1896 pci_fix_amd8111(bus, dev, func);
1902 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID);
1923 /* make sure parent bus dip has been created */
1924 if (pci_bus_res[bus].dip == NULL)
1925 create_root_bus_dip(bus);
1927 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename,
1930 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_valid,
1934 bdf = PCI_GETBDF(bus, dev, func);
1945 secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
1946 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
1983 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G);
1984 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L);
2001 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN);
2009 status = pci_getw(bus, dev, func, PCI_CONF_STAT);
2033 set_devpm_d0(bus, dev, func);
2036 add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge);
2039 * Record the non-PPB devices on the bus for possible
2040 * reprogramming at 2nd bus enumeration.
2043 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
2049 pci_bus_res[bus].privdata = entry;
2053 create_ioapic_node(bus, dev, func, vendorid, deviceid);
2059 add_nvidia_isa_bridge_props(dip, bus, dev, func);
2096 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide);
2350 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
2369 io_avail = &pci_bus_res[bus].io_avail;
2370 io_used = &pci_bus_res[bus].io_used;
2371 mem_avail = &pci_bus_res[bus].mem_avail;
2372 mem_used = &pci_bus_res[bus].mem_used;
2373 pmem_avail = &pci_bus_res[bus].pmem_avail;
2374 pmem_used = &pci_bus_res[bus].pmem_used;
2376 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8;
2381 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS);
2382 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS);
2383 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
2384 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
2411 * secondary-bus activity (see sections 4.1-4.3 of the
2423 base = pci_getl(bus, dev, func, offset);
2425 command = (uint_t)pci_getw(bus, dev, func,
2427 pci_putw(bus, dev, func, PCI_CONF_COMM,
2430 pci_putl(bus, dev, func, offset, 0xffffffff);
2431 value = pci_getl(bus, dev, func, offset);
2432 pci_putl(bus, dev, func, offset, base);
2434 pci_putw(bus, dev, func, PCI_CONF_COMM, command);
2469 * resources from its parent bus if there is no resource
2470 * available on its own bus.
2473 res_bus = bus;
2477 break; /* root bus already */
2492 /* take out of the resource map of the bus */
2500 pci_bus_res[bus].io_size += len;
2502 pci_bus_res[bus].io_reprogram) {
2507 pci_putl(bus, dev, func, offset,
2509 base = pci_getl(bus, dev, func, offset);
2516 bus, dev, func, offset, len);
2526 base_hi = pci_getl(bus, dev, func, offset + 4);
2550 * resources from its parent bus if there is no resource
2551 * available on its own bus.
2554 res_bus = bus;
2558 break; /* root bus already */
2582 /* take out of the resource map of the bus */
2599 pci_bus_res[bus].mem_size += len;
2601 pci_bus_res[bus].mem_reprogram) {
2632 pci_putl(bus, dev, func, offset,
2634 base = pci_getl(bus, dev, func, offset);
2640 bus, dev, func, offset, len);
2662 base = pci_getl(bus, dev, func, offset);
2663 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M);
2664 value = pci_getl(bus, dev, func, offset);
2665 pci_putl(bus, dev, func, offset, base);
2684 pci_bus_res[bus].mem_size += len;
2704 pci_bus_res[bus].io_size += 0xc;
2714 pci_bus_res[bus].io_size += 0x20;
2728 pci_bus_res[bus].mem_size += 0x20000;
2744 pci_bus_res[bus].io_size += 0x1;
2754 pci_bus_res[bus].io_size += 0x6;
2768 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
2774 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
2775 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
2783 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
2798 pci_bus_res[secbus].par_bus = bus;
2802 /* setup bus number hierarchy */
2805 * Keep track of the largest subordinate bus number (this is essential
2807 * subordinate bus number).
2809 if (subbus > pci_bus_res[bus].sub_bus)
2810 pci_bus_res[bus].sub_bus = subbus;
2812 * Loop through subordinate busses, initializing their parent bus
2820 pci_bus_res[i].par_bus = bus;
2831 * the "avail" resources for the bus. Not all of those resources will
2834 * bus node. Later, as children are found, resources are removed from
2853 val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM);
2855 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
2857 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
2862 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
2864 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
2866 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
2867 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
2874 memlist_insert(&pci_bus_res[bus].io_used,
2877 if (pci_bus_res[bus].io_avail != NULL) {
2878 (void) memlist_remove(&pci_bus_res[bus].io_avail,
2882 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x",
2886 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) {
2888 " pci-pci bridge [%d/%d/%d]", bus, dev, func);
2893 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
2895 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
2901 memlist_insert(&pci_bus_res[bus].mem_used,
2905 (void) memlist_remove(&pci_bus_res[bus].mem_avail,
2908 (void) memlist_remove(&pci_bus_res[bus].pmem_avail,
2911 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x",
2916 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW);
2918 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW);
2924 memlist_insert(&pci_bus_res[bus].pmem_used,
2928 (void) memlist_remove(&pci_bus_res[bus].pmem_avail,
2931 (void) memlist_remove(&pci_bus_res[bus].mem_avail,
2934 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x",
2938 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) {
2940 " pci-pci bridge [%d/%d/%d]", bus, dev, func);
2953 if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) &
2958 memlist_insert(&pci_bus_res[bus].io_used, 0x3b0, 0xc);
2959 if (pci_bus_res[bus].io_avail != NULL) {
2960 (void) memlist_remove(&pci_bus_res[bus].io_avail,
2966 memlist_insert(&pci_bus_res[bus].io_used, 0x3c0, 0x20);
2967 if (pci_bus_res[bus].io_avail != NULL) {
2968 (void) memlist_remove(&pci_bus_res[bus].io_avail,
2975 memlist_insert(&pci_bus_res[bus].mem_used, 0xa0000, 0x20000);
2976 if (pci_bus_res[bus].mem_avail != NULL) {
2977 (void) memlist_remove(&pci_bus_res[bus].mem_avail,
3017 add_bus_range_prop(int bus)
3021 if (pci_bus_res[bus].dip == NULL)
3023 bus_range[0] = bus;
3024 bus_range[1] = pci_bus_res[bus].sub_bus;
3025 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
3026 "bus-range", (int *)bus_range, 2);
3033 add_bus_slot_names_prop(int bus)
3053 if (pci_bus_res[bus].dip != NULL) {
3054 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pci_bus_res[bus].dip,
3058 pci_bus_res[bus].dip, "slot-names");
3061 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop));
3064 * Only create a peer bus node if this bus may be a peer bus.
3065 * It may be a peer bus if the dip is NULL and if par_bus is
3066 * -1 (par_bus is -1 if this bus was not found to be
3068 * If it's not a peer bus, then the ACPI BBN-handling code
3071 if (pci_bus_res[bus].par_bus == (uchar_t)-1 &&
3072 pci_bus_res[bus].dip == NULL) {
3074 create_root_bus_dip(bus);
3076 if (pci_bus_res[bus].dip != NULL) {
3079 pci_bus_res[bus].dip, "slot-names",
3082 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI "
3084 "property for incorrect bus %d", bus);
3126 add_ranges_prop(int bus, int ppb)
3132 /* no devinfo node - unused bus, return */
3133 if (pci_bus_res[bus].dip == NULL)
3138 memlist_merge(&pci_bus_res[bus].io_avail, &iolist);
3139 memlist_merge(&pci_bus_res[bus].io_used, &iolist);
3140 memlist_merge(&pci_bus_res[bus].mem_avail, &memlist);
3141 memlist_merge(&pci_bus_res[bus].mem_used, &memlist);
3142 memlist_merge(&pci_bus_res[bus].pmem_avail, &pmemlist);
3143 memlist_merge(&pci_bus_res[bus].pmem_used, &pmemlist);
3164 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
3203 add_bus_available_prop(int bus)
3208 /* no devinfo node - unused bus, return */
3209 if (pci_bus_res[bus].dip == NULL)
3212 count = memlist_count(pci_bus_res[bus].io_avail) +
3213 memlist_count(pci_bus_res[bus].mem_avail) +
3214 memlist_count(pci_bus_res[bus].pmem_avail);
3220 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_avail,
3222 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_avail,
3224 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_avail,
3228 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
3263 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
3273 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0);
3280 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4);