Lines Matching refs:BIT
38 #define XGE_HAL_GEN_INTR_TXPIC BIT(0)
39 #define XGE_HAL_GEN_INTR_TXDMA BIT(1)
40 #define XGE_HAL_GEN_INTR_TXMAC BIT(2)
41 #define XGE_HAL_GEN_INTR_TXXGXS BIT(3)
42 #define XGE_HAL_GEN_INTR_TXTRAFFIC BIT(8)
43 #define XGE_HAL_GEN_INTR_RXPIC BIT(32)
44 #define XGE_HAL_GEN_INTR_RXDMA BIT(33)
45 #define XGE_HAL_GEN_INTR_RXMAC BIT(34)
46 #define XGE_HAL_GEN_INTR_MC BIT(35)
47 #define XGE_HAL_GEN_INTR_RXXGXS BIT(36)
48 #define XGE_HAL_GEN_INTR_RXTRAFFIC BIT(40)
86 #define XGE_HAL_ADAPTER_STATUS_TDMA_READY BIT(0)
87 #define XGE_HAL_ADAPTER_STATUS_RDMA_READY BIT(1)
88 #define XGE_HAL_ADAPTER_STATUS_PFC_READY BIT(2)
89 #define XGE_HAL_ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3)
90 #define XGE_HAL_ADAPTER_STATUS_PIC_QUIESCENT BIT(5)
91 #define XGE_HAL_ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6)
92 #define XGE_HAL_ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7)
98 #define XGE_HAL_ADAPTER_STATUS_MC_DRAM_READY BIT(24)
99 #define XGE_HAL_ADAPTER_STATUS_MC_QUEUES_READY BIT(25)
100 #define XGE_HAL_ADAPTER_STATUS_M_PLL_LOCK BIT(30)
101 #define XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK BIT(31)
104 #define XGE_HAL_ADAPTER_CNTL_EN BIT(7)
105 #define XGE_HAL_ADAPTER_EOI_TX_ON BIT(15)
106 #define XGE_HAL_ADAPTER_LED_ON BIT(23)
108 #define XGE_HAL_ADAPTER_WAIT_INT BIT(48)
109 #define XGE_HAL_ADAPTER_ECC_EN BIT(55)
112 #define XGE_HAL_SERR_SOURCE_PIC BIT(0)
113 #define XGE_HAL_SERR_SOURCE_TXDMA BIT(1)
114 #define XGE_HAL_SERR_SOURCE_RXDMA BIT(2)
115 #define XGE_HAL_SERR_SOURCE_MAC BIT(3)
116 #define XGE_HAL_SERR_SOURCE_MC BIT(4)
117 #define XGE_HAL_SERR_SOURCE_XGXS BIT(5)
127 #define XGE_HAL_PCI_32_BIT BIT(8)
142 #define XGE_HAL_PIC_INT_TX BIT(0)
143 #define XGE_HAL_PIC_INT_FLSH BIT(1)
144 #define XGE_HAL_PIC_INT_MDIO BIT(2)
145 #define XGE_HAL_PIC_INT_IIC BIT(3)
146 #define XGE_HAL_PIC_INT_MISC BIT(4)
147 #define XGE_HAL_PIC_INT_RX BIT(32)
150 #define XGE_HAL_TXPIC_INT_SCHED_INTR BIT(42)
152 #define XGE_HAL_PCIX_INT_REG_ECC_SG_ERR BIT(0)
153 #define XGE_HAL_PCIX_INT_REG_ECC_DB_ERR BIT(1)
154 #define XGE_HAL_PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8)
155 #define XGE_HAL_PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9)
156 #define XGE_HAL_PCIX_INT_REG_INI_TX_FSM_SERR BIT(10)
157 #define XGE_HAL_PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11)
158 #define XGE_HAL_PCIX_INT_REG_TRT_FSM_SERR BIT(13)
159 #define XGE_HAL_PCIX_INT_REG_SRT_FSM_SERR BIT(14)
160 #define XGE_HAL_PCIX_INT_REG_PIFR_FSM_SERR BIT(15)
161 #define XGE_HAL_PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21)
162 #define XGE_HAL_PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23)
163 #define XGE_HAL_PCIX_INT_REG_INI_RX_FSM_SERR BIT(48)
164 #define XGE_HAL_PCIX_INT_REG_RA_RX_FSM_SERR BIT(50)
166 #define XGE_HAL_PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52)
167 #define XGE_HAL_PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54)
168 #define XGE_HAL_PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58)
172 #define XGE_HAL_RX_PIC_INT_REG_SPDM_READY BIT(0)
173 #define XGE_HAL_RX_PIC_INT_REG_SPDM_OVERWRITE_ERR BIT(44)
174 #define XGE_HAL_RX_PIC_INT_REG_SPDM_PERR BIT(55)
180 #define XGE_HAL_PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63)
181 #define XGE_HAL_PIC_FLSH_INT_REG_ERR BIT(62)
186 #define XGE_HAL_MDIO_INT_REG_MDIO_BUS_ERR BIT(0)
187 #define XGE_HAL_MDIO_INT_REG_DTX_BUS_ERR BIT(8)
188 #define XGE_HAL_MDIO_INT_REG_LASI BIT(39)
193 #define XGE_HAL_IIC_INT_REG_BUS_FSM_ERR BIT(4)
194 #define XGE_HAL_IIC_INT_REG_BIT_FSM_ERR BIT(5)
195 #define XGE_HAL_IIC_INT_REG_CYCLE_FSM_ERR BIT(6)
196 #define XGE_HAL_IIC_INT_REG_REQ_FSM_ERR BIT(7)
197 #define XGE_HAL_IIC_INT_REG_ACK_ERR BIT(8)
203 #define XGE_HAL_MISC_INT_REG_DP_ERR_INT BIT(0)
204 #define XGE_HAL_MISC_INT_REG_LINK_DOWN_INT BIT(1)
205 #define XGE_HAL_MISC_INT_REG_LINK_UP_INT BIT(2)
218 #define XGE_HAL_TX_TRAFFIC_INT_n(n) BIT(n)
222 #define XGE_HAL_RX_TRAFFIC_INT_n(n) BIT(n)
227 #define XGE_HAL_PIC_CNTL_RX_ALARM_MAP_1 BIT(0)
228 #define XGE_HAL_PIC_CNTL_ONE_SHOT_TINT BIT(1)
232 #define XGE_HAL_SWAPPER_CTRL_PIF_R_FE BIT(0)
233 #define XGE_HAL_SWAPPER_CTRL_PIF_R_SE BIT(1)
234 #define XGE_HAL_SWAPPER_CTRL_PIF_W_FE BIT(8)
235 #define XGE_HAL_SWAPPER_CTRL_PIF_W_SE BIT(9)
236 #define XGE_HAL_SWAPPER_CTRL_RTH_FE BIT(10)
237 #define XGE_HAL_SWAPPER_CTRL_RTH_SE BIT(11)
238 #define XGE_HAL_SWAPPER_CTRL_TXP_FE BIT(16)
239 #define XGE_HAL_SWAPPER_CTRL_TXP_SE BIT(17)
240 #define XGE_HAL_SWAPPER_CTRL_TXD_R_FE BIT(18)
241 #define XGE_HAL_SWAPPER_CTRL_TXD_R_SE BIT(19)
242 #define XGE_HAL_SWAPPER_CTRL_TXD_W_FE BIT(20)
243 #define XGE_HAL_SWAPPER_CTRL_TXD_W_SE BIT(21)
244 #define XGE_HAL_SWAPPER_CTRL_TXF_R_FE BIT(22)
245 #define XGE_HAL_SWAPPER_CTRL_TXF_R_SE BIT(23)
246 #define XGE_HAL_SWAPPER_CTRL_RXD_R_FE BIT(32)
247 #define XGE_HAL_SWAPPER_CTRL_RXD_R_SE BIT(33)
248 #define XGE_HAL_SWAPPER_CTRL_RXD_W_FE BIT(34)
249 #define XGE_HAL_SWAPPER_CTRL_RXD_W_SE BIT(35)
250 #define XGE_HAL_SWAPPER_CTRL_RXF_W_FE BIT(36)
251 #define XGE_HAL_SWAPPER_CTRL_RXF_W_SE BIT(37)
252 #define XGE_HAL_SWAPPER_CTRL_XMSI_FE BIT(40)
253 #define XGE_HAL_SWAPPER_CTRL_XMSI_SE BIT(41)
254 #define XGE_HAL_SWAPPER_CTRL_STATS_FE BIT(48)
255 #define XGE_HAL_SWAPPER_CTRL_STATS_SE BIT(49)
261 #define XGE_HAL_SCHED_INT_CTRL_TIMER_EN BIT(0)
262 #define XGE_HAL_SCHED_INT_CTRL_ONE_SHOT BIT(1)
270 #define XGE_HAL_TXREQTO_EN BIT(63)
274 #define XGE_HAL_STATREQTO_EN BIT(63)
282 #define XGE_HAL_XMSI_EN BIT(0)
283 #define XGE_HAL_XMSI_DIS_TINT_SERR BIT(1)
287 #define XGE_HAL_XMSI_WR_RDN BIT(7)
288 #define XGE_HAL_XMSI_STROBE BIT(15)
308 #define XGE_HAL_STAT_CFG_STAT_EN BIT(0)
309 #define XGE_HAL_STAT_CFG_ONE_SHOT_EN BIT(1)
310 #define XGE_HAL_STAT_CFG_STAT_NS_EN BIT(8)
311 #define XGE_HAL_STAT_CFG_STAT_RO BIT(9)
354 #define XGE_HAL_I2C_CONTROL_READ BIT(24)
355 #define XGE_HAL_I2C_CONTROL_NACK BIT(25)
364 #define XGE_HAL_MISC_CONTROL_EXT_REQ_EN BIT(1)
365 #define XGE_HAL_MISC_CONTROL_LINK_FAULT BIT(0)
369 #define XGE_HAL_GPIO_CTRL_GPIO_0 BIT(8)
433 #define XGE_HAL_TXDMA_PFC_INT BIT(0)
434 #define XGE_HAL_TXDMA_TDA_INT BIT(1)
435 #define XGE_HAL_TXDMA_PCC_INT BIT(2)
436 #define XGE_HAL_TXDMA_TTI_INT BIT(3)
437 #define XGE_HAL_TXDMA_LSO_INT BIT(4)
438 #define XGE_HAL_TXDMA_TPA_INT BIT(5)
439 #define XGE_HAL_TXDMA_SM_INT BIT(6)
441 #define XGE_HAL_PFC_ECC_SG_ERR BIT(7)
442 #define XGE_HAL_PFC_ECC_DB_ERR BIT(15)
443 #define XGE_HAL_PFC_SM_ERR_ALARM BIT(23)
444 #define XGE_HAL_PFC_MISC_0_ERR BIT(31)
445 #define XGE_HAL_PFC_MISC_1_ERR BIT(32)
446 #define XGE_HAL_PFC_PCIX_ERR BIT(39)
453 #define XGE_HAL_TDA_SM0_ERR_ALARM BIT(22)
454 #define XGE_HAL_TDA_SM1_ERR_ALARM BIT(23)
455 #define XGE_HAL_TDA_PCIX_ERR BIT(39)
468 #define XGE_HAL_PCC_6_COF_OV_ERR BIT(56)
469 #define XGE_HAL_PCC_7_COF_OV_ERR BIT(57)
470 #define XGE_HAL_PCC_6_LSO_OV_ERR BIT(58)
471 #define XGE_HAL_PCC_7_LSO_OV_ERR BIT(59)
476 #define XGE_HAL_TTI_ECC_SG_ERR BIT(7)
477 #define XGE_HAL_TTI_ECC_DB_ERR BIT(15)
478 #define XGE_HAL_TTI_SM_ERR_ALARM BIT(23)
483 #define XGE_HAL_LSO6_SEND_OFLOW BIT(12)
484 #define XGE_HAL_LSO7_SEND_OFLOW BIT(13)
485 #define XGE_HAL_LSO6_ABORT BIT(14)
486 #define XGE_HAL_LSO7_ABORT BIT(15)
487 #define XGE_HAL_LSO6_SM_ERR_ALARM BIT(22)
488 #define XGE_HAL_LSO7_SM_ERR_ALARM BIT(23)
493 #define XGE_HAL_TPA_TX_FRM_DROP BIT(7)
494 #define XGE_HAL_TPA_SM_ERR_ALARM BIT(23)
499 #define XGE_HAL_SM_SM_ERR_ALARM BIT(15)
512 #define XGE_HAL_TX_FIFO_PARTITION_EN BIT(0)
552 #define XGE_HAL_TTI_CMD_MEM_WE BIT(7)
553 #define XGE_HAL_TTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
554 #define XGE_HAL_TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15)
560 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38)
561 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39)
574 #define XGE_HAL_TX_PA_CFG_IGNORE_FRM_ERR BIT(1)
575 #define XGE_HAL_TX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
576 #define XGE_HAL_TX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
577 #define XGE_HAL_TX_PA_CFG_IGNORE_L2_ERR BIT(6)
598 #define XGE_HAL_RXDMA_RC_INT BIT(0)
599 #define XGE_HAL_RXDMA_RPA_INT BIT(1)
600 #define XGE_HAL_RXDMA_RDA_INT BIT(2)
601 #define XGE_HAL_RXDMA_RTI_INT BIT(3)
604 #define XGE_HAL_RXDMA_INT_RC_INT_M BIT(0)
605 #define XGE_HAL_RXDMA_INT_RPA_INT_M BIT(1)
606 #define XGE_HAL_RXDMA_INT_RDA_INT_M BIT(2)
607 #define XGE_HAL_RXDMA_INT_RTI_INT_M BIT(3)
612 #define XGE_HAL_RDA_FRM_ECC_SG_ERR BIT(23)
613 #define XGE_HAL_RDA_FRM_ECC_DB_N_AERR BIT(31)
614 #define XGE_HAL_RDA_SM1_ERR_ALARM BIT(38)
615 #define XGE_HAL_RDA_SM0_ERR_ALARM BIT(39)
616 #define XGE_HAL_RDA_MISC_ERR BIT(47)
617 #define XGE_HAL_RDA_PCIX_ERR BIT(55)
618 #define XGE_HAL_RDA_RXD_ECC_DB_SERR BIT(63)
625 #define XGE_HAL_RC_FTC_ECC_SG_ERR BIT(23)
626 #define XGE_HAL_RC_FTC_ECC_DB_ERR BIT(31)
628 #define XGE_HAL_RC_FTC_SM_ERR_ALARM BIT(47)
644 #define XGE_HAL_RPA_ECC_SG_ERR BIT(7)
645 #define XGE_HAL_RPA_ECC_DB_ERR BIT(15)
646 #define XGE_HAL_RPA_FLUSH_REQUEST BIT(22)
647 #define XGE_HAL_RPA_SM_ERR_ALARM BIT(23)
648 #define XGE_HAL_RPA_CREDIT_ERR BIT(31)
653 #define XGE_HAL_RTI_ECC_SG_ERR BIT(7)
654 #define XGE_HAL_RTI_ECC_DB_ERR BIT(15)
655 #define XGE_HAL_RTI_SM_ERR_ALARM BIT(23)
691 #define XGE_HAL_PRC_CTRL_RC_ENABLED BIT(7)
692 #define XGE_HAL_PRC_CTRL_RING_MODE (BIT(14)|BIT(15))
698 #define XGE_HAL_PRC_CTRL_RTH_DISABLE BIT(31)
699 #define XGE_HAL_PRC_CTRL_BIMODAL_INTERRUPT BIT(37)
700 #define XGE_HAL_PRC_CTRL_GROUP_READS BIT(38)
704 #define XGE_HAL_PRC_ALARM_ACTION_RR_R0_STOP BIT(3)
705 #define XGE_HAL_PRC_ALARM_ACTION_RW_R0_STOP BIT(7)
706 #define XGE_HAL_PRC_ALARM_ACTION_RR_R1_STOP BIT(11)
707 #define XGE_HAL_PRC_ALARM_ACTION_RW_R1_STOP BIT(15)
708 #define XGE_HAL_PRC_ALARM_ACTION_RR_R2_STOP BIT(19)
709 #define XGE_HAL_PRC_ALARM_ACTION_RW_R2_STOP BIT(23)
710 #define XGE_HAL_PRC_ALARM_ACTION_RR_R3_STOP BIT(27)
711 #define XGE_HAL_PRC_ALARM_ACTION_RW_R3_STOP BIT(31)
712 #define XGE_HAL_PRC_ALARM_ACTION_RR_R4_STOP BIT(35)
713 #define XGE_HAL_PRC_ALARM_ACTION_RW_R4_STOP BIT(39)
714 #define XGE_HAL_PRC_ALARM_ACTION_RR_R5_STOP BIT(43)
715 #define XGE_HAL_PRC_ALARM_ACTION_RW_R5_STOP BIT(47)
716 #define XGE_HAL_PRC_ALARM_ACTION_RR_R6_STOP BIT(51)
717 #define XGE_HAL_PRC_ALARM_ACTION_RW_R6_STOP BIT(55)
718 #define XGE_HAL_PRC_ALARM_ACTION_RR_R7_STOP BIT(59)
719 #define XGE_HAL_PRC_ALARM_ACTION_RW_R7_STOP BIT(63)
723 #define XGE_HAL_RTI_CMD_MEM_WE BIT(7)
724 #define XGE_HAL_RTI_CMD_MEM_STROBE BIT(15)
725 #define XGE_HAL_RTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
726 #define XGE_HAL_RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15)
731 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38)
732 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39)
744 #define XGE_HAL_RX_PA_CFG_IGNORE_FRM_ERR BIT(1)
745 #define XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
746 #define XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
765 #define XGE_HAL_MAC_INT_STATUS_TMAC_INT BIT(0)
766 #define XGE_HAL_MAC_INT_STATUS_RMAC_INT BIT(1)
769 #define XGE_HAL_TMAC_ECC_DB_ERR BIT(15)
770 #define XGE_HAL_TMAC_TX_BUF_OVRN BIT(23)
771 #define XGE_HAL_TMAC_TX_CRI_ERR BIT(31)
772 #define XGE_HAL_TMAC_TX_SM_ERR BIT(39)
777 #define XGE_HAL_RMAC_RX_BUFF_OVRN BIT(0)
778 #define XGE_HAL_RMAC_RTH_SPDM_ECC_SG_ERR BIT(0)
779 #define XGE_HAL_RMAC_RTS_ECC_DB_ERR BIT(0)
780 #define XGE_HAL_RMAC_ECC_DB_ERR BIT(0)
781 #define XGE_HAL_RMAC_RTH_SPDM_ECC_DB_ERR BIT(0)
782 #define XGE_HAL_RMAC_LINK_STATE_CHANGE_INT BIT(0)
783 #define XGE_HAL_RMAC_RX_SM_ERR BIT(39)
790 #define XGE_HAL_MAC_CFG_TMAC_ENABLE BIT(0)
791 #define XGE_HAL_MAC_CFG_RMAC_ENABLE BIT(1)
792 #define XGE_HAL_MAC_CFG_LAN_NOT_WAN BIT(2)
793 #define XGE_HAL_MAC_CFG_TMAC_LOOPBACK BIT(3)
794 #define XGE_HAL_MAC_CFG_TMAC_APPEND_PAD BIT(4)
795 #define XGE_HAL_MAC_CFG_RMAC_STRIP_FCS BIT(5)
796 #define XGE_HAL_MAC_CFG_RMAC_STRIP_PAD BIT(6)
797 #define XGE_HAL_MAC_CFG_RMAC_PROM_ENABLE BIT(7)
798 #define XGE_HAL_MAC_RMAC_DISCARD_PFRM BIT(8)
799 #define XGE_HAL_MAC_RMAC_BCAST_ENABLE BIT(9)
800 #define XGE_HAL_MAC_RMAC_ALL_ADDR_ENABLE BIT(10)
810 #define XGE_HAL_RMAC_ERR_FCS BIT(0)
811 #define XGE_HAL_RMAC_ERR_FCS_ACCEPT BIT(1)
812 #define XGE_HAL_RMAC_ERR_TOO_LONG BIT(1)
813 #define XGE_HAL_RMAC_ERR_TOO_LONG_ACCEPT BIT(1)
814 #define XGE_HAL_RMAC_ERR_RUNT BIT(2)
815 #define XGE_HAL_RMAC_ERR_RUNT_ACCEPT BIT(2)
816 #define XGE_HAL_RMAC_ERR_LEN_MISMATCH BIT(3)
817 #define XGE_HAL_RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3)
828 #define XGE_HAL_RMAC_ADDR_CMD_MEM_WE BIT(7)
830 #define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15)
831 #define XGE_HAL_RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15)
836 #define XGE_HAL_RMAC_ADDR_DATA0_MEM_USER BIT(48)
853 #define XGE_HAL_RMAC_PAUSE_GEN_EN BIT(0)
854 #define XGE_HAL_RMAC_PAUSE_RCV_EN BIT(1)
885 #define XGE_HAL_RTS_DIX_MAP_SCW(val) BIT(val,21)
892 #define XGE_HAL_RTS_CTRL_IGNORE_SNAP_OUI BIT(2)
893 #define XGE_HAL_RTS_CTRL_IGNORE_LLC_CTRL BIT(3)
894 #define XGE_HAL_RTS_CTRL_ENHANCED_MODE BIT(7)
897 #define XGE_HAL_RTS_PN_CAM_CTRL_WE BIT(7)
898 #define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15)
899 #define XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15)
902 #define XGE_HAL_RTS_PN_CAM_DATA_TCP_SELECT BIT(7)
907 #define XGE_HAL_RTS_DS_MEM_CTRL_WE BIT(7)
908 #define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15)
909 #define XGE_HAL_RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15)
924 #define XGE_HAL_RTS_MAC_SECT0_EN BIT(0)
925 #define XGE_HAL_RTS_MAC_SECT1_EN BIT(1)
926 #define XGE_HAL_RTS_MAC_SECT2_EN BIT(2)
927 #define XGE_HAL_RTS_MAC_SECT3_EN BIT(3)
928 #define XGE_HAL_RTS_MAC_SECT4_EN BIT(4)
929 #define XGE_HAL_RTS_MAC_SECT5_EN BIT(5)
930 #define XGE_HAL_RTS_MAC_SECT6_EN BIT(6)
931 #define XGE_HAL_RTS_MAC_SECT7_EN BIT(7)
936 #define XGE_HAL_RTS_RTH_EN BIT(3)
938 #define XGE_HAL_RTS_RTH_ALG_SEL_MS BIT(11)
939 #define XGE_HAL_RTS_RTH_TCP_IPV4_EN BIT(15)
940 #define XGE_HAL_RTS_RTH_UDP_IPV4_EN BIT(19)
941 #define XGE_HAL_RTS_RTH_IPV4_EN BIT(23)
942 #define XGE_HAL_RTS_RTH_TCP_IPV6_EN BIT(27)
943 #define XGE_HAL_RTS_RTH_UDP_IPV6_EN BIT(31)
944 #define XGE_HAL_RTS_RTH_IPV6_EN BIT(35)
945 #define XGE_HAL_RTS_RTH_TCP_IPV6_EX_EN BIT(39)
946 #define XGE_HAL_RTS_RTH_UDP_IPV6_EX_EN BIT(43)
947 #define XGE_HAL_RTS_RTH_IPV6_EX_EN BIT(47)
950 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_WE BIT(7)
951 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_STROBE BIT(15)
955 #define XGE_HAL_RTS_RTH_MAP_MEM_DATA_ENTRY_EN BIT(3)
959 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_STROBE BIT(15)
974 #define XGE_HAL_RTH_STATUS_SPDM_USE_L4 BIT(3)
1028 #define XGE_HAL_MC_INT_STATUS_MC_INT BIT(0)
1030 #define XGE_HAL_MC_INT_MASK_MC_INT BIT(0)
1033 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_L BIT(2) /* non-Xena */
1034 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_U BIT(3) /* non-Xena */
1035 #define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_L BIT(4) /* non-Xena */
1036 #define XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_U BIT(5) /* non-Xena */
1037 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_L BIT(6)
1038 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_U BIT(7)
1039 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_L BIT(10) /* non-Xena */
1040 #define XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_U BIT(11) /* non-Xena */
1041 #define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_L BIT(12) /* non-Xena */
1042 #define XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_U BIT(13) /* non-Xena */
1043 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_L BIT(14)
1044 #define XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_U BIT(15)
1045 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_0 BIT(17)
1046 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18) /* Xena: reset */
1047 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_1 BIT(19)
1048 #define XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20) /* Xena: reset */
1049 #define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22)
1050 #define XGE_HAL_MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23)
1051 #define XGE_HAL_MC_ERR_REG_SM_ERR BIT(31)
1052 #define XGE_HAL_MC_ERR_REG_PL_LOCK_N BIT(39)
1071 #define XGE_HAL_MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39)
1072 #define XGE_HAL_MC_RLDRAM_MRS_ENABLE BIT(47)
1085 #define XGE_HAL_MC_RLDRAM_TEST_MODE BIT(47)
1086 #define XGE_HAL_MC_RLDRAM_TEST_WRITE BIT(7)
1087 #define XGE_HAL_MC_RLDRAM_TEST_GO BIT(15)
1088 #define XGE_HAL_MC_RLDRAM_TEST_DONE BIT(23)
1089 #define XGE_HAL_MC_RLDRAM_TEST_PASS BIT(31)
1138 #define XGE_HAL_XGXS_INT_STATUS_TXGXS BIT(0)
1139 #define XGE_HAL_XGXS_INT_STATUS_RXGXS BIT(1)
1141 #define XGE_HAL_XGXS_INT_MASK_TXGXS BIT(0)
1142 #define XGE_HAL_XGXS_INT_MASK_RXGXS BIT(1)
1145 #define XGE_HAL_TXGXS_ECC_SG_ERR BIT(7)
1146 #define XGE_HAL_TXGXS_ECC_DB_ERR BIT(15)
1147 #define XGE_HAL_TXGXS_ESTORE_UFLOW BIT(31)
1148 #define XGE_HAL_TXGXS_TX_SM_ERR BIT(39)
1153 #define XGE_HAL_RXGXS_ESTORE_OFLOW BIT(7)
1154 #define XGE_HAL_RXGXS_RX_SM_ERR BIT(39)