Lines Matching defs:ixgbe
40 ixgbe_t *ixgbe = (ixgbe_t *)adapter;
41 struct ixgbe_hw *hw = &ixgbe->hw;
49 ixgbe_log(ixgbe, "interrupt: %s\n", tag);
50 ixgbe_log(ixgbe, "..eims: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_EIMS));
51 ixgbe_log(ixgbe, "..eimc: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_EIMC));
52 ixgbe_log(ixgbe, "..eiac: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_EIAC));
53 ixgbe_log(ixgbe, "..eiam: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_EIAM));
54 ixgbe_log(ixgbe, "..gpie: 0x%x\n", IXGBE_READ_REG(hw, IXGBE_GPIE));
55 ixgbe_log(ixgbe, "otherflag: 0x%x\n", ixgbe->capab->other_intr);
56 ixgbe_log(ixgbe, "eims_mask: 0x%x\n", ixgbe->eims);
61 ixgbe_log(ixgbe, "ivar[%d]: 0x%x\n", i, ivar);
66 for (i = 0; i < ixgbe->intr_cnt; i++) {
67 vect = &ixgbe->vect_map[i];
68 ixgbe_log(ixgbe,
74 j = bt_getlowbit(vect->rx_map, 0, (ixgbe->num_rx_rings - 1));
76 hw_index = ixgbe->rx_rings[j].hw_index;
77 ixgbe_log(ixgbe, "rx %d ivar %d rxdctl: 0x%x srrctl: 0x%x\n",
82 (ixgbe->num_rx_rings - 1));
86 j = bt_getlowbit(vect->tx_map, 0, (ixgbe->num_tx_rings - 1));
88 ixgbe_log(ixgbe, "tx %d ivar %d txdctl: 0x%x\n",
92 (ixgbe->num_tx_rings - 1));
98 ixgbe_log(ixgbe, "reta(%d): 0x%x\n",
104 ixgbe_log(ixgbe, "rssrk(%d): 0x%x\n",
109 ixgbe_log(ixgbe, "-- ral/rah --\n");
112 ixgbe_log(ixgbe, "ral(%d): 0x%x rah(%d): 0x%x\n",
118 ixgbe_log(ixgbe, "-- mta --\n");
121 ixgbe_log(ixgbe, "mta(%d): 0x%x\n", i, reg);
128 ixgbe_log(ixgbe, "-- vfta --\n");
131 ixgbe_log(ixgbe, "vfta(0x%x): 0x%x\n", off, reg);
138 ixgbe_log(ixgbe, "-- mdef --\n");
141 ixgbe_log(ixgbe, "mdef(%d): 0x%x\n", i, reg);
152 ixgbe_t *ixgbe = (ixgbe_t *)adapter;
159 ixgbe_log(ixgbe, "%s %s\n", tag, form);
165 ixgbe_t *ixgbe = (ixgbe_t *)arg;
182 handle = ixgbe->osdep.cfg_handle;
184 ixgbe_log(ixgbe, "Begin dump PCI config space");
186 ixgbe_log(ixgbe,
189 ixgbe_log(ixgbe,
192 ixgbe_log(ixgbe,
195 ixgbe_log(ixgbe,
198 ixgbe_log(ixgbe,
201 ixgbe_log(ixgbe,
204 ixgbe_log(ixgbe,
207 ixgbe_log(ixgbe,
210 ixgbe_log(ixgbe,
213 ixgbe_log(ixgbe,
216 ixgbe_log(ixgbe,
219 ixgbe_log(ixgbe,
222 ixgbe_log(ixgbe,
225 ixgbe_log(ixgbe,
228 ixgbe_log(ixgbe,
234 ixgbe_log(ixgbe,
237 ixgbe_log(ixgbe,
240 ixgbe_log(ixgbe,
243 ixgbe_log(ixgbe,
246 ixgbe_log(ixgbe,
249 ixgbe_log(ixgbe,
252 ixgbe_log(ixgbe,
258 ixgbe_log(ixgbe,
260 ixgbe_log(ixgbe,
263 ixgbe_log(ixgbe,
266 ixgbe_log(ixgbe,
269 ixgbe_log(ixgbe,
276 ixgbe_log(ixgbe,
282 ixgbe_log(ixgbe,
284 ixgbe_log(ixgbe,
287 ixgbe_log(ixgbe,
290 ixgbe_log(ixgbe,
293 ixgbe_log(ixgbe,
300 ixgbe_log(ixgbe,
306 ixgbe_log(ixgbe,
308 ixgbe_log(ixgbe,
311 ixgbe_log(ixgbe,
314 ixgbe_log(ixgbe,
317 ixgbe_log(ixgbe,
324 ixgbe_log(ixgbe,
329 ixgbe_log(ixgbe,
334 ixgbe_log(ixgbe,
340 ixgbe_log(ixgbe,
342 ixgbe_log(ixgbe,
348 ixgbe_log(ixgbe,
350 ixgbe_log(ixgbe,
356 ixgbe_log(ixgbe,
362 ixgbe_log(ixgbe,
364 ixgbe_log(ixgbe,
367 ixgbe_log(ixgbe,
370 ixgbe_log(ixgbe,
373 ixgbe_log(ixgbe,
376 ixgbe_log(ixgbe,
379 ixgbe_log(ixgbe,
382 ixgbe_log(ixgbe,
387 if (ddi_dev_regsize(ixgbe->dip, 4, &mem_size) != DDI_SUCCESS) {
388 ixgbe_log(ixgbe, "ddi_dev_regsize() failed");
392 if ((ddi_regs_map_setup(ixgbe->dip, 4, (caddr_t *)&base, 0, mem_size,
394 ixgbe_log(ixgbe, "ddi_regs_map_setup() failed");
398 ixgbe_log(ixgbe, "MSI-X Memory Space: (mem_size = %d, base = %x)",
402 ixgbe_log(ixgbe, "MSI-X Table Entry(%d):", i);
403 ixgbe_log(ixgbe, "lo_addr:\t%x",
406 ixgbe_log(ixgbe, "up_addr:\t%x",
409 ixgbe_log(ixgbe, "msg_data:\t%x",
412 ixgbe_log(ixgbe, "vct_ctrl:\t%x",
417 ixgbe_log(ixgbe, "MSI-X Pending Bits:\t%x",
429 ixgbe_t *ixgbe = (ixgbe_t *)adapter;
431 struct ixgbe_hw *hw = &ixgbe->hw;
436 ixgbe_log(ixgbe, "Basic IXGBE registers..");
438 ixgbe_log(ixgbe, "\tCTRL=%x\n", reg_val);
440 ixgbe_log(ixgbe, "\tSTATUS=%x\n", reg_val);
442 ixgbe_log(ixgbe, "\tCTRL_EXT=%x\n", reg_val);
444 ixgbe_log(ixgbe, "\tFCTRL=%x\n", reg_val);
447 ixgbe_log(ixgbe, "Some IXGBE interrupt registers..");
450 ixgbe_log(ixgbe, "\tGPIE=%x\n", reg_val);
453 ixgbe_log(ixgbe, "\tIVAR(0)=%x\n", reg_val);
456 ixgbe_log(ixgbe, "\tIVAR_MISC=%x\n", reg_val);
459 ixgbe_log(ixgbe, "Receive registers...");
461 ixgbe_log(ixgbe, "\tRXCTRL=%x\n", reg_val);
462 for (i = 0; i < ixgbe->num_rx_rings; i++) {
463 hw_index = ixgbe->rx_rings[i].hw_index;
465 ixgbe_log(ixgbe, "\tRXDCTL(%d)=%x\n", hw_index, reg_val);
467 ixgbe_log(ixgbe, "\tSRRCTL(%d)=%x\n", hw_index, reg_val);
470 ixgbe_log(ixgbe, "\tRXCSUM=%x\n", reg_val);
472 ixgbe_log(ixgbe, "\tMRQC=%x\n", reg_val);
474 ixgbe_log(ixgbe, "\tRDRXCTL=%x\n", reg_val);
477 ixgbe_log(ixgbe, "Some transmit registers..");
479 ixgbe_log(ixgbe, "\tDMATXCTL=%x\n", reg_val);
480 for (i = 0; i < ixgbe->num_tx_rings; i++) {
482 ixgbe_log(ixgbe, "\tTXDCTL(%d)=%x\n", i, reg_val);
484 ixgbe_log(ixgbe, "\tTDWBAL(%d)=%x\n", i, reg_val);
486 ixgbe_log(ixgbe, "\tTDWBAH(%d)=%x\n", i, reg_val);
488 ixgbe_log(ixgbe, "\tTXPBSIZE(%d)=%x\n", i, reg_val);