Lines Matching refs:ip
261 iprb_t *ip;
266 ip = kmem_zalloc(sizeof (*ip), KM_SLEEP);
267 ddi_set_driver_private(dip, ip);
268 ip->dip = dip;
270 list_create(&ip->mcast, sizeof (struct iprb_mcast),
274 mutex_init(&ip->culock, NULL, MUTEX_DRIVER, NULL);
275 mutex_init(&ip->rulock, NULL, MUTEX_DRIVER, NULL);
277 if (pci_config_setup(dip, &ip->pcih) != DDI_SUCCESS) {
278 iprb_error(ip, "unable to map configuration space");
279 iprb_destroy(ip);
283 if (ddi_regs_map_setup(dip, 1, &ip->regs, 0, 0, &acc_attr,
284 &ip->regsh) != DDI_SUCCESS) {
285 iprb_error(ip, "unable to map device registers");
286 iprb_destroy(ip);
291 PUT32(ip, CSR_PORT, PORT_SEL_RESET);
293 PUT32(ip, CSR_PORT, PORT_SW_RESET);
295 PUT8(ip, CSR_INTCTL, INTCTL_MASK);
296 (void) GET8(ip, CSR_INTCTL);
301 ip->tx_timeout = TX_WATCHDOG;
302 ip->rx_timeout = RX_WATCHDOG;
304 iprb_identify(ip);
307 w = iprb_eeprom_read(ip, 0);
308 ip->factaddr[0] = w & 0xff;
309 ip->factaddr[1] = w >> 8;
310 w = iprb_eeprom_read(ip, 1);
311 ip->factaddr[2] = w & 0xff;
312 ip->factaddr[3] = w >> 8;
313 w = iprb_eeprom_read(ip, 2);
314 ip->factaddr[4] = w & 0xff;
315 ip->factaddr[5] = w >> 8;
316 bcopy(ip->factaddr, ip->curraddr, 6);
318 if (ip->resumebug) {
326 if ((iprb_eeprom_read(ip, 10) & 0x02) == 0) {
328 ip->resumebug = B_FALSE;
332 if ((iprb_eeprom_read(ip, 3) & 0x3) != 0x3) {
334 ip->rxhangbug = B_TRUE;
338 w = iprb_eeprom_read(ip, 6);
340 if ((ip->miih = mii_alloc(ip, dip, &iprb_mii_ops)) == NULL) {
341 iprb_error(ip, "unable to allocate MII ops vector");
342 iprb_destroy(ip);
345 if (ip->canpause) {
346 mii_set_pauseable(ip->miih, B_TRUE, B_FALSE);
353 if (iprb_dma_alloc(ip, &ip->cmds[i], CB_SIZE) != DDI_SUCCESS) {
354 iprb_destroy(ip);
360 iprb_dma_t *cb = &ip->cmds[i];
362 PUTCB32(cb, CB_LNK_OFFSET, (ip->cmds[(i + 1) % NUM_TX].paddr));
367 if (iprb_dma_alloc(ip, &ip->rxb[i], RFD_SIZE) != DDI_SUCCESS) {
368 iprb_destroy(ip);
372 if (iprb_dma_alloc(ip, &ip->stats, STATS_SIZE) != DDI_SUCCESS) {
373 iprb_destroy(ip);
377 if (iprb_add_intr(ip) != DDI_SUCCESS) {
378 iprb_destroy(ip);
383 iprb_error(ip, "unable to allocate mac structure");
384 iprb_destroy(ip);
389 macp->m_driver = ip;
391 macp->m_src_addr = ip->curraddr;
396 if (mac_register(macp, &ip->mach) != 0) {
397 iprb_error(ip, "unable to register mac with framework");
399 iprb_destroy(ip);
410 iprb_t *ip;
412 ip = ddi_get_driver_private(dip);
413 ASSERT(ip != NULL);
415 if (mac_disable(ip->mach) != 0)
418 (void) mac_unregister(ip->mach);
419 iprb_destroy(ip);
424 iprb_add_intr(iprb_t *ip)
428 if (ddi_intr_alloc(ip->dip, &ip->intrh, DDI_INTR_TYPE_FIXED, 0, 1,
430 iprb_error(ip, "failed allocating interrupt handle");
434 if (ddi_intr_add_handler(ip->intrh, iprb_intr, ip, NULL) !=
436 (void) ddi_intr_free(ip->intrh);
437 ip->intrh = NULL;
438 iprb_error(ip, "failed adding interrupt handler");
441 if (ddi_intr_enable(ip->intrh) != DDI_SUCCESS) {
442 (void) ddi_intr_remove_handler(ip->intrh);
443 (void) ddi_intr_free(ip->intrh);
444 ip->intrh = NULL;
445 iprb_error(ip, "failed enabling interrupt");
452 iprb_dma_alloc(iprb_t *ip, iprb_dma_t *h, size_t size)
458 if (ddi_dma_alloc_handle(ip->dip, &dma_attr, DDI_DMA_SLEEP, NULL,
460 iprb_error(ip, "unable to allocate dma handle");
465 iprb_error(ip, "unable to allocate dma memory");
472 iprb_error(ip, "unable to map command memory");
494 iprb_destroy(iprb_t *ip)
500 if (ip->intrh != NULL) {
501 (void) ddi_intr_disable(ip->intrh);
502 (void) ddi_intr_remove_handler(ip->intrh);
503 (void) ddi_intr_free(ip->intrh);
507 iprb_dma_free(&ip->cmds[i]);
510 iprb_dma_free(&ip->rxb[i]);
512 iprb_dma_free(&ip->stats);
514 if (ip->miih)
515 mii_free(ip->miih);
518 while ((mc = list_head(&ip->mcast)) != NULL) {
519 list_remove(&ip->mcast, mc);
524 if (ip->pcih)
525 pci_config_teardown(&ip->pcih);
526 if (ip->regsh)
527 ddi_regs_map_free(&ip->regsh);
530 ddi_set_driver_private(ip->dip, NULL);
532 list_destroy(&ip->mcast);
533 mutex_destroy(&ip->culock);
534 mutex_destroy(&ip->rulock);
537 kmem_free(ip, sizeof (*ip));
541 iprb_identify(iprb_t *ip)
543 ip->devid = pci_config_get16(ip->pcih, PCI_CONF_DEVID);
544 ip->revid = pci_config_get8(ip->pcih, PCI_CONF_REVID);
546 switch (ip->devid) {
550 if (ip->revid >= REV_82558_A4) {
551 ip->canpause = B_TRUE;
552 ip->canmwi = B_TRUE;
554 ip->is557 = B_TRUE;
556 if (ip->revid >= REV_82559_A0)
557 ip->resumebug = B_TRUE;
561 ip->canpause = B_TRUE;
562 ip->resumebug = B_TRUE;
563 ip->canmwi = B_TRUE;
572 ip->resumebug = B_TRUE;
573 if (ip->revid >= REV_82558_A4)
574 ip->canpause = B_TRUE;
578 if (ip->revid >= REV_82558_A4)
579 ip->canpause = B_TRUE;
584 if (ddi_prop_get_int(DDI_DEV_T_ANY, ip->dip, 0, "MWIEnable", 1) == 0) {
585 ip->canmwi = B_FALSE;
590 iprb_eeprom_sendbits(iprb_t *ip, uint32_t val, uint8_t nbits)
598 PUT16(ip, CSR_EECTL, x | EEPROM_EECS);
600 PUT16(ip, CSR_EECTL, x | EEPROM_EESK | EEPROM_EECS);
602 PUT16(ip, CSR_EECTL, x | EEPROM_EECS);
609 iprb_eeprom_read(iprb_t *ip, uint16_t address)
617 if ((address != 0) && (ip->eeprom_bits == 0))
618 (void) iprb_eeprom_read(ip, 0);
620 if ((bits = ip->eeprom_bits) == 0) {
625 PUT16(ip, CSR_EECTL, EEPROM_EECS);
629 iprb_eeprom_sendbits(ip, 6, 3);
633 PUT16(ip, CSR_EECTL, x | EEPROM_EECS);
635 PUT16(ip, CSR_EECTL, x | EEPROM_EESK | EEPROM_EECS);
637 PUT16(ip, CSR_EECTL, x | EEPROM_EECS);
642 if ((GET16(ip, CSR_EECTL) & EEPROM_EEDO) == 0) {
643 if (ip->eeprom_bits == 0) {
644 ip->eeprom_bits = n;
646 1U << ip->eeprom_bits);
651 if (n != ip->eeprom_bits) {
652 iprb_error(ip, "cannot determine EEPROM size (%d, %d)",
653 ip->eeprom_bits, n);
659 PUT16(ip, CSR_EECTL, EEPROM_EECS | EEPROM_EESK);
661 if (GET16(ip, CSR_EECTL) & EEPROM_EEDO)
664 PUT16(ip, CSR_EECTL, EEPROM_EECS);
669 PUT16(ip, CSR_EECTL, 0);
676 iprb_cmd_ready(iprb_t *ip)
680 if (GET8(ip, CSR_CMD) == 0) {
685 iprb_error(ip, "timeout waiting for chip to become ready");
690 iprb_cmd_reclaim(iprb_t *ip)
692 while (ip->cmd_count) {
693 iprb_dma_t *cb = &ip->cmds[ip->cmd_tail];
700 ip->cmd_tail++;
701 ip->cmd_tail %= NUM_TX;
702 ip->cmd_count--;
703 if (ip->cmd_count == 0) {
704 ip->tx_wdog = 0;
706 ip->tx_wdog = gethrtime();
712 iprb_cmd_drain(iprb_t *ip)
715 iprb_cmd_reclaim(ip);
716 if (ip->cmd_count == 0)
720 iprb_error(ip, "time out waiting for commands to drain");
725 iprb_cmd_submit(iprb_t *ip, uint16_t cmd)
727 iprb_dma_t *ncb = &ip->cmds[ip->cmd_head];
728 iprb_dma_t *lcb = &ip->cmds[ip->cmd_last];
731 ASSERT((ip->cmd_count) < NUM_TX);
732 if (ip->cmd_count == (NUM_TX - 1)) {
757 if (ip->resumebug) {
758 if (iprb_cmd_ready(ip) != DDI_SUCCESS)
760 PUT8(ip, CSR_CMD, CUC_NOP);
761 (void) GET8(ip, CSR_CMD);
766 if (iprb_cmd_ready(ip) != DDI_SUCCESS)
775 PUT8(ip, CSR_CMD, CUC_RESUME);
776 (void) GET8(ip, CSR_CMD); /* flush CSR */
778 ip->tx_wdog = gethrtime();
779 ip->cmd_last = ip->cmd_head;
780 ip->cmd_head++;
781 ip->cmd_head %= NUM_TX;
782 ip->cmd_count++;
788 iprb_cmd_next(iprb_t *ip)
790 if (ip->cmd_count == NUM_TX) {
793 ASSERT(ip->cmd_count < NUM_TX);
794 return (&ip->cmds[ip->cmd_head]);
798 iprb_set_unicast(iprb_t *ip)
802 ASSERT(mutex_owned(&ip->culock));
804 if ((cb = iprb_cmd_next(ip)) == NULL)
807 PUTCBEA(cb, CB_IAS_ADR_OFFSET, ip->curraddr);
808 return (iprb_cmd_submit(ip, CB_CMD_IAS));
812 iprb_set_multicast(iprb_t *ip)
819 ASSERT(mutex_owned(&ip->culock));
821 if ((ip->nmcast <= 0) || (ip->nmcast > CB_MCS_CNT_MAX)) {
832 if ((cb = iprb_cmd_next(ip)) == NULL) {
836 l = &ip->mcast;
840 ASSERT(i == ip->nmcast);
842 return (iprb_cmd_submit(ip, CB_CMD_MCS));
846 iprb_set_config(iprb_t *ip)
850 ASSERT(mutex_owned(&ip->culock));
851 if ((cb = iprb_cmd_next(ip)) == NULL) {
857 PUTCB8(cb, CB_CONFIG_OFFSET + 3, (ip->canmwi ? 1 : 0));
860 PUTCB8(cb, CB_CONFIG_OFFSET + 6, (ip->promisc ? 0x80 : 0) | 0x3a);
861 PUTCB8(cb, CB_CONFIG_OFFSET + 7, (ip->promisc ? 0 : 0x1) | 2);
862 PUTCB8(cb, CB_CONFIG_OFFSET + 8, (ip->miih ? 0x1 : 0));
866 PUTCB8(cb, CB_CONFIG_OFFSET + 12, (ip->is557 ? 0 : 1) | 0x60);
870 (ip->miih ? 0x80 : 0) | (ip->promisc ? 0x1 : 0) | 0x48);
872 PUTCB8(cb, CB_CONFIG_OFFSET + 17, (ip->canpause ? 0x40 : 0));
873 PUTCB8(cb, CB_CONFIG_OFFSET + 18, (ip->is557 ? 0 : 0x8) | 0xf2);
875 ((ip->revid < REV_82558_B0) ? 0 : 0x80) |
876 (ip->canpause ? 0x18 : 0));
879 ((ip->nmcast >= CB_MCS_CNT_MAX) ? 0x8 : 0) | 0x5);
881 return (iprb_cmd_submit(ip, CB_CMD_CONFIG));
885 iprb_set_ucode(iprb_t *ip)
892 if (iprb_ucode[i].rev == ip->revid) {
902 ASSERT(mutex_owned(&ip->culock));
903 if ((cb = iprb_cmd_next(ip)) == NULL) {
909 return (iprb_cmd_submit(ip, CB_CMD_UCODE));
913 iprb_configure(iprb_t *ip)
915 ASSERT(mutex_owned(&ip->culock));
917 if (iprb_cmd_drain(ip) != DDI_SUCCESS)
920 if (iprb_set_config(ip) != DDI_SUCCESS)
922 if (iprb_set_unicast(ip) != DDI_SUCCESS)
924 if (iprb_set_multicast(ip) != DDI_SUCCESS)
931 iprb_stop(iprb_t *ip)
934 PUT32(ip, CSR_PORT, PORT_SEL_RESET);
935 (void) GET32(ip, CSR_PORT);
939 PUT8(ip, CSR_INTCTL, INTCTL_MASK);
943 iprb_start(iprb_t *ip)
947 ASSERT(mutex_owned(&ip->rulock));
948 ASSERT(mutex_owned(&ip->culock));
951 PUT32(ip, CSR_PORT, PORT_SEL_RESET);
952 (void) GET32(ip, CSR_PORT);
955 PUT32(ip, CSR_PORT, PORT_SW_RESET);
956 (void) GET32(ip, CSR_PORT);
958 PUT8(ip, CSR_INTCTL, INTCTL_MASK);
961 ip->cmd_head = ip->cmd_tail = 0;
962 ip->cmd_last = NUM_TX - 1;
964 if (iprb_cmd_ready(ip) != DDI_SUCCESS)
966 PUT32(ip, CSR_GEN_PTR, 0);
967 PUT8(ip, CSR_CMD, CUC_CUBASE);
968 (void) GET8(ip, CSR_CMD);
970 if (iprb_cmd_ready(ip) != DDI_SUCCESS)
972 PUT32(ip, CSR_GEN_PTR, 0);
973 PUT8(ip, CSR_CMD, RUC_RUBASE);
974 (void) GET8(ip, CSR_CMD);
977 cb = iprb_cmd_next(ip);
979 if (iprb_cmd_submit(ip, CB_CMD_NOP) != DDI_SUCCESS)
983 if (iprb_cmd_ready(ip) != DDI_SUCCESS)
985 PUT32(ip, CSR_GEN_PTR, cb->paddr);
986 PUT8(ip, CSR_CMD, CUC_START);
987 (void) GET8(ip, CSR_CMD);
990 if (iprb_set_ucode(ip) != DDI_SUCCESS)
994 iprb_rx_init(ip);
996 PUT32(ip, CSR_GEN_PTR, ip->rxb[0].paddr);
998 (void) iprb_cmd_ready(ip);
999 PUT8(ip, CSR_CMD, RUC_START);
1000 (void) GET8(ip, CSR_CMD); /* flush CSR */
1003 PUT8(ip, CSR_INTCTL, 0);
1004 (void) GET8(ip, CSR_INTCTL);
1010 iprb_update_stats(iprb_t *ip)
1012 iprb_dma_t *sp = &ip->stats;
1016 ASSERT(mutex_owned(&ip->culock));
1020 if (tstamp / NANOSEC == ip->stats_time / NANOSEC)
1026 if (iprb_cmd_ready(ip) != DDI_SUCCESS)
1028 PUT32(ip, CSR_GEN_PTR, sp->paddr);
1029 PUT8(ip, CSR_CMD, CUC_STATSBASE);
1030 (void) GET8(ip, CSR_CMD);
1032 if (iprb_cmd_ready(ip) != DDI_SUCCESS)
1034 PUT8(ip, CSR_CMD, CUC_STATS_RST);
1035 (void) GET8(ip, CSR_CMD); /* flush wb */
1046 iprb_error(ip, "time out acquiring hardware statistics");
1050 ip->ex_coll += GETSTAT(sp, STATS_TX_MAXCOL_OFFSET);
1051 ip->late_coll += GETSTAT(sp, STATS_TX_LATECOL_OFFSET);
1052 ip->uflo += GETSTAT(sp, STATS_TX_UFLO_OFFSET);
1053 ip->defer_xmt += GETSTAT(sp, STATS_TX_DEFER_OFFSET);
1054 ip->one_coll += GETSTAT(sp, STATS_TX_ONECOL_OFFSET);
1055 ip->multi_coll += GETSTAT(sp, STATS_TX_MULTCOL_OFFSET);
1056 ip->collisions += GETSTAT(sp, STATS_TX_TOTCOL_OFFSET);
1057 ip->fcs_errs += GETSTAT(sp, STATS_RX_FCS_OFFSET);
1058 ip->align_errs += GETSTAT(sp, STATS_RX_ALIGN_OFFSET);
1059 ip->norcvbuf += GETSTAT(sp, STATS_RX_NOBUF_OFFSET);
1060 ip->oflo += GETSTAT(sp, STATS_RX_OFLO_OFFSET);
1061 ip->runt += GETSTAT(sp, STATS_RX_SHORT_OFFSET);
1063 ip->stats_time = tstamp;
1067 iprb_send(iprb_t *ip, mblk_t *mp)
1072 ASSERT(mutex_owned(&ip->culock));
1075 iprb_cmd_reclaim(ip);
1077 cb = iprb_cmd_next(ip);
1081 ip->wantw = B_TRUE;
1087 ip->macxmt_errs++;
1092 ip->opackets++;
1093 ip->obytes += sz;
1102 ip->multixmt++;
1104 ip->brdcstxmt++;
1109 if (iprb_cmd_submit(ip, CB_CMD_TX) != DDI_SUCCESS) {
1110 ip->macxmt_errs++;
1117 iprb_rx_add(iprb_t *ip)
1122 ASSERT(mutex_owned(&ip->rulock));
1124 curr = ip->rx_index;
1125 last = ip->rx_last;
1128 ip->rx_last = curr;
1129 ip->rx_index = next;
1131 lfd = &ip->rxb[last];
1132 rfd = &ip->rxb[curr];
1133 nfd = &ip->rxb[next];
1146 iprb_rx_init(iprb_t *ip)
1148 ip->rx_index = 0;
1149 ip->rx_last = NUM_RX - 1;
1151 iprb_rx_add(ip);
1152 ip->rx_index = 0;
1153 ip->rx_last = NUM_RX - 1;
1157 iprb_rx(iprb_t *ip)
1171 rfd = &ip->rxb[ip->rx_index];
1177 ip->rx_wdog = gethrtime();
1185 ip->toolong++;
1186 iprb_rx_add(ip);
1190 iprb_rx_add(ip);
1194 ip->norcvbuf++;
1195 iprb_rx_add(ip);
1201 iprb_rx_add(ip);
1204 ip->ipackets++;
1205 ip->rbytes += cnt;
1208 ip->multircv++;
1210 ip->brdcstrcv++;
1222 iprb_t *ip = arg;
1224 mutex_enter(&ip->culock);
1225 ip->promisc = on;
1226 if (ip->running && !ip->suspended)
1227 (void) iprb_configure(ip);
1228 mutex_exit(&ip->culock);
1235 iprb_t *ip = arg;
1237 mutex_enter(&ip->culock);
1238 bcopy(macaddr, ip->curraddr, 6);
1239 if (ip->running && !ip->suspended)
1240 (void) iprb_configure(ip);
1241 mutex_exit(&ip->culock);
1248 iprb_t *ip = arg;
1249 list_t *l = &ip->mcast;
1258 mutex_enter(&ip->culock);
1260 ip->nmcast++;
1261 if (ip->running && !ip->suspended)
1262 (void) iprb_configure(ip);
1263 mutex_exit(&ip->culock);
1265 mutex_enter(&ip->culock);
1268 list_remove(&ip->mcast, mc);
1269 ip->nmcast--;
1270 if (ip->running && !ip->suspended)
1271 (void) iprb_configure(ip);
1275 mutex_exit(&ip->culock);
1286 iprb_t *ip = arg;
1288 mutex_enter(&ip->rulock);
1289 mutex_enter(&ip->culock);
1290 rv = ip->suspended ? 0 : iprb_start(ip);
1292 ip->running = B_TRUE;
1293 ip->perh = ddi_periodic_add(iprb_periodic, ip, 5000000000, 0);
1294 mutex_exit(&ip->culock);
1295 mutex_exit(&ip->rulock);
1297 if (ip->miih)
1298 mii_start(ip->miih);
1301 mac_link_update(ip->mach, LINK_STATE_UP);
1309 iprb_t *ip = arg;
1311 if (ip->miih) {
1312 mii_stop(ip->miih);
1314 mac_link_update(ip->mach, LINK_STATE_DOWN);
1317 ddi_periodic_delete(ip->perh);
1318 ip->perh = 0;
1320 mutex_enter(&ip->rulock);
1321 mutex_enter(&ip->culock);
1323 if (!ip->suspended) {
1324 iprb_update_stats(ip);
1325 iprb_stop(ip);
1327 ip->running = B_FALSE;
1328 mutex_exit(&ip->culock);
1329 mutex_exit(&ip->rulock);
1335 iprb_t *ip = arg;
1337 if (ip->miih && (mii_m_getstat(ip->miih, stat, val) == 0)) {
1341 mutex_enter(&ip->culock);
1342 if ((!ip->suspended) && (ip->running)) {
1343 iprb_update_stats(ip);
1345 mutex_exit(&ip->culock);
1349 if (ip->miih == NULL) {
1354 if (ip->miih == NULL) {
1359 *val = ip->multircv;
1362 *val = ip->brdcstrcv;
1365 *val = ip->multixmt;
1368 *val = ip->brdcstxmt;
1371 * val = ip->ipackets;
1374 *val = ip->rbytes;
1377 *val = ip->opackets;
1380 *val = ip->obytes;
1383 *val = ip->norcvbuf;
1386 *val = ip->collisions;
1389 *val = ip->align_errs +
1390 ip->fcs_errs +
1391 ip->norcvbuf +
1392 ip->runt +
1393 ip->toolong +
1394 ip->macrcv_errs;
1397 *val = ip->ex_coll +
1398 ip->late_coll +
1399 ip->uflo +
1400 ip->macxmt_errs +
1401 ip->nocarrier;
1404 *val = ip->align_errs;
1407 *val = ip->fcs_errs;
1410 *val = ip->defer_xmt;
1413 *val = ip->one_coll + ip->multi_coll + ip->ex_coll;
1416 *val = ip->multi_coll;
1419 *val = ip->late_coll;
1422 *val = ip->ex_coll;
1425 *val = ip->oflo;
1428 *val = ip->uflo;
1431 *val = ip->runt;
1434 *val = ip->toolong;
1437 *val = ip->nocarrier; /* reported only for "suspend" */
1440 *val = ip->macxmt_errs;
1443 *val = ip->macrcv_errs;
1455 iprb_t *ip = arg;
1457 if (ip->miih != NULL) {
1458 mii_m_propinfo(ip->miih, name, id, pih);
1473 iprb_t *ip = arg;
1476 if (ip->miih != NULL) {
1477 return (mii_m_getprop(ip->miih, name, id, sz, val));
1498 iprb_t *ip = arg;
1500 if (ip->miih != NULL) {
1501 return (mii_m_setprop(ip->miih, name, id, sz, val));
1509 iprb_t *ip = arg;
1512 mutex_enter(&ip->culock);
1517 if (ip->suspended) {
1519 ip->nocarrier++;
1523 if ((mp = iprb_send(ip, mp)) != NULL) {
1529 mutex_exit(&ip->culock);
1536 iprb_t *ip = arg;
1538 if ((ip->miih != NULL) && (mii_m_loop_ioctl(ip->miih, wq, mp)))
1547 iprb_t *ip = arg;
1559 PUT32(ip, CSR_MDICTL, mdi);
1561 mdi = GET32(ip, CSR_MDICTL);
1573 iprb_t *ip = arg;
1581 PUT32(ip, CSR_MDICTL, mdi);
1583 if (GET32(ip, CSR_MDICTL) & MDI_R)
1591 iprb_t *ip = arg;
1593 mac_link_update(ip->mach, link);
1599 iprb_t *ip = (void *)arg1;
1605 mutex_enter(&ip->rulock);
1606 if (ip->suspended) {
1607 mutex_exit(&ip->rulock);
1610 sts = GET8(ip, CSR_STS);
1613 mutex_exit(&ip->rulock);
1617 PUT8(ip, CSR_STS, sts);
1620 mp = iprb_rx(ip);
1623 ((GET8(ip, CSR_STATE) & STATE_RUS) == STATE_RUS_NORES)) {
1624 iprb_rx_init(ip);
1626 mutex_enter(&ip->culock);
1627 PUT32(ip, CSR_GEN_PTR, ip->rxb[0].paddr);
1629 (void) iprb_cmd_ready(ip);
1630 PUT8(ip, CSR_CMD, RUC_START);
1631 (void) GET8(ip, CSR_CMD); /* flush CSR */
1632 mutex_exit(&ip->culock);
1635 mutex_exit(&ip->rulock);
1638 mac_rx(ip->mach, NULL, mp);
1640 if ((sts & (STS_CNA | STS_CX)) && ip->wantw) {
1641 ip->wantw = B_FALSE;
1642 mac_tx_update(ip->mach);
1650 iprb_t *ip = arg;
1653 mutex_enter(&ip->rulock);
1654 if (ip->suspended || !ip->running) {
1655 mutex_exit(&ip->rulock);
1664 if (ip->rxhangbug &&
1665 ((ip->miih == NULL) || (mii_get_speed(ip->miih) == 10000000)) &&
1666 ((gethrtime() - ip->rx_wdog) > ip->rx_timeout)) {
1672 mutex_enter(&ip->culock);
1674 if (ip->tx_wdog && ((gethrtime() - ip->tx_wdog) > ip->tx_timeout)) {
1682 iprb_stop(ip);
1683 if (iprb_start(ip) != DDI_SUCCESS) {
1684 iprb_error(ip, "unable to restart chip");
1688 iprb_update_stats(ip);
1690 mutex_exit(&ip->culock);
1691 mutex_exit(&ip->rulock);
1697 iprb_t *ip = ddi_get_driver_private(dip);
1700 PUT32(ip, CSR_PORT, PORT_SEL_RESET);
1702 PUT32(ip, CSR_PORT, PORT_SW_RESET);
1704 PUT8(ip, CSR_INTCTL, INTCTL_MASK);
1712 iprb_t *ip = ddi_get_driver_private(dip);
1714 if (ip->miih)
1715 mii_suspend(ip->miih);
1717 mutex_enter(&ip->rulock);
1718 mutex_enter(&ip->culock);
1719 if (!ip->suspended) {
1720 ip->suspended = B_TRUE;
1721 if (ip->running) {
1722 iprb_update_stats(ip);
1723 iprb_stop(ip);
1726 mutex_exit(&ip->culock);
1727 mutex_exit(&ip->rulock);
1734 iprb_t *ip = ddi_get_driver_private(dip);
1736 mutex_enter(&ip->rulock);
1737 mutex_enter(&ip->culock);
1739 ip->suspended = B_FALSE;
1740 if (ip->running) {
1741 if (iprb_start(ip) != DDI_SUCCESS) {
1742 iprb_error(ip, "unable to restart chip!");
1743 ip->suspended = B_TRUE;
1744 mutex_exit(&ip->culock);
1745 mutex_exit(&ip->rulock);
1750 mutex_exit(&ip->culock);
1751 mutex_exit(&ip->rulock);
1752 if (ip->miih)
1753 mii_resume(ip->miih);
1788 iprb_error(iprb_t *ip, const char *fmt, ...)
1798 ddi_driver_name(ip->dip), ddi_get_instance(ip->dip), buf);