Lines Matching defs:hw
37 enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
39 enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
41 enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
43 enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
45 enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
51 * @hw: pointer to the HW structure
59 enum i40e_status_code i40e_init_nvm(struct i40e_hw *hw)
61 struct i40e_nvm_info *nvm = &hw->nvm;
71 gens = rd32(hw, I40E_GLNVM_GENS);
78 fla = rd32(hw, I40E_GLNVM_FLA);
86 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n");
94 * @hw: pointer to the HW structure
100 enum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,
109 if (hw->nvm.blank_nvm_mode)
112 ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
115 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
118 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
121 i40e_debug(hw, I40E_DEBUG_NVM,
123 access, time_left, ret_code, hw->aq.asq_last_status);
130 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
131 ret_code = i40e_aq_request_resource(hw,
136 hw->nvm.hw_semaphore_timeout =
142 hw->nvm.hw_semaphore_timeout = 0;
143 i40e_debug(hw, I40E_DEBUG_NVM,
145 time_left, ret_code, hw->aq.asq_last_status);
155 * @hw: pointer to the HW structure
159 void i40e_release_nvm(struct i40e_hw *hw)
166 if (hw->nvm.blank_nvm_mode)
169 ret_code = i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
175 (total_delay < hw->aq.asq_cmd_timeout)) {
177 ret_code = i40e_aq_release_resource(hw,
185 * @hw: pointer to the HW structure
189 static enum i40e_status_code i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
198 srctl = rd32(hw, I40E_GLNVM_SRCTL);
206 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
212 * @hw: pointer to the HW structure
218 enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
222 if (hw->mac.type == I40E_MAC_X722)
223 return i40e_read_nvm_word_aq(hw, offset, data);
225 return i40e_read_nvm_word_srctl(hw, offset, data);
230 * @hw: pointer to the HW structure
236 enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
244 if (offset >= hw->nvm.sr_size) {
245 i40e_debug(hw, I40E_DEBUG_NVM,
247 offset, hw->nvm.sr_size);
253 ret_code = i40e_poll_sr_srctl_done_bit(hw);
258 wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
261 ret_code = i40e_poll_sr_srctl_done_bit(hw);
263 sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
270 i40e_debug(hw, I40E_DEBUG_NVM,
280 * @hw: pointer to the HW structure
286 enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
293 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, TRUE);
301 * @hw: pointer to the HW structure
310 enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
314 if (hw->mac.type == I40E_MAC_X722)
315 return i40e_read_nvm_buffer_aq(hw, offset, words, data);
317 return i40e_read_nvm_buffer_srctl(hw, offset, words, data);
322 * @hw: pointer to the HW structure
331 enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
342 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);
355 * @hw: pointer to the HW structure
364 enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
392 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,
414 * @hw: pointer to the HW structure.
423 enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
433 cmd_details.wb_desc = &hw->nvm_wb_desc;
440 if ((offset + words) > hw->nvm.sr_size)
441 i40e_debug(hw, I40E_DEBUG_NVM,
443 (offset + words), hw->nvm.sr_size);
446 i40e_debug(hw, I40E_DEBUG_NVM,
452 i40e_debug(hw, I40E_DEBUG_NVM,
456 ret_code = i40e_aq_read_nvm(hw, module_pointer,
466 * @hw: pointer to the HW structure.
475 enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
485 cmd_details.wb_desc = &hw->nvm_wb_desc;
492 if ((offset + words) > hw->nvm.sr_size)
502 ret_code = i40e_aq_update_nvm(hw, module_pointer,
512 * @hw: pointer to the HW structure
521 enum i40e_status_code i40e_write_nvm_word(struct i40e_hw *hw, u32 offset,
529 return i40e_write_nvm_aq(hw, 0x00, offset, 1, data, FALSE);
534 * @hw: pointer to the HW structure
545 enum i40e_status_code i40e_write_nvm_buffer(struct i40e_hw *hw,
561 return i40e_write_nvm_aq(hw, module_pointer, offset, words,
567 * @hw: pointer to hardware structure
575 enum i40e_status_code i40e_calc_nvm_checksum(struct i40e_hw *hw, u16 *checksum)
587 ret_code = i40e_allocate_virt_mem(hw, &vmem,
594 ret_code = i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
601 ret_code = i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
611 for (i = 0; i < hw->nvm.sr_size; i++) {
616 ret_code = i40e_read_nvm_buffer(hw, i, &words, data);
645 i40e_free_virt_mem(hw, &vmem);
651 * @hw: pointer to hardware structure
657 enum i40e_status_code i40e_update_nvm_checksum(struct i40e_hw *hw)
665 ret_code = i40e_calc_nvm_checksum(hw, &checksum);
668 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
676 * @hw: pointer to hardware structure
682 enum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw,
691 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
698 i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);