Lines Matching defs:hw
53 * @hw: pointer to the hardware structure
57 static void i40e_adminq_init_regs(struct i40e_hw *hw)
60 if (i40e_is_vf(hw)) {
61 hw->aq.asq.tail = I40E_VF_ATQT1;
62 hw->aq.asq.head = I40E_VF_ATQH1;
63 hw->aq.asq.len = I40E_VF_ATQLEN1;
64 hw->aq.asq.bal = I40E_VF_ATQBAL1;
65 hw->aq.asq.bah = I40E_VF_ATQBAH1;
66 hw->aq.arq.tail = I40E_VF_ARQT1;
67 hw->aq.arq.head = I40E_VF_ARQH1;
68 hw->aq.arq.len = I40E_VF_ARQLEN1;
69 hw->aq.arq.bal = I40E_VF_ARQBAL1;
70 hw->aq.arq.bah = I40E_VF_ARQBAH1;
72 hw->aq.asq.tail = I40E_PF_ATQT;
73 hw->aq.asq.head = I40E_PF_ATQH;
74 hw->aq.asq.len = I40E_PF_ATQLEN;
75 hw->aq.asq.bal = I40E_PF_ATQBAL;
76 hw->aq.asq.bah = I40E_PF_ATQBAH;
77 hw->aq.arq.tail = I40E_PF_ARQT;
78 hw->aq.arq.head = I40E_PF_ARQH;
79 hw->aq.arq.len = I40E_PF_ARQLEN;
80 hw->aq.arq.bal = I40E_PF_ARQBAL;
81 hw->aq.arq.bah = I40E_PF_ARQBAH;
87 * @hw: pointer to the hardware structure
89 enum i40e_status_code i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
93 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
95 (hw->aq.num_asq_entries *
101 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
102 (hw->aq.num_asq_entries *
105 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
114 * @hw: pointer to the hardware structure
116 enum i40e_status_code i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
120 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
122 (hw->aq.num_arq_entries *
131 * @hw: pointer to the hardware structure
136 void i40e_free_adminq_asq(struct i40e_hw *hw)
138 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
143 * @hw: pointer to the hardware structure
148 void i40e_free_adminq_arq(struct i40e_hw *hw)
150 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
155 * @hw: pointer to the hardware structure
157 static enum i40e_status_code i40e_alloc_arq_bufs(struct i40e_hw *hw)
169 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
170 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
173 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
176 for (i = 0; i < hw->aq.num_arq_entries; i++) {
177 bi = &hw->aq.arq.r.arq_bi[i];
178 ret_code = i40e_allocate_dma_mem(hw, bi,
180 hw->aq.arq_buf_size,
186 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
189 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
214 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
215 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
222 * @hw: pointer to the hardware structure
224 static enum i40e_status_code i40e_alloc_asq_bufs(struct i40e_hw *hw)
231 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
232 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
235 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
238 for (i = 0; i < hw->aq.num_asq_entries; i++) {
239 bi = &hw->aq.asq.r.asq_bi[i];
240 ret_code = i40e_allocate_dma_mem(hw, bi,
242 hw->aq.asq_buf_size,
254 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
255 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
262 * @hw: pointer to the hardware structure
264 static void i40e_free_arq_bufs(struct i40e_hw *hw)
269 for (i = 0; i < hw->aq.num_arq_entries; i++)
270 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
273 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
276 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
281 * @hw: pointer to the hardware structure
283 static void i40e_free_asq_bufs(struct i40e_hw *hw)
288 for (i = 0; i < hw->aq.num_asq_entries; i++)
289 if (hw->aq.asq.r.asq_bi[i].pa)
290 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
293 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
296 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
299 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
304 * @hw: pointer to the hardware structure
308 static enum i40e_status_code i40e_config_asq_regs(struct i40e_hw *hw)
314 wr32(hw, hw->aq.asq.head, 0);
315 wr32(hw, hw->aq.asq.tail, 0);
318 if (!i40e_is_vf(hw))
319 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
321 if (i40e_is_vf(hw))
322 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
324 wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa));
325 wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa));
328 reg = rd32(hw, hw->aq.asq.bal);
329 if (reg != I40E_LO_DWORD(hw->aq.asq.desc_buf.pa))
337 * @hw: pointer to the hardware structure
341 static enum i40e_status_code i40e_config_arq_regs(struct i40e_hw *hw)
347 wr32(hw, hw->aq.arq.head, 0);
348 wr32(hw, hw->aq.arq.tail, 0);
351 if (!i40e_is_vf(hw))
352 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
354 if (i40e_is_vf(hw))
355 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
357 wr32(hw, hw->aq.arq.bal, I40E_LO_DWORD(hw->aq.arq.desc_buf.pa));
358 wr32(hw, hw->aq.arq.bah, I40E_HI_DWORD(hw->aq.arq.desc_buf.pa));
361 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
364 reg = rd32(hw, hw->aq.arq.bal);
365 if (reg != I40E_LO_DWORD(hw->aq.arq.desc_buf.pa))
373 * @hw: pointer to the hardware structure
377 * in the hw->aq structure:
378 * - hw->aq.num_asq_entries
379 * - hw->aq.arq_buf_size
384 enum i40e_status_code i40e_init_asq(struct i40e_hw *hw)
388 if (hw->aq.asq.count > 0) {
395 if ((hw->aq.num_asq_entries == 0) ||
396 (hw->aq.asq_buf_size == 0)) {
401 hw->aq.asq.next_to_use = 0;
402 hw->aq.asq.next_to_clean = 0;
403 hw->aq.asq.count = hw->aq.num_asq_entries;
406 ret_code = i40e_alloc_adminq_asq_ring(hw);
411 ret_code = i40e_alloc_asq_bufs(hw);
416 ret_code = i40e_config_asq_regs(hw);
424 i40e_free_adminq_asq(hw);
432 * @hw: pointer to the hardware structure
436 * in the hw->aq structure:
437 * - hw->aq.num_asq_entries
438 * - hw->aq.arq_buf_size
443 enum i40e_status_code i40e_init_arq(struct i40e_hw *hw)
447 if (hw->aq.arq.count > 0) {
454 if ((hw->aq.num_arq_entries == 0) ||
455 (hw->aq.arq_buf_size == 0)) {
460 hw->aq.arq.next_to_use = 0;
461 hw->aq.arq.next_to_clean = 0;
462 hw->aq.arq.count = hw->aq.num_arq_entries;
465 ret_code = i40e_alloc_adminq_arq_ring(hw);
470 ret_code = i40e_alloc_arq_bufs(hw);
475 ret_code = i40e_config_arq_regs(hw);
483 i40e_free_adminq_arq(hw);
491 * @hw: pointer to the hardware structure
495 enum i40e_status_code i40e_shutdown_asq(struct i40e_hw *hw)
499 if (hw->aq.asq.count == 0)
503 wr32(hw, hw->aq.asq.head, 0);
504 wr32(hw, hw->aq.asq.tail, 0);
505 wr32(hw, hw->aq.asq.len, 0);
506 wr32(hw, hw->aq.asq.bal, 0);
507 wr32(hw, hw->aq.asq.bah, 0);
510 i40e_acquire_spinlock(&hw->aq.asq_spinlock);
512 hw->aq.asq.count = 0; /* to indicate uninitialized queue */
515 i40e_free_asq_bufs(hw);
517 i40e_release_spinlock(&hw->aq.asq_spinlock);
524 * @hw: pointer to the hardware structure
528 enum i40e_status_code i40e_shutdown_arq(struct i40e_hw *hw)
532 if (hw->aq.arq.count == 0)
536 wr32(hw, hw->aq.arq.head, 0);
537 wr32(hw, hw->aq.arq.tail, 0);
538 wr32(hw, hw->aq.arq.len, 0);
539 wr32(hw, hw->aq.arq.bal, 0);
540 wr32(hw, hw->aq.arq.bah, 0);
543 i40e_acquire_spinlock(&hw->aq.arq_spinlock);
545 hw->aq.arq.count = 0; /* to indicate uninitialized queue */
548 i40e_free_arq_bufs(hw);
550 i40e_release_spinlock(&hw->aq.arq_spinlock);
557 * @hw: pointer to the hardware structure
560 * in the hw->aq structure:
561 * - hw->aq.num_asq_entries
562 * - hw->aq.num_arq_entries
563 * - hw->aq.arq_buf_size
564 * - hw->aq.asq_buf_size
566 enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw)
573 if ((hw->aq.num_arq_entries == 0) ||
574 (hw->aq.num_asq_entries == 0) ||
575 (hw->aq.arq_buf_size == 0) ||
576 (hw->aq.asq_buf_size == 0)) {
582 i40e_init_spinlock(&hw->aq.asq_spinlock);
583 i40e_init_spinlock(&hw->aq.arq_spinlock);
586 i40e_adminq_init_regs(hw);
589 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
592 ret_code = i40e_init_asq(hw);
597 ret_code = i40e_init_arq(hw);
602 if (i40e_is_vf(hw))
609 ret_code = i40e_aq_get_firmware_version(hw,
610 &hw->aq.fw_maj_ver,
611 &hw->aq.fw_min_ver,
612 &hw->aq.fw_build,
613 &hw->aq.api_maj_ver,
614 &hw->aq.api_min_ver,
620 i40e_resume_aq(hw);
626 i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION,
627 &hw->nvm.version);
628 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo);
629 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi);
630 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
631 i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr);
632 i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF),
634 i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)),
636 hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;
638 if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) {
644 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
645 hw->aq.nvm_release_on_done = FALSE;
646 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
648 ret_code = i40e_aq_set_hmc_resource_profile(hw,
658 i40e_shutdown_arq(hw);
660 i40e_shutdown_asq(hw);
662 i40e_destroy_spinlock(&hw->aq.asq_spinlock);
663 i40e_destroy_spinlock(&hw->aq.arq_spinlock);
671 * @hw: pointer to the hardware structure
673 enum i40e_status_code i40e_shutdown_adminq(struct i40e_hw *hw)
677 if (i40e_check_asq_alive(hw))
678 i40e_aq_queue_shutdown(hw, TRUE);
680 i40e_shutdown_asq(hw);
681 i40e_shutdown_arq(hw);
684 i40e_destroy_spinlock(&hw->aq.asq_spinlock);
685 i40e_destroy_spinlock(&hw->aq.arq_spinlock);
687 if (hw->nvm_buff.va)
688 i40e_free_virt_mem(hw, &hw->nvm_buff);
695 * @hw: pointer to the hardware structure
699 u16 i40e_clean_asq(struct i40e_hw *hw)
701 struct i40e_adminq_ring *asq = &(hw->aq.asq);
710 while (rd32(hw, hw->aq.asq.head) != ntc) {
711 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
712 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
719 cb_func(hw, &desc_cb);
737 * @hw: pointer to the hw struct
742 bool i40e_asq_done(struct i40e_hw *hw)
747 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
753 * @hw: pointer to the hw struct
762 enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
776 hw->aq.asq_last_status = I40E_AQ_RC_OK;
778 val = rd32(hw, hw->aq.asq.head);
779 if (val >= hw->aq.num_asq_entries) {
780 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
786 if (hw->aq.asq.count == 0) {
787 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
793 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
820 i40e_acquire_spinlock(&hw->aq.asq_spinlock);
822 if (buff_size > hw->aq.asq_buf_size) {
823 i40e_debug(hw,
832 i40e_debug(hw,
846 if (i40e_clean_asq(hw) == 0) {
847 i40e_debug(hw,
855 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
863 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
879 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
880 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
882 (hw->aq.asq.next_to_use)++;
883 if (hw->aq.asq.next_to_use == hw->aq.asq.count)
884 hw->aq.asq.next_to_use = 0;
886 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
898 if (i40e_asq_done(hw))
903 } while (total_delay < hw->aq.asq_cmd_timeout);
907 if (i40e_asq_done(hw)) {
915 i40e_debug(hw,
928 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
931 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
933 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
943 i40e_debug(hw,
950 i40e_release_spinlock(&hw->aq.asq_spinlock);
974 * @hw: pointer to the hw struct
982 enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,
987 u16 ntc = hw->aq.arq.next_to_clean;
996 i40e_acquire_spinlock(&hw->aq.arq_spinlock);
999 if (!i40e_is_vf(hw))
1000 ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);
1001 if (i40e_is_vf(hw))
1002 ntu = (rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK);
1010 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
1016 hw->aq.arq_last_status =
1018 i40e_debug(hw,
1021 hw->aq.arq_last_status);
1030 hw->aq.arq.r.arq_bi[desc_idx].va,
1033 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
1034 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
1035 hw->aq.arq_buf_size);
1041 bi = &hw->aq.arq.r.arq_bi[ntc];
1045 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
1052 wr32(hw, hw->aq.arq.tail, ntc);
1055 if (ntc == hw->aq.num_arq_entries)
1057 hw->aq.arq.next_to_clean = ntc;
1058 hw->aq.arq.next_to_use = ntu;
1063 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
1064 i40e_release_spinlock(&hw->aq.arq_spinlock);
1067 if (hw->aq.nvm_release_on_done) {
1068 i40e_release_nvm(hw);
1069 hw->aq.nvm_release_on_done = FALSE;
1072 switch (hw->nvmupd_state) {
1074 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1078 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
1089 void i40e_resume_aq(struct i40e_hw *hw)
1092 hw->aq.asq.next_to_use = 0;
1093 hw->aq.asq.next_to_clean = 0;
1095 i40e_config_asq_regs(hw);
1097 hw->aq.arq.next_to_use = 0;
1098 hw->aq.arq.next_to_clean = 0;
1100 i40e_config_arq_regs(hw);