Lines Matching defs:rcrp
1396 p_rx_rcr_ring_t rcrp, rdc_stat_t cs, int bytes_to_read)
1420 channel = rcrp->rdc;
1431 channel, rcrp->rcr_desc_rd_head_p,
1432 rcrp->rcr_desc_rd_head_pp, rcrp->comp_rd_index));
1448 comp_rd_index = rcrp->comp_rd_index;
1450 rcr_desc_rd_head_p = rcrp->rcr_desc_rd_head_p;
1451 rcr_desc_rd_head_pp = rcrp->rcr_desc_rd_head_pp;
1464 rcr_head_index = rcrp->rcr_desc_rd_head_p - rcrp->rcr_desc_first_p;
1465 rcr_tail_index = rcr_tail - rcrp->rcr_tail_begin;
1471 num_rcrs = (rcrp->comp_size - rcr_head_index) + rcr_tail_index;
1474 npkts = hxge_scan_for_last_eop(rcrp, rcr_desc_rd_head_p, num_rcrs);
1494 rcrp, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont,
1497 rdc_stats = rcrp->rdc_stats;
1546 rcrp->comp_wrap_mask);
1549 rcrp->rcr_desc_first_p, rcrp->rcr_desc_last_p);
1568 rcrp->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp;
1569 rcrp->comp_rd_index = comp_rd_index;
1570 rcrp->rcr_desc_rd_head_p = rcr_desc_rd_head_p;
1572 if ((hxgep->intr_timeout != rcrp->intr_timeout) ||
1573 (hxgep->intr_threshold != rcrp->intr_threshold)) {
1574 rcrp->intr_timeout = hxgep->intr_timeout;
1575 rcrp->intr_threshold = hxgep->intr_threshold;
1577 if (rcrp->intr_timeout)
1579 rcr_cfg_b.bits.timeout = rcrp->intr_timeout;
1580 rcr_cfg_b.bits.pthres = rcrp->intr_threshold;
1597 channel, rcrp->rcr_desc_rd_head_pp, rcrp->comp_rd_index));
1607 static uint32_t hxge_scan_for_last_eop(p_rx_rcr_ring_t rcrp,
1624 rcrp->rcr_desc_first_p, rcrp->rcr_desc_last_p);
2086 p_rx_rcr_ring_t rcrp;
2089 rcrp = hxgep->rx_rcr_rings->rcr_rings[channel];
2090 rbrp = rcrp->rx_rbr_p;
2230 p_rx_rcr_ring_t rcrp;
2233 rcrp = hxgep->rx_rcr_rings->rcr_rings[channel];
2234 rbrp = rcrp->rx_rbr_p;
2565 p_rx_rcr_ring_t rcrp;
2730 rcrp = (p_rx_rcr_ring_t)KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP);
2731 MUTEX_INIT(&rcrp->lock, NULL, MUTEX_DRIVER,
2733 rcrp->rdc = dma_channel;
2734 rcrp->hxgep = hxgep;
2737 rcrp->comp_size = hxge_port_rcr_size;
2738 rcrp->comp_wrap_mask = hxge_port_rcr_size - 1;
2742 dmap = (p_hxge_dma_common_t)&rcrp->rcr_desc;
2743 hxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size,
2745 rcrp->comp_rd_index = 0;
2746 rcrp->comp_wt_index = 0;
2747 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p =
2748 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc);
2750 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp =
2751 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc);
2753 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp =
2754 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc);
2756 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p +
2758 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp +
2761 rcrp->rcr_tail_begin = DMA_COMMON_IOADDR(rcrp->rcr_desc);
2762 rcrp->rcr_tail_begin = (rcrp->rcr_tail_begin & 0x7ffffULL) >> 3;
2769 dma_channel, rbr_vaddrp, rcrp->rcr_desc_rd_head_p,
2770 rcrp->rcr_desc_rd_head_pp, rcrp->rcr_desc_last_p,
2771 rcrp->rcr_desc_last_pp));
2777 rcrp->intr_timeout = hxgep->intr_timeout;
2778 rcrp->intr_threshold = hxgep->intr_threshold;
2779 rcrp->full_hdr_flag = B_FALSE;
2780 rcrp->sw_priv_hdr_len = 0;
2782 cfga_p = &(rcrp->rcr_cfga);
2783 cfgb_p = &(rcrp->rcr_cfgb);
2786 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress;
2788 cfga_p->value = (rcrp->rcr_addr &
2791 cfga_p->value |= ((uint64_t)rcrp->comp_size << RCRCFIG_A_LEN_SHIF);
2798 cfgb_p->bits.pthres = rcrp->intr_threshold;
2799 cfgb_p->bits.timeout = rcrp->intr_timeout;
2832 cfig2_p->bits.full_hdr = rcrp->full_hdr_flag;
2833 cfig2_p->bits.offset = rcrp->sw_priv_hdr_len;
2835 rbrp->rx_rcr_p = rcrp;
2836 rcrp->rx_rbr_p = rbrp;
2837 *rcr_p = rcrp;
3581 p_rx_rcr_ring_t rcrp;
3603 rcrp = (p_rx_rcr_ring_t)hxgep->rx_rcr_rings->rcr_rings[channel];
3605 MUTEX_ENTER(&rcrp->lock);
3640 rcrp->comp_rd_index = 0;
3641 rcrp->comp_wt_index = 0;
3642 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p =
3643 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc);
3645 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp =
3646 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc);
3648 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp =
3649 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc);
3652 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p +
3654 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp +
3657 rcrp->rcr_tail_begin = DMA_COMMON_IOADDR(rcrp->rcr_desc);
3658 rcrp->rcr_tail_begin = (rcrp->rcr_tail_begin & 0x7ffffULL) >> 3;
3660 dmap = (p_hxge_dma_common_t)&rcrp->rcr_desc;
3682 (void) hxge_rxdma_start_channel(hxgep, channel, rbrp, rcrp, mboxp,
3706 MUTEX_EXIT(&rcrp->lock);
3713 MUTEX_EXIT(&rcrp->lock);
3728 p_rx_rcr_ring_t rcrp;
3762 rcrp = hxgep->rx_rcr_rings->rcr_rings[channel];
3763 rbrp = rcrp->rx_rbr_p;