Lines Matching defs:hxgep
60 static hxge_status_t hxge_map_rxdma(p_hxge_t hxgep);
61 static void hxge_unmap_rxdma(p_hxge_t hxgep);
62 static hxge_status_t hxge_rxdma_hw_start_common(p_hxge_t hxgep);
63 static hxge_status_t hxge_rxdma_hw_start(p_hxge_t hxgep);
64 static void hxge_rxdma_hw_stop(p_hxge_t hxgep);
65 static hxge_status_t hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel,
70 static void hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel,
72 static hxge_status_t hxge_map_rxdma_channel_cfg_ring(p_hxge_t hxgep,
76 static void hxge_unmap_rxdma_channel_cfg_ring(p_hxge_t hxgep,
78 static hxge_status_t hxge_map_rxdma_channel_buf_ring(p_hxge_t hxgep,
81 static void hxge_unmap_rxdma_channel_buf_ring(p_hxge_t hxgep,
83 static hxge_status_t hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel,
86 static hxge_status_t hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel);
87 static mblk_t *hxge_rx_pkts(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp,
91 static void hxge_receive_packet(p_hxge_t hxgep, p_rx_rcr_ring_t rcr_p,
94 static hxge_status_t hxge_disable_rxdma_channel(p_hxge_t hxgep,
98 static hxge_status_t hxge_rx_err_evnts(p_hxge_t hxgep, uint_t index,
100 static hxge_status_t hxge_rxbuf_index_info_init(p_hxge_t hxgep,
102 static hxge_status_t hxge_rxdma_fatal_err_recover(p_hxge_t hxgep,
104 static hxge_status_t hxge_rx_port_fatal_err_recover(p_hxge_t hxgep);
105 static void hxge_rbr_empty_restore(p_hxge_t hxgep,
109 hxge_init_rxdma_channels(p_hxge_t hxgep)
115 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_init_rxdma_channels"));
118 hxgep->rdc_first_intr[i] = B_TRUE;
123 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value);
126 status = hxge_map_rxdma(hxgep);
128 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
133 status = hxge_rxdma_hw_start_common(hxgep);
135 hxge_unmap_rxdma(hxgep);
138 status = hxge_rxdma_hw_start(hxgep);
140 hxge_unmap_rxdma(hxgep);
143 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
149 hxge_uninit_rxdma_channels(p_hxge_t hxgep)
151 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_uninit_rxdma_channels"));
153 hxge_rxdma_hw_stop(hxgep);
154 hxge_unmap_rxdma(hxgep);
156 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_uinit_rxdma_channels"));
160 hxge_init_rxdma_channel_cntl_stat(p_hxge_t hxgep, uint16_t channel,
167 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
170 handle = HXGE_DEV_HPI_HANDLE(hxgep);
181 hxge_enable_rxdma_channel(p_hxge_t hxgep, uint16_t channel,
190 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel"));
191 handle = HXGE_DEV_HPI_HANDLE(hxgep);
199 HXGE_DEBUG_MSG((hxgep, RX_CTL,
206 switch (hxgep->rx_bksize_code) {
235 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel: "
238 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel: "
277 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_enable_rxdma_channel"));
283 hxge_disable_rxdma_channel(p_hxge_t hxgep, uint16_t channel)
288 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_disable_rxdma_channel"));
290 handle = HXGE_DEV_HPI_HANDLE(hxgep);
295 HXGE_DEBUG_MSG((hxgep, RX_CTL,
299 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_disable_rxdma_channel"));
304 hxge_rxdma_channel_rcrflush(p_hxge_t hxgep, uint8_t channel)
309 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
312 handle = HXGE_DEV_HPI_HANDLE(hxgep);
315 HXGE_DEBUG_MSG((hxgep, DMA_CTL,
332 hxge_rxbuf_pp_to_vp(p_hxge_t hxgep, p_rx_rbr_ring_t rbr_p,
348 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_rxbuf_pp_to_vp"));
350 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
383 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
391 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
430 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
458 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
497 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
504 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
512 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
522 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
532 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
539 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> getting total index"));
544 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
559 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
571 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
575 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "<== hxge_rxbuf_pp_to_vp"));
647 hxge_rxbuf_index_info_init(p_hxge_t hxgep, p_rx_rbr_ring_t rbrp)
653 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_rxbuf_index_info_init"));
665 HXGE_DEBUG_MSG((hxgep, DMA2_CTL,
673 HXGE_DEBUG_MSG((hxgep, DMA2_CTL,
686 HXGE_DEBUG_MSG((hxgep, DMA2_CTL,
689 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_rxbuf_index_info_init"));
696 hxge_dump_rcr_entry(p_hxge_t hxgep, p_rcr_entry_t entry_p)
705 HXGE_DEBUG_MSG((hxgep, RX_CTL,
734 HXGE_DEBUG_MSG((hxgep, RX_CTL, "rcr pp 0x%llx l2 len %d",
741 hxge_rxdma_stop(p_hxge_t hxgep)
743 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop"));
745 MUTEX_ENTER(&hxgep->vmac_lock);
746 (void) hxge_rx_vmac_disable(hxgep);
747 (void) hxge_rxdma_hw_mode(hxgep, HXGE_DMA_STOP);
748 MUTEX_EXIT(&hxgep->vmac_lock);
750 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop"));
754 hxge_rxdma_stop_reinit(p_hxge_t hxgep)
756 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_reinit"));
758 (void) hxge_rxdma_stop(hxgep);
759 (void) hxge_uninit_rxdma_channels(hxgep);
760 (void) hxge_init_rxdma_channels(hxgep);
762 MUTEX_ENTER(&hxgep->vmac_lock);
763 (void) hxge_rx_vmac_enable(hxgep);
764 MUTEX_EXIT(&hxgep->vmac_lock);
766 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop_reinit"));
770 hxge_rxdma_hw_mode(p_hxge_t hxgep, boolean_t enable)
780 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
783 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) {
784 HXGE_DEBUG_MSG((hxgep, RX_CTL,
789 rx_rbr_rings = hxgep->rx_rbr_rings;
791 HXGE_DEBUG_MSG((hxgep, RX_CTL,
797 HXGE_DEBUG_MSG((hxgep, RX_CTL,
804 HXGE_DEBUG_MSG((hxgep, RX_CTL,
809 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
814 handle = HXGE_DEV_HPI_HANDLE(hxgep);
822 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
827 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
835 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
959 void hxge_post_page(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p,
963 hxge_post_page(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p)
965 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_post_page"));
990 hpi_rxdma_rdc_rbr_kick(HXGE_DEV_HPI_HANDLE(hxgep), rx_rbr_p->rdc, 1);
993 hxge_rbr_empty_restore(hxgep, rx_rbr_p);
996 HXGE_DEBUG_MSG((hxgep, RX_CTL,
999 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_post_page"));
1077 hxge_post_page(rx_msg_p->hxgep, ring, rx_msg_p);
1091 p_hxge_t hxgep = (p_hxge_t)arg2;
1102 "<== hxge_rx_intr: arg2 $%p arg1 $%p", hxgep, ldvp));
1106 if (arg2 == NULL || (void *) ldvp->hxgep != arg2) {
1107 hxgep = ldvp->hxgep;
1110 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL,
1111 "==> hxge_rx_intr: arg2 $%p arg1 $%p", hxgep, ldvp));
1116 handle = HXGE_DEV_HPI_HANDLE(hxgep);
1122 ring = hxgep->rx_rcr_rings->rcr_rings[channel];
1123 rhp = &hxgep->rx_ring_handles[channel];
1148 (hxgep->hxge_mac_state == HXGE_MAC_STARTED)) {
1149 mp = hxge_rx_pkts(hxgep, ldvp->vdma_index,
1156 (void) hxge_rx_err_evnts(hxgep, channel, ldvp, cs);
1166 rbrp = hxgep->rx_rbr_rings->rbr_rings[channel];
1202 mac_rx_ring(hxgep->mach, ring->rcr_mac_handle, mp,
1219 p_hxge_t hxgep;
1228 hxgep = ring_handle->hxgep;
1229 ringp = hxgep->rx_rcr_rings->rcr_rings[ring_handle->index];
1264 p_hxge_t hxgep;
1271 hxgep = ring_handle->hxgep;
1272 ringp = hxgep->rx_rcr_rings->rcr_rings[ring_handle->index];
1287 handle = HXGE_DEV_HPI_HANDLE(hxgep);
1339 p_hxge_t hxgep;
1345 hxgep = rhp->hxgep;
1350 handle = HXGE_DEV_HPI_HANDLE(hxgep);
1351 ring = hxgep->rx_rcr_rings->rcr_rings[rhp->index];
1373 mblk = hxge_rx_pkts(hxgep, ring->ldvp->vdma_index,
1385 (void) hxge_rx_err_evnts(hxgep, ldvp->vdma_index, ldvp, cs);
1395 hxge_rx_pkts(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp,
1416 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:vindex %d "
1419 handle = HXGE_DEV_HPI_HANDLE(hxgep);
1422 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:index %d "
1428 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL,
1439 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL,
1445 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_pkts:rcr channel %d "
1454 if (hxgep->rdc_first_intr[channel])
1479 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL,
1487 hxge_dump_rcr_entry(hxgep, rcr_desc_rd_head_p);
1493 hxge_receive_packet(hxgep,
1499 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL,
1528 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL,
1553 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL,
1556 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL,
1572 if ((hxgep->intr_timeout != rcrp->intr_timeout) ||
1573 (hxgep->intr_threshold != rcrp->intr_threshold)) {
1574 rcrp->intr_timeout = hxgep->intr_timeout;
1575 rcrp->intr_threshold = hxgep->intr_threshold;
1586 if (hxgep->rdc_first_intr[channel] && (npkt_read > 0)) {
1587 hxgep->rdc_first_intr[channel] = B_FALSE;
1594 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL,
1599 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "<== hxge_rx_pkts"));
1634 hxge_receive_packet(p_hxge_t hxgep, p_rx_rcr_ring_t rcr_p,
1671 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_receive_packet"));
1679 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "hxge_receive_packet "
1708 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1715 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1721 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1730 HXGE_DEBUG_MSG((hxgep, RX_CTL,
1743 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1755 HXGE_DEBUG_MSG((hxgep, RX_CTL,
1763 HXGE_DEBUG_MSG((hxgep, RX_CTL,
1773 status = hxge_rxbuf_pp_to_vp(hxgep, rx_rbr_p,
1777 HXGE_DEBUG_MSG((hxgep, RX_CTL,
1784 HXGE_DEBUG_MSG((hxgep, RX_CTL,
1789 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1793 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1800 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1809 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1817 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1822 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1827 HXGE_DEBUG_MSG((hxgep, RX_CTL,
1832 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1845 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1865 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1872 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1894 HXGE_DEBUG_MSG((hxgep, RX_CTL,
1903 HXGE_FM_REPORT_ERROR(hxgep, NULL, HXGE_FM_EREPORT_RDMC_RCR_ERR);
1907 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
1912 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
1933 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
1987 HXGE_DEBUG_MSG((hxgep, RX_CTL,
2065 HXGE_DEBUG_MSG((hxgep, RX_CTL,
2072 HXGE_DEBUG_MSG((hxgep, RX2_CTL,
2077 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_receive_packet: "
2083 hxge_rx_rbr_empty_recover(p_hxge_t hxgep, uint8_t channel)
2089 rcrp = hxgep->rx_rcr_rings->rcr_rings[channel];
2091 handle = HXGE_DEV_HPI_HANDLE(hxgep);
2105 hxge_rbr_empty_restore(hxgep, rbrp);
2115 hxge_rx_err_evnts(p_hxge_t hxgep, uint_t index, p_hxge_ldv_t ldvp,
2124 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_rx_err_evnts"));
2126 handle = HXGE_DEV_HPI_HANDLE(hxgep);
2129 rdc_stats = &hxgep->statsp->rdc_stats[ldvp->vdma_index];
2133 HXGE_FM_REPORT_ERROR(hxgep, channel,
2136 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2148 HXGE_FM_REPORT_ERROR(hxgep, channel,
2151 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2158 HXGE_FM_REPORT_ERROR(hxgep, channel,
2161 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2168 HXGE_FM_REPORT_ERROR(hxgep, channel,
2171 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2178 HXGE_FM_REPORT_ERROR(hxgep, channel,
2181 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2196 HXGE_FM_REPORT_ERROR(hxgep, channel,
2199 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2206 HXGE_FM_REPORT_ERROR(hxgep, channel,
2209 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2216 hxge_rx_rbr_empty_recover(hxgep, channel);
2221 HXGE_FM_REPORT_ERROR(hxgep, channel,
2224 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2233 rcrp = hxgep->rx_rcr_rings->rcr_rings[channel];
2236 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2242 status = hxge_rxdma_fatal_err_recover(hxgep, channel);
2245 FM_SERVICE_RESTORED(hxgep);
2249 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_rx_err_evnts"));
2254 hxge_map_rxdma(p_hxge_t hxgep)
2275 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_map_rxdma"));
2277 dma_buf_poolp = hxgep->rx_buf_pool_p;
2278 dma_rbr_cntl_poolp = hxgep->rx_rbr_cntl_pool_p;
2279 dma_rcr_cntl_poolp = hxgep->rx_rcr_cntl_pool_p;
2280 dma_mbox_cntl_poolp = hxgep->rx_mbox_cntl_pool_p;
2286 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2293 HXGE_DEBUG_MSG((hxgep, RX_CTL,
2325 hxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT;
2326 hxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT;
2341 status = hxge_map_rxdma_channel(hxgep, channel,
2355 rcr_rings[i]->rdc_stats = &hxgep->statsp->rdc_stats[i];
2360 hxgep->rx_rbr_rings = rx_rbr_rings;
2362 hxgep->rx_rcr_rings = rx_rcr_rings;
2365 hxgep->rx_mbox_areas_p = rx_mbox_areas_p;
2370 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2376 hxge_unmap_rxdma_channel(hxgep, channel,
2388 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2395 hxge_unmap_rxdma(p_hxge_t hxgep)
2411 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_unmap_rxdma"));
2413 dma_buf_poolp = hxgep->rx_buf_pool_p;
2414 dma_rbr_cntl_poolp = hxgep->rx_rbr_cntl_pool_p;
2415 dma_rcr_cntl_poolp = hxgep->rx_rcr_cntl_pool_p;
2416 dma_mbox_cntl_poolp = hxgep->rx_mbox_cntl_pool_p;
2422 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2427 rx_rbr_rings = hxgep->rx_rbr_rings;
2428 rx_rcr_rings = hxgep->rx_rcr_rings;
2430 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2437 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2442 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2447 rx_mbox_areas_p = hxgep->rx_mbox_areas_p;
2453 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2456 (void) hxge_unmap_rxdma_channel(hxgep, channel,
2469 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_unmap_rxdma"));
2473 hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel,
2484 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2490 status = hxge_map_rxdma_channel_buf_ring(hxgep, channel,
2493 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2502 status = hxge_map_rxdma_channel_cfg_ring(hxgep, channel,
2506 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2515 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2518 hxge_unmap_rxdma_channel_cfg_ring(hxgep, *rcr_p, *rx_mbox_p);
2522 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2524 "(hxgep 0x%x status 0x%x channel %d)",
2525 hxgep, status, channel));
2526 hxge_unmap_rxdma_channel_buf_ring(hxgep, *rbr_p);
2531 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2532 "<== hxge_map_rxdma_channel: (hxgep 0x%x status 0x%x channel %d)",
2533 hxgep, status, channel));
2540 hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel,
2543 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2549 (void) hxge_unmap_rxdma_channel_cfg_ring(hxgep, rcr_p, rx_mbox_p);
2552 (void) hxge_unmap_rxdma_channel_buf_ring(hxgep, rbr_p);
2554 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_unmap_rxdma_channel"));
2559 hxge_map_rxdma_channel_cfg_ring(p_hxge_t hxgep, uint16_t dma_channel,
2585 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2620 rcfgb_p->bits.bksize = hxgep->rx_bksize_code;
2627 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2634 rx_msg_p->hxgep = hxgep;
2722 HXGE_DEBUG_MSG((hxgep, RX_CTL,
2732 (void *) hxgep->interrupt_cookie);
2734 rcrp->hxgep = hxgep;
2736 hxge_port_rcr_size = hxgep->hxge_port_rcr_size;
2764 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2777 rcrp->intr_timeout = hxgep->intr_timeout;
2778 rcrp->intr_threshold = hxgep->intr_threshold;
2812 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2827 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2840 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2847 hxge_unmap_rxdma_channel_cfg_ring(p_hxge_t hxgep,
2850 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2857 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2862 hxge_map_rxdma_channel_buf_ring(p_hxge_t hxgep, uint16_t channel,
2877 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2881 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2887 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2894 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
2908 (void *) hxgep->interrupt_cookie);
2910 (void *) hxgep->interrupt_cookie);
2942 rbrp->block_size = hxgep->rx_default_block_size;
2944 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2950 rbrp->block_size, hxgep->rx_default_block_size,
2977 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
2989 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3001 * HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3016 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3024 status = hxge_rxbuf_index_info_init(hxgep, rbrp);
3025 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, " hxge_map_rxdma_channel_buf_ring: "
3038 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3061 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3069 hxge_unmap_rxdma_channel_buf_ring(p_hxge_t hxgep,
3078 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3081 HXGE_DEBUG_MSG((hxgep, RX_CTL,
3085 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3092 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3099 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3106 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3137 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3143 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3148 hxge_rxdma_hw_start_common(p_hxge_t hxgep)
3152 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start_common"));
3159 (void) hxge_init_fzc_rx_common(hxgep);
3161 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start_common"));
3167 hxge_rxdma_hw_start(p_hxge_t hxgep)
3179 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start"));
3181 rx_rbr_rings = hxgep->rx_rbr_rings;
3182 rx_rcr_rings = hxgep->rx_rcr_rings;
3184 HXGE_DEBUG_MSG((hxgep, RX_CTL,
3191 HXGE_DEBUG_MSG((hxgep, RX_CTL,
3195 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3202 HXGE_REG_WR64(hxgep->hpi_handle, RDC_PREF_CMD, i);
3209 HXGE_REG_WR64(hxgep->hpi_handle, RDC_SHADOW_CMD, i);
3216 HXGE_REG_WR64(hxgep->hpi_handle, RDC_CTRL_FIFO_CMD, i);
3223 HXGE_REG_WR64(hxgep->hpi_handle, RDC_DATA_FIFO_CMD, i);
3229 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_STAT, 0xFF);
3232 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0);
3236 rx_mbox_areas_p = hxgep->rx_mbox_areas_p;
3243 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3246 status = hxge_rxdma_start_channel(hxgep, channel,
3255 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start: "
3261 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3266 (void) hxge_rxdma_stop_channel(hxgep, channel);
3270 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3276 hxge_rxdma_hw_stop(p_hxge_t hxgep)
3284 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_stop"));
3286 rx_rbr_rings = hxgep->rx_rbr_rings;
3287 rx_rcr_rings = hxgep->rx_rcr_rings;
3290 HXGE_DEBUG_MSG((hxgep, RX_CTL,
3297 HXGE_DEBUG_MSG((hxgep, RX_CTL,
3302 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3308 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3311 (void) hxge_rxdma_stop_channel(hxgep, channel);
3314 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_stop: "
3318 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_rxdma_hw_stop"));
3322 hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel,
3332 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel"));
3334 handle = HXGE_DEV_HPI_HANDLE(hxgep);
3336 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "hxge_rxdma_start_channel: "
3338 hxgep->hpi_handle.regp, hxgep->hpi_handle.regh));
3343 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3349 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3357 status = hxge_init_fzc_rxdma_channel(hxgep,
3360 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3366 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3372 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3379 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3385 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: "
3393 status = hxge_enable_rxdma_channel(hxgep,
3396 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3403 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: "
3415 status = hxge_init_rxdma_channel_cntl_stat(hxgep, channel, &cs);
3416 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: "
3419 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3426 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: "
3428 HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
3430 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_rxdma_start_channel"));
3435 hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel)
3443 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_channel"));
3445 handle = HXGE_DEV_HPI_HANDLE(hxgep);
3447 HXGE_DEBUG_MSG((hxgep, RX_CTL, "hxge_rxdma_stop_channel: "
3449 hxgep->hpi_handle.regp, hxgep->hpi_handle.regh));
3454 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3460 HXGE_DEBUG_MSG((hxgep, RX_CTL,
3467 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3473 HXGE_DEBUG_MSG((hxgep, RX_CTL,
3478 status = hxge_init_rxdma_channel_cntl_stat(hxgep, channel, &cs);
3480 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_channel: control "
3484 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3491 HXGE_DEBUG_MSG((hxgep, RX_CTL,
3495 status = hxge_disable_rxdma_channel(hxgep, channel);
3498 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3505 HXGE_DEBUG_MSG((hxgep, RX_CTL,
3507 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop_channel"));
3513 hxge_rxdma_handle_sys_errors(p_hxge_t hxgep)
3520 handle = hxgep->hpi_handle;
3521 statsp = (p_hxge_rdc_sys_stats_t)&hxgep->statsp->rdc_sys_stats;
3530 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3538 HXGE_FM_REPORT_ERROR(hxgep, NULL,
3540 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3548 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3556 HXGE_FM_REPORT_ERROR(hxgep, NULL,
3558 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3564 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3566 status = hxge_rx_port_fatal_err_recover(hxgep);
3568 FM_SERVICE_RESTORED(hxgep);
3576 hxge_rxdma_fatal_err_recover(p_hxge_t hxgep, uint16_t channel)
3591 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_fatal_err_recover"));
3598 handle = HXGE_DEV_HPI_HANDLE(hxgep);
3600 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Rx DMA stop..."));
3602 rbrp = (p_rx_rbr_ring_t)hxgep->rx_rbr_rings->rbr_rings[channel];
3603 rcrp = (p_rx_rcr_ring_t)hxgep->rx_rcr_rings->rcr_rings[channel];
3608 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxDMA channel..."));
3612 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3616 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxDMA interrupt..."));
3622 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3625 HXGE_DEBUG_MSG((hxgep, RX_CTL, "RxDMA channel reset..."));
3630 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3634 hxge_port_rcr_size = hxgep->hxge_port_rcr_size;
3635 mboxp = (p_rx_mbox_t)hxgep->rx_mbox_areas_p->rxmbox_areas[channel];
3663 HXGE_DEBUG_MSG((hxgep, RX_CTL, "rbr entries = %d\n",
3674 HXGE_DEBUG_MSG((hxgep, RX_CTL, "RxDMA channel re-start..."));
3682 (void) hxge_rxdma_start_channel(hxgep, channel, rbrp, rcrp, mboxp,
3692 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3701 RXDMA_REG_READ64(HXGE_DEV_HPI_HANDLE(hxgep),
3708 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_fatal_err_recover"));
3714 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3720 hxge_rx_port_fatal_err_recover(p_hxge_t hxgep)
3731 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_port_fatal_err_recover"));
3732 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovering from RDC error ..."));
3735 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxMAC...\n"));
3736 MUTEX_ENTER(&hxgep->vmac_lock);
3737 if (hxge_rx_vmac_disable(hxgep) != HXGE_OK)
3747 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value);
3752 if (hxge_rxdma_hw_start_common(hxgep) != HXGE_OK)
3755 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Stop all RxDMA channels..."));
3757 ndmas = hxgep->rx_buf_pool_p->ndmas;
3758 dma_buf_p = hxgep->rx_buf_pool_p->dma_buf_pool_p;
3762 rcrp = hxgep->rx_rcr_rings->rcr_rings[channel];
3770 if (hxge_rxdma_fatal_err_recover(hxgep, channel) != HXGE_OK) {
3771 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3777 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Reset RxMAC..."));
3780 if (hxge_rx_vmac_reset(hxgep) != HXGE_OK) {
3781 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3786 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Re-initialize RxMAC..."));
3789 if ((status = hxge_rx_vmac_init(hxgep)) != HXGE_OK) {
3790 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3794 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Re-enable RxMAC..."));
3797 if ((status = hxge_rx_vmac_enable(hxgep)) != HXGE_OK) {
3798 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3802 MUTEX_EXIT(&hxgep->vmac_lock);
3805 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0);
3807 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3809 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rx_port_fatal_err_recover"));
3813 MUTEX_EXIT(&hxgep->vmac_lock);
3814 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3815 "Error Recovery failed for hxge(%d)", hxgep->instance));
3820 hxge_rbr_empty_restore(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p)
3827 rdc_stats = &hxgep->statsp->rdc_stats[rx_rbr_p->rdc];
3843 MUTEX_ENTER(&hxgep->vmac_lock);
3844 (void) hxge_rx_vmac_disable(hxgep);
3851 RXDMA_REG_WRITE64(HXGE_DEV_HPI_HANDLE(hxgep), RDC_STAT,
3855 HXGE_DEV_HPI_HANDLE(hxgep), rx_rbr_p->rdc);
3860 status = hxge_rxdma_fatal_err_recover(hxgep, rx_rbr_p->rdc);
3862 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
3864 hxgep->instance, rx_rbr_p->rdc));
3871 (void) hxge_rx_vmac_enable(hxgep);
3872 MUTEX_EXIT(&hxgep->vmac_lock);