Cross Reference: /illumos-gate/usr/src/uts/common/io/e1000g/e1000g

Lines Matching defs:hw
42  * @hw: pointer to the HW structure
48 e1000_ttl_workaround_enabled_82541(struct e1000_hw *hw)
50 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
55 	if ((hw->mac.type != e1000_82541) && (hw->mac.type != e1000_82547))
66  * @hw: pointer to the HW structure
75 e1000_fifo_workaround_82547(struct e1000_hw *hw, u16 length)
77 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
84 	if (hw->mac.type != e1000_82547)
101 	if (E1000_READ_REG(hw, E1000_TDT(0)) !=
102 	    E1000_READ_REG(hw, E1000_TDH(0))) {
107 	if (E1000_READ_REG(hw, E1000_TDFT) != E1000_READ_REG(hw, E1000_TDFH)) {
112 	if (E1000_READ_REG(hw, E1000_TDFTS) !=
113 	    E1000_READ_REG(hw, E1000_TDFHS)) {
119 	tctl = E1000_READ_REG(hw, E1000_TCTL);
120 	E1000_WRITE_REG(hw, E1000_TCTL, tctl & ~E1000_TCTL_EN);
123 	E1000_WRITE_REG(hw, E1000_TDFT, dev_spec->tx_fifo_start);
124 	E1000_WRITE_REG(hw, E1000_TDFH, dev_spec->tx_fifo_start);
125 	E1000_WRITE_REG(hw, E1000_TDFTS, dev_spec->tx_fifo_start);
126 	E1000_WRITE_REG(hw, E1000_TDFHS, dev_spec->tx_fifo_start);
129 	E1000_WRITE_REG(hw, E1000_TCTL, tctl);
130 	E1000_WRITE_FLUSH(hw);
140  * @hw: pointer to the HW structure
146 e1000_update_tx_fifo_head_82547(struct e1000_hw *hw, u32 length)
148 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
152 	if (hw->mac.type != e1000_82547)
164  * @hw: pointer to the HW structure
171 e1000_set_ttl_workaround_state_82541(struct e1000_hw *hw, bool state)
173 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
177 	if ((hw->mac.type != e1000_82541) && (hw->mac.type != e1000_82547))
185  * @hw: pointer to the HW structure
197 e1000_igp_ttl_workaround_82547(struct e1000_hw *hw)
199 	struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
208 	if ((hw->mac.type != e1000_82541) && (hw->mac.type != e1000_82547))
211 	if (!(e1000_ttl_workaround_enabled_82541(hw)))
215 	ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
237 			ret_val = hw->phy.ops.read_reg(hw,
269 	    hw->phy.ops.write_reg(hw, IGP01E1000_PHY_DSP_RESET, dsp_value);