Lines Matching defs:dev_spec
50 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
58 state = dev_spec->ttl_workaround;
77 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
97 if ((dev_spec->tx_fifo_head + fifo_pkt_len) <
98 (dev_spec->tx_fifo_size + E1000_FIFO_PAD_82547))
123 E1000_WRITE_REG(hw, E1000_TDFT, dev_spec->tx_fifo_start);
124 E1000_WRITE_REG(hw, E1000_TDFH, dev_spec->tx_fifo_start);
125 E1000_WRITE_REG(hw, E1000_TDFTS, dev_spec->tx_fifo_start);
126 E1000_WRITE_REG(hw, E1000_TDFHS, dev_spec->tx_fifo_start);
132 dev_spec->tx_fifo_head = 0;
148 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
155 dev_spec->tx_fifo_head += E1000_ROUNDUP(length + E1000_FIFO_HDR_SIZE,
158 if (dev_spec->tx_fifo_head > dev_spec->tx_fifo_size)
159 dev_spec->tx_fifo_head -= dev_spec->tx_fifo_size;
173 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
180 dev_spec->ttl_workaround = state;
199 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
224 if (dev_spec->dsp_reset_counter) {
225 dev_spec->dsp_reset_counter = 0;
232 if (dev_spec->dsp_reset_counter == 0) {
247 dev_spec->dsp_reset_counter++;
255 if (dev_spec->dsp_reset_counter > E1000_MAX_DSP_RESETS) {
256 dev_spec->dsp_reset_counter = 0;
259 if (dev_spec->dsp_reset_counter) {
260 dsp_value = (dev_spec->dsp_reset_counter & 1)
263 dev_spec->dsp_reset_counter++;