Lines Matching refs:descriptor
190 /* retrieve and compute information for context descriptor */
248 * to be within one descriptor. Here we reallocate and refill the
404 * (one redundant descriptor and one hw checksum context descriptor are
563 * The following code determine if the context descriptor is
568 * workaround for 82546EB, context descriptor must be reloaded
616 struct e1000_tx_desc *descriptor;
628 descriptor = NULL;
636 /* Context descriptor reload check */
642 descriptor = next_desc;
645 (struct e1000_context_desc *)descriptor);
648 if (descriptor == tx_ring->tbd_last)
660 * "ignored except on the first data descriptor of a packet." However,
662 * given data descriptor is used to interpret that data descriptor --
663 * regardless of whether or not the descriptor is the first in a packet
669 * POPTS field on every data descriptor to be the intended options for
691 descriptor = next_desc;
692 descriptor->buffer_addr =
694 descriptor->lower.data =
698 descriptor->upper.data = zeroed.upper.data;
700 descriptor->lower.data |=
702 /* must set RS on every outgoing descriptor */
703 descriptor->lower.data |=
707 descriptor->lower.data |= E1000_TXD_CMD_TSE;
710 if (descriptor == tx_ring->tbd_last)
724 descriptor == first_data_desc &&
725 ((descriptor->lower.data & E1000G_TBD_LENGTH_MASK)
727 /* modified the first descriptor */
728 descriptor->lower.data &=
730 descriptor->lower.flags.length =
733 /* insert a new descriptor */
747 /* must set RS on every outgoing descriptor */
755 descriptor = next_desc;
775 * Count the checksum context descriptor for
793 ((descriptor->lower.data & E1000G_TBD_LENGTH_MASK) > 8)) {
794 /* modified the previous descriptor */
795 descriptor->lower.data -= 4;
797 /* insert a new descriptor */
801 descriptor->buffer_addr +
802 (descriptor->lower.data & E1000G_TBD_LENGTH_MASK);
812 descriptor = next_desc;
815 if (descriptor == tx_ring->tbd_last)
825 ASSERT(descriptor);
841 descriptor->lower.data |= E1000_TXD_CMD_IDE |
844 descriptor->lower.data |= E1000_TXD_CMD_EOP;
851 descriptor->lower.data |= E1000_TXD_CMD_IFCS;
932 /* Setup TX descriptor pointers */
952 /* Setup HW Base and Length of Tx descriptor area */
968 /* Setup our HW Tx Head & Tail descriptor pointers */
1026 struct e1000_tx_desc *descriptor;
1048 /* Sync the Tx descriptor DMA buffer */
1066 * Get hold of the next descriptor that the e1000g will
1067 * report status back to (this will be the last descriptor
1074 descriptor = tx_ring->tbd_oldest + (packet->num_desc - 1);
1077 if (descriptor > tx_ring->tbd_last)
1078 descriptor -= Adapter->tx_desc_num;
1081 * If the descriptor done bit is set free TxSwPacket and
1084 if (descriptor->upper.fields.status & E1000_TXD_STAT_DD) {
1088 if (descriptor == tx_ring->tbd_last)
1093 descriptor + 1;
1228 desc_array->descriptor[0].address = address;
1229 desc_array->descriptor[0].length = (uint32_t)length;
1243 desc_array->descriptor[0].address = address;
1244 desc_array->descriptor[0].length = (uint32_t)length;
1249 desc_array->descriptor[0].address = address;
1250 desc_array->descriptor[0].length = length - 4;
1251 desc_array->descriptor[1].address = address + (length - 4);
1252 desc_array->descriptor[1].length = 4;
1423 * Each cookie will have one descriptor
1587 desc_array.descriptor[counter].address;
1589 desc_array.descriptor[counter].length;