Lines Matching defs:hw
30 e1000_pci_set_mwi(struct e1000_hw *hw)
32 uint16_t val = hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE;
34 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val);
38 e1000_pci_clear_mwi(struct e1000_hw *hw)
40 uint16_t val = hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE;
42 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val);
46 e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
48 pci_config_put16(OS_DEP(hw)->cfg_handle, reg, *value);
52 e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
55 pci_config_get16(OS_DEP(hw)->cfg_handle, reg);
65 phy_spd_state(struct e1000_hw *hw, boolean_t enable)
71 switch (hw->mac.type) {
91 (void) e1000_read_phy_reg(hw, offset, ®);
98 (void) e1000_write_phy_reg(hw, offset, reg);
109 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
111 *value = pci_config_get16(OS_DEP(hw)->cfg_handle,
123 e1000_write_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
130 status = pci_lcap_locate(OS_DEP(hw)->cfg_handle, pcie_id, &pcie_cap);
134 pci_config_put16(OS_DEP(hw)->cfg_handle,
145 e1000_rar_clear(struct e1000_hw *hw, uint32_t index)
153 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
154 E1000_WRITE_FLUSH(hw);
163 e1000_destroy_hw_mutex(struct e1000_hw *hw)
167 switch (hw->mac.type) {
172 dev_spec = &hw->dev_spec.ich8lan;