Lines Matching refs:ret_val
167 s32 ret_val = E1000_SUCCESS;
228 ret_val = e1000_get_phy_id_82575(hw);
257 ret_val = phy->ops.write_reg(hw,
260 if (ret_val)
263 ret_val = phy->ops.read_reg(hw,
266 if (ret_val)
277 ret_val = e1000_initialize_M88E1512_phy(hw);
278 if (ret_val)
282 ret_val = e1000_initialize_M88E1543_phy(hw);
283 if (ret_val)
318 ret_val = -E1000_ERR_PHY;
323 return ret_val;
600 s32 ret_val = -E1000_ERR_PARAM;
609 ret_val = hw->phy.ops.acquire(hw);
610 if (ret_val)
613 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
618 return ret_val;
633 s32 ret_val = -E1000_ERR_PARAM;
642 ret_val = hw->phy.ops.acquire(hw);
643 if (ret_val)
646 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
651 return ret_val;
664 s32 ret_val = E1000_SUCCESS;
684 ret_val = e1000_get_phy_id(hw);
706 ret_val = -E1000_ERR_PHY;
710 ret_val = e1000_get_phy_id(hw);
726 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
727 if (ret_val == E1000_SUCCESS) {
745 ret_val = -E1000_ERR_PHY;
747 ret_val = e1000_get_phy_id(hw);
754 return ret_val;
765 s32 ret_val = E1000_SUCCESS;
784 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
785 if (ret_val)
788 ret_val = hw->phy.ops.commit(hw);
789 if (ret_val)
793 ret_val = e1000_initialize_M88E1512_phy(hw);
795 return ret_val;
814 s32 ret_val = E1000_SUCCESS;
822 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
823 if (ret_val)
828 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
830 if (ret_val)
834 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
837 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
839 if (ret_val)
843 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
852 ret_val = phy->ops.read_reg(hw,
855 if (ret_val)
859 ret_val = phy->ops.write_reg(hw,
862 if (ret_val)
865 ret_val = phy->ops.read_reg(hw,
868 if (ret_val)
872 ret_val = phy->ops.write_reg(hw,
875 if (ret_val)
881 return ret_val;
988 s32 ret_val = E1000_SUCCESS;
992 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
993 if (ret_val)
1021 ret_val = e1000_acquire_nvm_generic(hw);
1022 if (ret_val)
1026 return ret_val;
1058 s32 ret_val = E1000_SUCCESS;
1065 ret_val = -E1000_ERR_SWFW_SYNC;
1084 ret_val = -E1000_ERR_SWFW_SYNC;
1094 return ret_val;
1174 s32 ret_val;
1179 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1182 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1185 return ret_val;
1197 s32 ret_val;
1203 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1218 ret_val = e1000_config_fc_after_link_up_generic(hw);
1219 if (ret_val)
1222 ret_val = e1000_check_for_copper_link_generic(hw);
1225 return ret_val;
1237 s32 ret_val;
1244 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1245 if (ret_val)
1246 return ret_val;
1248 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1249 if (ret_val)
1250 return ret_val;
1256 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1257 if (ret_val)
1258 return ret_val;
1260 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1261 if (ret_val)
1262 return ret_val;
1275 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1276 if (ret_val)
1277 return ret_val;
1282 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1283 if (ret_val)
1284 return ret_val;
1430 s32 ret_val;
1438 ret_val = e1000_disable_pcie_master_generic(hw);
1439 if (ret_val)
1443 ret_val = e1000_set_pcie_completion_timeout(hw);
1444 if (ret_val)
1461 ret_val = e1000_get_auto_rd_done_generic(hw);
1462 if (ret_val) {
1480 ret_val = e1000_check_alt_mac_addr_generic(hw);
1482 return ret_val;
1494 s32 ret_val;
1500 ret_val = mac->ops.id_led_init(hw);
1501 if (ret_val) {
1524 ret_val = mac->ops.setup_link(hw);
1537 return ret_val;
1551 s32 ret_val;
1575 ret_val = e1000_setup_serdes_link_82575(hw);
1576 if (ret_val)
1583 ret_val = hw->phy.ops.reset(hw);
1584 if (ret_val) {
1599 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1602 ret_val = e1000_copper_link_setup_m88(hw);
1607 ret_val = e1000_copper_link_setup_igp(hw);
1610 ret_val = e1000_copper_link_setup_82577(hw);
1613 ret_val = -E1000_ERR_PHY;
1617 if (ret_val)
1620 ret_val = e1000_setup_copper_link_generic(hw);
1622 return ret_val;
1638 s32 ret_val = E1000_SUCCESS;
1645 return ret_val;
1686 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1687 if (ret_val) {
1689 return ret_val;
1763 return ret_val;
1780 s32 ret_val = E1000_SUCCESS;
1811 ret_val = e1000_set_sfp_media_type_82575(hw);
1812 if ((ret_val != E1000_SUCCESS) ||
1845 return ret_val;
1857 s32 ret_val = E1000_ERR_CONFIG;
1873 ret_val = e1000_read_sfp_data_byte(hw,
1876 if (ret_val == E1000_SUCCESS)
1881 if (ret_val != E1000_SUCCESS)
1884 ret_val = e1000_read_sfp_data_byte(hw,
1887 if (ret_val != E1000_SUCCESS)
1910 ret_val = E1000_SUCCESS;
1914 return ret_val;
1927 s32 ret_val;
1931 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1932 if (ret_val) {
1949 return ret_val;
2010 s32 ret_val;
2019 ret_val = e1000_check_alt_mac_addr_generic(hw);
2020 if (ret_val)
2023 ret_val = e1000_read_mac_addr_generic(hw);
2026 return ret_val;
2229 s32 ret_val = E1000_SUCCESS;
2250 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2252 if (ret_val)
2257 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2264 return ret_val;
2373 s32 ret_val;
2377 ret_val = hw->phy.ops.acquire(hw);
2378 if (ret_val)
2381 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2386 return ret_val;
2399 s32 ret_val;
2403 ret_val = hw->phy.ops.acquire(hw);
2404 if (ret_val)
2407 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2412 return ret_val;
2425 s32 ret_val = E1000_SUCCESS;
2436 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2439 if (ret_val) {
2451 return ret_val;
2463 s32 ret_val = E1000_SUCCESS;
2484 ret_val = e1000_disable_pcie_master_generic(hw);
2485 if (ret_val)
2520 ret_val = e1000_get_auto_rd_done_generic(hw);
2521 if (ret_val) {
2537 ret_val = e1000_reset_mdicnfg_82580(hw);
2538 if (ret_val)
2542 ret_val = e1000_check_alt_mac_addr_generic(hw);
2548 return ret_val;
2563 u16 ret_val = 0;
2566 ret_val = e1000_82580_rxpbs_table[data];
2568 return ret_val;
2582 s32 ret_val = E1000_SUCCESS;
2589 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2590 if (ret_val) {
2599 ret_val = -E1000_ERR_NVM;
2604 return ret_val;
2619 s32 ret_val;
2626 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2627 if (ret_val) {
2634 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2636 if (ret_val)
2640 return ret_val;
2653 s32 ret_val;
2660 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2661 if (ret_val) {
2674 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2676 if (ret_val != E1000_SUCCESS)
2681 return ret_val;
2694 s32 ret_val;
2700 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2701 if (ret_val) {
2709 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2711 if (ret_val) {
2719 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2720 if (ret_val)
2725 return ret_val;
2738 s32 ret_val = E1000_SUCCESS;
2746 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2748 if (ret_val != E1000_SUCCESS)
2753 return ret_val;
2766 s32 ret_val = E1000_SUCCESS;
2774 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2775 if (ret_val != E1000_SUCCESS)
2780 return ret_val;
2793 s32 ret_val;
2797 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2798 if (ret_val)
2799 return ret_val;
2802 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2804 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2806 return ret_val;
2831 s32 ret_val = E1000_SUCCESS;
2840 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2841 if (ret_val)
2844 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2845 if (ret_val)
2848 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2849 if (ret_val)
2852 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2853 if (ret_val)
2856 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2857 if (ret_val)
2860 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2861 if (ret_val)
2864 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2865 if (ret_val)
2868 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2869 if (ret_val)
2872 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2873 if (ret_val)
2877 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2878 if (ret_val)
2881 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2882 if (ret_val)
2886 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2887 if (ret_val)
2891 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2892 if (ret_val)
2896 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2897 if (ret_val)
2900 ret_val = phy->ops.commit(hw);
2901 if (ret_val) {
2903 return ret_val;
2908 return ret_val;
2920 s32 ret_val = E1000_SUCCESS;
2929 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2930 if (ret_val)
2933 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2934 if (ret_val)
2937 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2938 if (ret_val)
2941 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2942 if (ret_val)
2945 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2946 if (ret_val)
2949 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2950 if (ret_val)
2953 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2954 if (ret_val)
2957 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2958 if (ret_val)
2961 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2962 if (ret_val)
2966 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2967 if (ret_val)
2970 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2971 if (ret_val)
2975 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2976 if (ret_val)
2980 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2981 if (ret_val)
2985 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2986 if (ret_val)
2990 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2991 if (ret_val)
2995 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2996 if (ret_val)
2999 ret_val = phy->ops.commit(hw);
3000 if (ret_val) {
3002 return ret_val;
3007 return ret_val;
3077 s32 ret_val = E1000_SUCCESS;
3089 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
3090 if (ret_val)
3093 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3095 if (ret_val)
3099 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3101 if (ret_val)
3105 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
3106 if (ret_val)
3110 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3113 if (ret_val)
3126 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3131 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3134 if (ret_val)
3139 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3145 return ret_val;
3159 s32 ret_val = E1000_SUCCESS;
3170 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3173 if (ret_val)
3180 return ret_val;
3241 s32 ret_val = E1000_SUCCESS;
3258 return ret_val;