Lines Matching defs:mc5
26 #pragma ident "%Z%%M% %I% %E% SMI" /* mc5.c */
30 #include "mc5.h"
135 unsigned int t1_mc5_get_tcam_size(struct pemc5 *mc5)
137 return mc5->tcam_size;
140 static int set_tcam_rtbl_base(struct pemc5 *mc5, unsigned int rtbl_base)
142 if (rtbl_base >= t1_mc5_get_tcam_size(mc5)) return -1;
143 t1_write_reg_4(mc5->adapter, A_MC5_ROUTING_TABLE_INDEX, rtbl_base);
147 unsigned int t1_mc5_get_tcam_rtbl_base(struct pemc5 *mc5)
149 return t1_read_reg_4(mc5->adapter, A_MC5_ROUTING_TABLE_INDEX);
152 unsigned int t1_mc5_get_tcam_rtbl_size(struct pemc5 *mc5)
154 unsigned int tcam_size = t1_mc5_get_tcam_size(mc5);
155 unsigned int tcam_rtable_base = t1_mc5_get_tcam_rtbl_base(mc5);
160 static int set_tcam_server_base(struct pemc5 *mc5, unsigned int server_base)
162 if (server_base >= t1_mc5_get_tcam_size(mc5)) return -1;
163 t1_write_reg_4(mc5->adapter, A_MC5_SERVER_INDEX, server_base);
167 unsigned int t1_mc5_get_tcam_server_base(struct pemc5 *mc5)
169 return t1_read_reg_4(mc5->adapter, A_MC5_SERVER_INDEX);
172 unsigned int t1_mc5_get_tcam_server_size(struct pemc5 *mc5)
174 unsigned int tcam_rtable_base = t1_mc5_get_tcam_rtbl_base(mc5);
175 unsigned int tcam_server_base = t1_mc5_get_tcam_server_base(mc5);
216 static int init_mask_data_array(struct pemc5 *mc5, u32 mask_array_base,
220 adapter_t *adap = mc5->adapter;
226 unsigned int size72 = tcam_part_size[mc5->part_size] / 72;
227 unsigned int server_base = t1_mc5_get_tcam_server_base(mc5);
228 if (mc5->mode == MC5_MODE_144_BIT)
242 mc5->mode == MC5_MODE_144_BIT ?
250 static int init_lara7000(struct pemc5 *mc5)
253 adapter_t *adap = mc5->adapter;
258 if (mc5->parity_enabled) {
267 dbgi_wr_data3(adap, mc5->mode == MC5_MODE_144_BIT ?
273 dbgi_wr_data3(adap, mc5->mode == MC5_MODE_144_BIT ?
282 dbgi_wr_data3(adap, mc5->mode == MC5_MODE_72_BIT ?
295 if (i <= 1 && mc5->mode == MC5_MODE_72_BIT)
308 return init_mask_data_array(mc5, MC5_LRA_MSKARY_BASE_ADR0,
315 static int init_idt52100(struct pemc5 *mc5)
318 adapter_t *adap = mc5->adapter;
373 return init_mask_data_array(mc5, MC5_IDT_MSKARY_BASE_ADR0,
381 static inline void mc5_dbgi_mode_enable(struct pemc5 *mc5)
383 t1_write_reg_4(mc5->adapter, A_MC5_CONFIG,
384 V_MODE(mc5->mode == MC5_MODE_72_BIT) |
389 static void mc5_dbgi_mode_disable(struct pemc5 *mc5)
391 t1_write_reg_4(mc5->adapter, A_MC5_CONFIG,
392 V_MODE(mc5->mode == MC5_MODE_72_BIT) |
393 V_COMPRESSION_ENABLE(mc5->mode == MC5_MODE_72_BIT) |
394 V_PARITY_ENABLE(mc5->parity_enabled) |
395 V_SYN_ISSUE_MODE(mc5->issue_syn) | F_M_BUS_ENABLE |
403 int t1_mc5_init(struct pemc5 *mc5, unsigned int nservers,
408 unsigned int tcam_size = t1_mc5_get_tcam_size(mc5);
409 adapter_t *adap = mc5->adapter;
413 cfg |= V_MODE(mc5->mode == MC5_MODE_72_BIT) | F_TCAM_RESET;
420 if (set_tcam_rtbl_base(mc5, tcam_size - nroutes) ||
421 set_tcam_server_base(mc5, tcam_size - nroutes - nservers))
425 if (mc5->mode == MC5_MODE_72_BIT)
426 t1_mc5_lip_write_entries(mc5);
428 mc5->issue_syn = (unsigned char)syn;
429 mc5->parity_enabled = (unsigned char)parity;
435 mc5_dbgi_mode_enable(mc5);
437 switch (mc5->part_type) {
439 err = init_lara7000(mc5);
442 err = init_idt52100(mc5);
450 mc5_dbgi_mode_disable(mc5);
456 * @mc5: the MC5 handle
463 int t1_read_mc5_range(struct pemc5 *mc5, unsigned int start,
468 adapter_t *adap = mc5->adapter;
470 if (mc5->part_type == LARA_7000)
472 else if (mc5->part_type == IDT75P52100)
477 mc5_dbgi_mode_enable(mc5);
489 mc5_dbgi_mode_disable(mc5);
501 void t1_mc5_intr_enable(struct pemc5 *mc5)
505 if (!mc5->parity_enabled)
509 if (!t1_is_asic(mc5->adapter)) {
516 t1_write_reg_4(mc5->adapter, A_MC5_INT_ENABLE, mask);
520 u32 pl_intr = t1_read_reg_4(mc5->adapter, A_PL_ENABLE);
522 t1_write_reg_4(mc5->adapter, A_PL_ENABLE,
524 t1_write_reg_4(mc5->adapter, A_MC5_INT_ENABLE,
530 void t1_mc5_intr_disable(struct pemc5 *mc5)
533 if (!t1_is_asic(mc5->adapter))
534 t1_write_reg_4(mc5->adapter, A_MC5_INT_ENABLE, 0);
538 u32 pl_intr = t1_read_reg_4(mc5->adapter, A_PL_ENABLE);
540 t1_write_reg_4(mc5->adapter, A_PL_ENABLE,
542 t1_write_reg_4(mc5->adapter, A_MC5_INT_ENABLE, 0);
546 void t1_mc5_intr_clear(struct pemc5 *mc5)
549 if (!t1_is_asic(mc5->adapter)) {
550 t1_write_reg_4(mc5->adapter, A_MC5_INT_CAUSE, 0xffffffff);
554 t1_write_reg_4(mc5->adapter, A_PL_CAUSE, F_PL_INTR_MC5);
555 t1_write_reg_4(mc5->adapter, A_MC5_INT_CAUSE, 0xffffffff);
562 void t1_mc5_intr_handler(struct pemc5 *mc5)
564 adapter_t *adap = mc5->adapter;
568 mc5->intr_counts.hit_out_active_region_err++;
571 mc5->intr_counts.hit_in_active_region_err++;
574 mc5->intr_counts.hit_in_routing_region_err++;
577 mc5->intr_counts.miss_err++;
580 mc5->intr_counts.lip_equal_zero_err++;
583 mc5->intr_counts.lip_miss_err++;
585 if ((cause & F_MC5_INT_PARITY_ERR) && mc5->parity_enabled) {
587 mc5->intr_counts.parity_err++;
591 mc5->intr_counts.active_region_full_err++;
594 mc5->intr_counts.next_free_addr_srch_err++;
597 mc5->intr_counts.syn_cookie++;
600 mc5->intr_counts.syn_cookie_bad_message++;
603 mc5->intr_counts.syn_cookie_off_message++;
606 mc5->intr_counts.receive_unknown_cmd++;
611 mc5->intr_counts.parity_in_request_q_err++;
617 mc5->intr_counts.parity_in_dispatch_q_err++;
621 mc5->intr_counts.del_and_act_is_empty++;
629 const struct pemc5_intr_counts *t1_mc5_get_intr_counts(struct pemc5 *mc5)
631 return &mc5->intr_counts;
636 struct pemc5 *mc5;
642 mc5 = t1_os_malloc_wait_zero(sizeof(*mc5));
643 if (!mc5) return NULL;
645 mc5->adapter = adapter;
646 mc5->mode = (unsigned char) mode;
649 mc5->part_size = G_TCAM_PART_SIZE(cfg);
650 mc5->part_type = (unsigned char) G_TCAM_PART_TYPE(cfg);
652 mc5->part_type |= 4;
659 mc5->tcam_size = tcam_part_size[mc5->part_size] / bits_per_entry;
661 return mc5;
664 void t1_mc5_destroy(struct pemc5 *mc5)
666 t1_os_free((void *)mc5, sizeof(*mc5));
687 static int mc5_set_lip_entries(struct pemc5 *mc5, u32 *p,
696 u32 cfg = t1_read_reg_4(mc5->adapter, A_MC5_CONFIG);
697 t1_write_reg_4(mc5->adapter, A_MC5_CONFIG,
702 t1_write_reg_4(mc5->adapter, A_MC5_LIP_RAM_DATA, p[i]);
703 t1_write_reg_4(mc5->adapter, A_MC5_LIP_RAM_ADDR, 0x100 + i);
707 t1_write_reg_4(mc5->adapter, A_MC5_CONFIG, cfg | F_COMPRESSION_ENABLE);
715 void t1_mc5_lip_write_entries(struct pemc5 *mc5)
720 if (mc5->lip_index) {
721 qsort(mc5->lip, mc5->lip_index, sizeof(u32), mc5_cmp);
722 filler = mc5->lip[mc5->lip_index - 1];
724 for (i = mc5->lip_index; i < MC5_LIP_NUM_OF_ENTRIES; i++)
725 mc5->lip[i] = filler;
726 mc5_set_lip_entries(mc5, mc5->lip, MC5_LIP_NUM_OF_ENTRIES);
729 void t1_mc5_lip_clear_entries(struct pemc5 *mc5)
731 mc5->lip_index = 0;
737 int t1_mc5_lip_add_entry(struct pemc5 *mc5, u32 lip)
739 if (mc5->lip_index >= MC5_LIP_NUM_OF_ENTRIES) return 1;
740 mc5->lip[mc5->lip_index++] = lip;