Lines Matching defs:adap
220 adapter_t *adap = mc5->adapter;
232 dbgi_wr_data3(adap, 0, 0, 0);
234 if (mc5_write(adap, data_array_base + i, write_cmd))
238 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
241 t1_write_reg_4(adap, A_MC5_DBGI_REQ_DATA0,
244 if (mc5_write(adap, mask_array_base + i, write_cmd))
253 adapter_t *adap = mc5->adapter;
255 t1_write_reg_4(adap, A_MC5_RSP_LATENCY,
256 t1_is_asic(adap) ? 0x0a0a0a0a : 0x09090909);
259 t1_write_reg_4(adap, A_MC5_AOPEN_SRCH_CMD, 0x20022);
260 t1_write_reg_4(adap, A_MC5_SYN_SRCH_CMD, 0x20022);
261 t1_write_reg_4(adap, A_MC5_ACK_SRCH_CMD, 0x20022);
265 t1_write_reg_4(adap, A_MC5_DBGI_CONFIG, DBGI_MODE_LARA_7000);
267 dbgi_wr_data3(adap, mc5->mode == MC5_MODE_144_BIT ?
270 if (mc5_write(adap, MC5_LRA_CMDREG_ADR0, MC5_LRA_CMD_WRITE))
273 dbgi_wr_data3(adap, mc5->mode == MC5_MODE_144_BIT ?
276 if (mc5_write(adap, MC5_LRA_CFGREG_ADR0, MC5_LRA_CMD_WRITE))
282 dbgi_wr_data3(adap, mc5->mode == MC5_MODE_72_BIT ?
286 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
288 if (mc5_write(adap, MC5_LRA_GMRREG_BASE_ADR0_1 + i,
296 dbgi_wr_data3(adap, 0xfffffffd, 0xffffc003, 0xff);
298 dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);
300 dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);
302 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
304 if (mc5_write(adap, MC5_LRA_GMRREG_BASE_ADR0_2 + i,
318 adapter_t *adap = mc5->adapter;
320 t1_write_reg_4(adap, A_MC5_RSP_LATENCY, 0x151515);
321 t1_write_reg_4(adap, A_MC5_PART_ID_INDEX, 2);
327 t1_write_reg_4(adap, A_MC5_POPEN_DATA_WR_CMD, MC5_IDT_CMD_WRITE);
328 t1_write_reg_4(adap, A_MC5_POPEN_MASK_WR_CMD, MC5_IDT_CMD_WRITE);
329 t1_write_reg_4(adap, A_MC5_AOPEN_SRCH_CMD, MC5_IDT_CMD_SEARCH);
330 t1_write_reg_4(adap, A_MC5_AOPEN_LRN_CMD, MC5_IDT_CMD_LEARN);
331 t1_write_reg_4(adap, A_MC5_SYN_SRCH_CMD, MC5_IDT_CMD_SEARCH | 0x6000);
332 t1_write_reg_4(adap, A_MC5_SYN_LRN_CMD, MC5_IDT_CMD_LEARN);
333 t1_write_reg_4(adap, A_MC5_ACK_SRCH_CMD, MC5_IDT_CMD_SEARCH);
334 t1_write_reg_4(adap, A_MC5_ACK_LRN_CMD, MC5_IDT_CMD_LEARN);
335 t1_write_reg_4(adap, A_MC5_ILOOKUP_CMD, MC5_IDT_CMD_SEARCH);
336 t1_write_reg_4(adap, A_MC5_ELOOKUP_CMD, MC5_IDT_CMD_SEARCH | 0x7000);
337 t1_write_reg_4(adap, A_MC5_DATA_WRITE_CMD, MC5_IDT_CMD_WRITE);
338 t1_write_reg_4(adap, A_MC5_DATA_READ_CMD, MC5_IDT_CMD_READ);
341 t1_write_reg_4(adap, A_MC5_DBGI_CONFIG, DBGI_MODE_IDT_52100);
344 dbgi_wr_data3(adap, MC5_IDT_LAR_MODE144, 0, 0);
345 if (mc5_write(adap, MC5_IDT_LAR_ADR0, MC5_IDT_CMD_WRITE))
349 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0);
350 if (mc5_write(adap, MC5_IDT_SSR0_ADR0, MC5_IDT_CMD_WRITE) ||
351 mc5_write(adap, MC5_IDT_SSR1_ADR0, MC5_IDT_CMD_WRITE))
357 dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);
359 dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);
361 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
363 if (mc5_write(adap, MC5_IDT_GMR_BASE_ADR0 + i,
369 dbgi_wr_data3(adap, 1, 0, 0);
370 if (mc5_write(adap, MC5_IDT_SCR_ADR0, MC5_IDT_CMD_WRITE))
409 adapter_t *adap = mc5->adapter;
412 cfg = t1_read_reg_4(adap, A_MC5_CONFIG) & ~F_MODE;
414 t1_write_reg_4(adap, A_MC5_CONFIG, cfg);
415 if (t1_wait_op_done(adap, A_MC5_CONFIG, F_TCAM_READY, 1, 500, 0)) {
416 CH_ERR("%s: TCAM reset timed out\n", adapter_name(adap));
432 t1_write_reg_4(adap, A_MC5_DBGI_REQ_ADDR1, 0);
433 t1_write_reg_4(adap, A_MC5_DBGI_REQ_ADDR2, 0);
445 CH_ERR("%s: unsupported TCAM type\n", adapter_name(adap));
468 adapter_t *adap = mc5->adapter;
480 t1_write_reg_4(adap, A_MC5_DBGI_REQ_ADDR0, start++);
481 if (mc5_cmd_write(adap, read_cmd)) {
485 dbgi_rd_rsp3(adap, buf + 2, buf + 1, buf);
564 adapter_t *adap = mc5->adapter;
565 u32 cause = t1_read_reg_4(adap, A_MC5_INT_CAUSE);
586 CH_ALERT("%s: MC5 parity error\n", adapter_name(adap));
610 adapter_name(adap));
616 adapter_name(adap));
624 t1_fatal_err(adap);
626 t1_write_reg_4(adap, A_MC5_INT_CAUSE, cause);