Lines Matching defs:adapter
35 adapter_t *adapter;
46 #define is_MC4A(adapter) (!t1_is_T1B(adapter))
49 static unsigned int __devinit mc4_calc_size(adapter_t *adapter)
51 u32 mc4_cfg = t1_read_reg_4(adapter, A_MC4_CFG);
52 unsigned int width = is_MC4A(adapter) ? G_MC4A_WIDTH(mc4_cfg) :
64 static int wrreg_wait(adapter_t *adapter, unsigned int addr, u32 val)
68 t1_write_reg_4(adapter, addr, val);
69 val = t1_read_reg_4(adapter, addr); /* flush */
71 if (!(t1_read_reg_4(adapter, addr) & F_BUSY))
77 adapter_name(adapter), addr);
88 adapter_t *adapter = mc4->adapter;
91 val = t1_read_reg_4(adapter, A_MC4_CFG);
92 t1_write_reg_4(adapter, A_MC4_CFG, val | F_POWER_UP);
93 val = t1_read_reg_4(adapter, A_MC4_CFG); /* flush */
95 if (is_MC4A(adapter)) {
102 val = t1_read_reg_4(adapter, A_MC4_STROBE);
103 t1_write_reg_4(adapter, A_MC4_STROBE,
114 if (t1_is_asic(adapter) && !slow_mode) {
115 val = t1_read_reg_4(adapter, A_MC4_STROBE);
116 t1_write_reg_4(adapter, A_MC4_STROBE,
123 val = t1_read_reg_4(adapter, A_MC4_STROBE);
127 adapter_name(adapter));
136 ext_mode = t1_is_asic(adapter) && !slow_mode ? 0 : 1;
137 if (wrreg_wait(adapter, A_MC4_EXT_MODE, ext_mode))
141 if (wrreg_wait(adapter, A_MC4_MODE, 0x32))
145 val = t1_read_reg_4(adapter, A_MC4_REFRESH);
146 if (wrreg_wait(adapter, A_MC4_REFRESH, val & ~F_REFRESH_ENABLE))
150 if (wrreg_wait(adapter, A_MC4_REFRESH, val & ~F_REFRESH_ENABLE))
159 t1_write_reg_4(adapter, A_MC4_REFRESH,
161 (void) t1_read_reg_4(adapter, A_MC4_REFRESH); /* flush */
163 t1_write_reg_4(adapter, A_MC4_ECC_CNTL,
167 t1_write_reg_4(adapter, A_MC4_BIST_ADDR_BEG, 0);
168 t1_write_reg_4(adapter, A_MC4_BIST_ADDR_END, (mc4->size << width) - 1);
169 t1_write_reg_4(adapter, A_MC4_BIST_DATA, 0);
170 t1_write_reg_4(adapter, A_MC4_BIST_OP, V_OP(1) | 0x1f0);
171 (void) t1_read_reg_4(adapter, A_MC4_BIST_OP); /* flush */
176 val = t1_read_reg_4(adapter, A_MC4_BIST_OP);
179 CH_ERR("%s: MC4 BIST timed out\n", adapter_name(adapter));
184 val = t1_read_reg_4(adapter, A_MC4_CFG);
185 t1_write_reg_4(adapter, A_MC4_CFG, val | F_READY);
186 val = t1_read_reg_4(adapter, A_MC4_CFG); /* flush */
193 struct pemc4 * __devinit t1_mc4_create(adapter_t *adapter)
198 mc4->adapter = adapter;
199 mc4->size = mc4_calc_size(adapter);
216 if (t1_is_asic(mc4->adapter)) {
217 t1_write_reg_4(mc4->adapter, A_MC4_INT_ENABLE, MC4_INT_MASK);
219 pl_intr = t1_read_reg_4(mc4->adapter, A_PL_ENABLE);
220 t1_write_reg_4(mc4->adapter, A_PL_ENABLE,
229 if (t1_is_asic(mc4->adapter)) {
230 t1_write_reg_4(mc4->adapter, A_MC4_INT_ENABLE, 0);
232 pl_intr = t1_read_reg_4(mc4->adapter, A_PL_ENABLE);
233 t1_write_reg_4(mc4->adapter, A_PL_ENABLE,
240 if (t1_is_asic(mc4->adapter)) {
241 t1_write_reg_4(mc4->adapter, A_MC4_INT_CAUSE, 0xffffffff);
242 t1_write_reg_4(mc4->adapter, A_PL_CAUSE, F_PL_INTR_MC4);
248 adapter_t *adapter = mc4->adapter;
249 u32 cause = t1_read_reg_4(adapter, A_MC4_INT_CAUSE);
255 adapter_name(adapter),
256 G_MC4_CE_ADDR(t1_read_reg_4(adapter, A_MC4_CE_ADDR)),
257 t1_read_reg_4(adapter, A_MC4_CE_DATA0),
258 t1_read_reg_4(adapter, A_MC4_CE_DATA1),
259 t1_read_reg_4(adapter, A_MC4_CE_DATA2),
260 t1_read_reg_4(adapter, A_MC4_CE_DATA3),
261 t1_read_reg_4(adapter, A_MC4_CE_DATA4));
268 adapter_name(adapter),
269 G_MC4_UE_ADDR(t1_read_reg_4(adapter, A_MC4_UE_ADDR)),
270 t1_read_reg_4(adapter, A_MC4_UE_DATA0),
271 t1_read_reg_4(adapter, A_MC4_UE_DATA1),
272 t1_read_reg_4(adapter, A_MC4_UE_DATA2),
273 t1_read_reg_4(adapter, A_MC4_UE_DATA3),
274 t1_read_reg_4(adapter, A_MC4_UE_DATA4));
279 CH_ALERT("%s: MC4 address error\n", adapter_name(adapter));
283 t1_fatal_err(adapter);
285 t1_write_reg_4(mc4->adapter, A_MC4_INT_CAUSE, cause);
301 adapter_t *adap = mc4->adapter;