Lines Matching refs:control
499 * The PCI express device control register and device status register
562 * All the state machine control registers below have at least a
616 * Other bits in some of the above state machine control registers
700 * and a set of bits that control whether ATTN is asserted on each
717 * End of state machine control register definitions
921 * Receive Rules Registers: 16 pairs of control+mask/value pairs
1348 * This contains various bits relating to power control (which differ
1427 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in
1590 #define MII_DSP_CONTROL 0x16 /* DSP control register */
1690 * Write this value to the AUX control register
1901 uint32_t control;