Lines Matching refs:tw32
104 #define tw32(reg,val) tg3_write_indirect_reg32((reg),(val))
114 tw32(reg, val);
145 tw32(TG3PCI_MISC_HOST_CTRL,
845 tw32(MAC_LED_CTRL, LED_CTRL_PHY_MODE_1);
1030 tw32(MAC_TX_AUTO_NEG, 0);
1054 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1069 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1267 tw32(MAC_TX_AUTO_NEG, 0);
1393 tw32(MAC_TX_LENGTHS,
1398 tw32(MAC_TX_LENGTHS,
1434 tw32(ofs, val);
1499 tw32(FTQ_RESET, 0xffffffff);
1500 tw32(FTQ_RESET, 0x00000000);
1525 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
1541 tw32(GRC_MISC_CFG, val);
1570 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1576 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1579 tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
1591 tw32(GRC_RX_CPU_EVENT, val);
1649 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
1650 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
1657 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
1658 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
1668 tw32(MAC_TX_BACKOFF_SEED, addr_high);
1736 tw32(_table[0], _table[1]); \
1762 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
1773 tw32(GRC_MODE, tp->grc_mode); /* Redundant? */
1796 tw32(TG3PCI_PCISTATE, val);
1819 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
1829 tw32(GRC_MODE,
1834 tw32(GRC_MISC_CFG,
1839 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
1841 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
1843 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
1844 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
1845 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
1848 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1850 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1852 tw32(BUFMGR_MB_HIGH_WATER,
1855 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1857 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1859 tw32(BUFMGR_MB_HIGH_WATER,
1862 tw32(BUFMGR_DMA_LOW_WATER,
1864 tw32(BUFMGR_DMA_HIGH_WATER,
1867 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
1878 tw32(FTQ_RESET, 0xffffffff);
1879 tw32(FTQ_RESET, 0x00000000);
1932 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
1935 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
2010 tw32(HOSTCC_MODE, 0);
2058 tw32(TG3PCI_X_CAPS, val);
2136 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2138 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2154 tw32(MAC_LED_CTRL, 0);
2155 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2163 tw32(MAC_SERDES_CFG, 0x616000);
2168 tw32(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
2176 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
2177 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
2178 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
2179 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
2188 case 16: tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
2189 case 15: tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
2190 case 14: tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
2191 case 13: tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
2192 case 12: tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
2193 case 11: tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
2194 case 10: tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
2195 case 9: tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
2196 case 8: tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
2197 case 7: tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
2198 case 6: tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
2199 case 5: tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
2200 case 4: /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
2201 case 3: /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
2216 tw32(GRC_EEPROM_ADDR,
2237 tw32(NVRAM_CFG1, nvcfg1);
2260 tw32(GRC_EEPROM_ADDR,
2297 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2304 tw32(NVRAM_ADDR, offset);
2305 tw32(NVRAM_CMD,
2321 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2326 tw32(NVRAM_SWARB, 0x20);
2745 tw32(GRC_MODE, tp->grc_mode);
2750 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
2862 tw32(TG3PCI_CLOCK_CTRL, 0);
2908 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);