Lines Matching refs:ap
953 struct tg3_fiber_aneginfo *ap)
959 if (ap->state == ANEG_STATE_UNKNOWN) {
960 ap->rxconfig = 0;
961 ap->link_time = 0;
962 ap->cur_time = 0;
963 ap->ability_match_cfg = 0;
964 ap->ability_match_count = 0;
965 ap->ability_match = 0;
966 ap->idle_match = 0;
967 ap->ack_match = 0;
969 ap->cur_time++;
974 if (rx_cfg_reg != ap->ability_match_cfg) {
975 ap->ability_match_cfg = rx_cfg_reg;
976 ap->ability_match = 0;
977 ap->ability_match_count = 0;
979 if (++ap->ability_match_count > 1) {
980 ap->ability_match = 1;
981 ap->ability_match_cfg = rx_cfg_reg;
985 ap->ack_match = 1;
987 ap->ack_match = 0;
989 ap->idle_match = 0;
991 ap->idle_match = 1;
992 ap->ability_match_cfg = 0;
993 ap->ability_match_count = 0;
994 ap->ability_match = 0;
995 ap->ack_match = 0;
1000 ap->rxconfig = rx_cfg_reg;
1003 switch(ap->state) {
1005 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1006 ap->state = ANEG_STATE_AN_ENABLE;
1010 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1011 if (ap->flags & MR_AN_ENABLE) {
1012 ap->link_time = 0;
1013 ap->cur_time = 0;
1014 ap->ability_match_cfg = 0;
1015 ap->ability_match_count = 0;
1016 ap->ability_match = 0;
1017 ap->idle_match = 0;
1018 ap->ack_match = 0;
1020 ap->state = ANEG_STATE_RESTART_INIT;
1022 ap->state = ANEG_STATE_DISABLE_LINK_OK;
1027 ap->link_time = ap->cur_time;
1028 ap->flags &= ~(MR_NP_LOADED);
1029 ap->txconfig = 0;
1035 ap->state = ANEG_STATE_RESTART;
1039 delta = ap->cur_time - ap->link_time;
1041 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1052 ap->flags &= ~(MR_TOGGLE_TX);
1053 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1054 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1058 ap->state = ANEG_STATE_ABILITY_DETECT;
1062 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1063 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1068 ap->txconfig |= ANEG_CFG_ACK;
1069 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1073 ap->state = ANEG_STATE_ACK_DETECT;
1077 if (ap->ack_match != 0) {
1078 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1079 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1080 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1082 ap->state = ANEG_STATE_AN_ENABLE;
1084 } else if (ap->ability_match != 0 &&
1085 ap->rxconfig == 0) {
1086 ap->state = ANEG_STATE_AN_ENABLE;
1091 if (ap->rxconfig & ANEG_CFG_INVAL) {
1095 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1104 if (ap->rxconfig & ANEG_CFG_FD)
1105 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
1106 if (ap->rxconfig & ANEG_CFG_HD)
1107 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
1108 if (ap->rxconfig & ANEG_CFG_PS1)
1109 ap->flags |= MR_LP_ADV_SYM_PAUSE;
1110 if (ap->rxconfig & ANEG_CFG_PS2)
1111 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
1112 if (ap->rxconfig & ANEG_CFG_RF1)
1113 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
1114 if (ap->rxconfig & ANEG_CFG_RF2)
1115 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
1116 if (ap->rxconfig & ANEG_CFG_NP)
1117 ap->flags |= MR_LP_ADV_NEXT_PAGE;
1119 ap->link_time = ap->cur_time;
1121 ap->flags ^= (MR_TOGGLE_TX);
1122 if (ap->rxconfig & 0x0008)
1123 ap->flags |= MR_TOGGLE_RX;
1124 if (ap->rxconfig & ANEG_CFG_NP)
1125 ap->flags |= MR_NP_RX;
1126 ap->flags |= MR_PAGE_RX;
1128 ap->state = ANEG_STATE_COMPLETE_ACK;
1133 if (ap->ability_match != 0 &&
1134 ap->rxconfig == 0) {
1135 ap->state = ANEG_STATE_AN_ENABLE;
1138 delta = ap->cur_time - ap->link_time;
1140 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
1141 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1143 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
1144 !(ap->flags & MR_NP_RX)) {
1145 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1154 ap->link_time = ap->cur_time;
1158 ap->state = ANEG_STATE_IDLE_DETECT;
1163 if (ap->ability_match != 0 &&
1164 ap->rxconfig == 0) {
1165 ap->state = ANEG_STATE_AN_ENABLE;
1168 delta = ap->cur_time - ap->link_time;
1171 ap->state = ANEG_STATE_LINK_OK;
1176 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);