History log of /illumos-gate/usr/src/common/crypto/modes/amd64/gcm_intel.s
Revision Date Author Comments Expand
8de5c4f463386063e184a851437d58080c6c626c 21-Nov-2009 Dan OpenSolaris Anderson <opensolaris@drydog.com>

6899006 Remove .byte asm directives and use new Intel Westmere opcodes 6647055 x86_64 MD5/SHA1 assembly source should use 32-bit registers when the assembler supports it

/illumos-gate/usr/src/common/bignum/bignumimpl.c /illumos-gate/usr/src/common/bignum/sun4u/mont_mulf_kernel_v9.s /illumos-gate/usr/src/common/crypto/aes/amd64/aes_intel.s /illumos-gate/usr/src/common/crypto/arcfour/arcfour_crypt.c /illumos-gate/usr/src/common/crypto/md5/amd64/md5_amd64.pl /illumos-gate/usr/src/common/crypto/md5/md5.c /illumos-gate/usr/src/common/crypto/md5/md5_byteswap.h gcm_intel.s /illumos-gate/usr/src/common/crypto/sha1/amd64/sha1-x86_64.pl /illumos-gate/usr/src/common/crypto/sha1/sha1.c /illumos-gate/usr/src/common/crypto/sha2/amd64/sha512-x86_64.pl /illumos-gate/usr/src/common/crypto/sha2/sha2.c /illumos-gate/usr/src/lib/libmd/Makefile.com /illumos-gate/usr/src/uts/common/crypto/io/md5_mod.c /illumos-gate/usr/src/uts/common/crypto/io/sha1_mod.c /illumos-gate/usr/src/uts/common/crypto/io/sha2_mod.c /illumos-gate/usr/src/uts/intel/md5/Makefile /illumos-gate/usr/src/uts/intel/sha1/Makefile /illumos-gate/usr/src/uts/intel/sha2/Makefile /illumos-gate/usr/src/uts/sparc/aes/Makefile /illumos-gate/usr/src/uts/sparc/arcfour/Makefile /illumos-gate/usr/src/uts/sparc/md5/Makefile /illumos-gate/usr/src/uts/sparc/sha1/Makefile /illumos-gate/usr/src/uts/sparc/sha2/Makefile /illumos-gate/usr/src/uts/sun4u/aes/Makefile /illumos-gate/usr/src/uts/sun4u/arcfour/Makefile /illumos-gate/usr/src/uts/sun4u/bignum/Makefile /illumos-gate/usr/src/uts/sun4u/md5/Makefile /illumos-gate/usr/src/uts/sun4u/sha1/Makefile /illumos-gate/usr/src/uts/sun4v/arcfour/Makefile /illumos-gate/usr/src/uts/sun4v/md5/Makefile
104d3bde5b4ac46904f144d3676110fc57a69603 24-Sep-2009 Dan OpenSolaris Anderson <opensolaris@drydog.com>

6826942 Need an optimized GCM leveraging Intel's PCMULQDQ instruction