cpu.h revision 27268f5d1d723d53b107fd3c0672cec7d752ca74
/*
* i386 virtual CPU header
*
* Copyright (c) 2003 Fabrice Bellard
*
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
* other than GPL or LGPL is available it will apply instead, Sun elects to use only
* the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
* a choice of LGPL license versions is made available with the language indicating
* that LGPLv2 or any later version may be used, or where a choice of which version
* of the LGPL is applied is otherwise unspecified.
*/
#ifndef CPU_I386_H
#define CPU_I386_H
#include "config.h"
#ifdef TARGET_X86_64
#define TARGET_LONG_BITS 64
#else
#define TARGET_LONG_BITS 32
#endif
/* target supports implicit self modifying code */
#define TARGET_HAS_SMC
/* support for self modifying code even if the modified instruction is
close to the modifying instruction */
#define TARGET_HAS_PRECISE_SMC
#define TARGET_HAS_ICE 1
#ifdef TARGET_X86_64
#define ELF_MACHINE EM_X86_64
#else
#define ELF_MACHINE EM_386
#endif
#include "cpu-defs.h"
#include "softfloat.h"
#if defined(VBOX)
# include <iprt/critsect.h>
#endif /* VBOX */
#define R_EAX 0
#define R_ECX 1
#define R_EDX 2
#define R_EBX 3
#define R_ESP 4
#define R_EBP 5
#define R_ESI 6
#define R_EDI 7
#define R_AL 0
#define R_CL 1
#define R_DL 2
#define R_BL 3
#define R_AH 4
#define R_CH 5
#define R_DH 6
#define R_BH 7
#define R_ES 0
#define R_CS 1
#define R_SS 2
#define R_DS 3
#define R_FS 4
#define R_GS 5
/* segment descriptor fields */
#define DESC_B_SHIFT 22
#define DESC_DPL_SHIFT 13
#define DESC_TYPE_SHIFT 8
/* eflags masks */
#define CC_C 0x0001
#define CC_P 0x0004
#define CC_A 0x0010
#define CC_Z 0x0040
#define CC_S 0x0080
#define CC_O 0x0800
#define TF_SHIFT 8
#define IOPL_SHIFT 12
#define VM_SHIFT 17
#define TF_MASK 0x00000100
#define IF_MASK 0x00000200
#define DF_MASK 0x00000400
#define IOPL_MASK 0x00003000
#define NT_MASK 0x00004000
#define RF_MASK 0x00010000
#define VM_MASK 0x00020000
#define AC_MASK 0x00040000
#define VIF_MASK 0x00080000
#define VIP_MASK 0x00100000
#define ID_MASK 0x00200000
/* hidden flags - used internally by qemu to represent additionnal cpu
states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not redundant. We avoid
using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
with eflags. */
/* current cpl */
#define HF_CPL_SHIFT 0
/* true if soft mmu is being used */
#define HF_SOFTMMU_SHIFT 2
/* true if hardware interrupts must be disabled for next instruction */
#define HF_INHIBIT_IRQ_SHIFT 3
/* 16 or 32 segments */
#define HF_CS32_SHIFT 4
#define HF_SS32_SHIFT 5
/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
#define HF_ADDSEG_SHIFT 6
/* copy of CR0.PE (protected mode) */
#define HF_PE_SHIFT 7
#define HF_EM_SHIFT 10
#define HF_TS_SHIFT 11
/* hflags2 */
#define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
#define CR0_PE_MASK (1 << 0)
#define CR4_VME_MASK (1 << 0)
#define PG_PRESENT_BIT 0
#define PG_RW_BIT 1
#define PG_USER_BIT 2
#define PG_PWT_BIT 3
#define PG_PCD_BIT 4
#define PG_ACCESSED_BIT 5
#define PG_DIRTY_BIT 6
#define PG_PSE_BIT 7
#define PG_GLOBAL_BIT 8
#define PG_NX_BIT 63
#define PG_ERROR_W_BIT 1
#define PG_ERROR_P_MASK 0x01
#define PG_ERROR_U_MASK 0x04
#define PG_ERROR_RSVD_MASK 0x08
#define PG_ERROR_I_D_MASK 0x10
#define MSR_IA32_APICBASE 0x1b
#ifndef MSR_IA32_SYSENTER_CS /* VBox x86.h klugde */
#define MSR_IA32_SYSENTER_CS 0x174
#define MSR_IA32_SYSENTER_ESP 0x175
#define MSR_IA32_SYSENTER_EIP 0x176
#endif
#define MSR_IA32_SYSENTER_CS 0x174
#define MSR_IA32_SYSENTER_ESP 0x175
#define MSR_IA32_SYSENTER_EIP 0x176
#define MSR_MCG_CAP 0x179
#define MSR_MCG_STATUS 0x17a
#define MSR_MCG_CTL 0x17b
#define MSR_PAT 0x277
#define MSR_EFER 0xc0000080
#define MSR_EFER_SCE (1 << 0)
#ifdef VBOX
#define MSR_APIC_RANGE_START 0x800
#define MSR_APIC_RANGE_END 0x900
#endif
#define MSR_STAR 0xc0000081
#define MSR_LSTAR 0xc0000082
#define MSR_CSTAR 0xc0000083
#define MSR_FMASK 0xc0000084
#define MSR_FSBASE 0xc0000100
#define MSR_GSBASE 0xc0000101
#define MSR_KERNELGSBASE 0xc0000102
#define MSR_VM_HSAVE_PA 0xc0010117
/* cpuid_features bits */
#define CPUID_FP87 (1 << 0)
#define CPUID_EXT_SSE3 (1 << 0)
#define CPUID_EXT3_LAHF_LM (1 << 0)
#define EXCP00_DIVZ 0
#define EXCP01_SSTP 1
#define EXCP02_NMI 2
#define EXCP03_INT3 3
#define EXCP04_INTO 4
#define EXCP05_BOUND 5
#define EXCP06_ILLOP 6
#define EXCP07_PREX 7
#define EXCP08_DBLE 8
#define EXCP09_XERR 9
#define EXCP0A_TSS 10
#define EXCP0B_NOSEG 11
#define EXCP0C_STACK 12
#define EXCP0D_GPF 13
#define EXCP0E_PAGE 14
#define EXCP10_COPR 16
#define EXCP11_ALGN 17
#define EXCP12_MCHK 18
for syscall instruction */
enum {
CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
CC_OP_LOGICB, /* modify all flags, CC_DST = res */
CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
};
#ifdef FLOATX80
#define USE_X86LDOUBLE
#endif
#ifdef USE_X86LDOUBLE
typedef floatx80 CPU86_LDouble;
#else
typedef float64 CPU86_LDouble;
#endif
typedef struct SegmentCache {
#ifdef VBOX
/** The new selector is saved here when we are unable to sync it before invoking the recompiled code. */
#endif
} SegmentCache;
typedef union {
} XMMReg;
typedef union {
uint64_t q;
} MMXReg;
#ifdef WORDS_BIGENDIAN
#else
#endif
#define MMX_Q(n) q
#ifdef TARGET_X86_64
#define CPU_NB_REGS 16
#else
#define CPU_NB_REGS 8
#endif
#define NB_MMU_MODES 2
typedef struct CPUX86State {
/* standard registers */
flags and DF are set to zero because they are
stored elsewhere */
/* emulator internal eflags handling */
are known at translation time. */
/* segments */
/* FPU state */
unsigned int fpstt; /* top of stack index */
unsigned int fpus;
unsigned int fpuc;
union {
#ifdef USE_X86LDOUBLE
#else
#endif
} fpregs[8];
/* emulator internal variables */
#ifdef VBOX
#endif
#endif
/* sysenter registers */
#ifdef VBOX
#endif
#ifdef TARGET_X86_64
#endif
int error_code;
int exception_is_int;
int old_exception; /* exception in flight */
#ifdef VBOX
/** cpu state flags. (see defines below) */
/** The VM handle. */
/** code buffer for instruction emulation */
void *pvCodeBuffer;
/** code buffer size */
#endif /* VBOX */
/* processor features (e.g. for CPUID insn) */
#ifndef VBOX /* remR3CpuId deals with these */
#endif /* !VBOX */
#ifndef VBOX
#endif /* !VBOX */
#ifndef VBOX
#ifdef USE_KQEMU
int kqemu_enabled;
int last_io_time;
#endif
/* in order to simplify APIC support, we leave this pointer to the
user */
struct APICState *apic_state;
#else
#endif
} CPUX86State;
#ifdef VBOX
/* Version 1.6 structure; just for loading the old saved state */
typedef struct SegmentCache_Ver16 {
/** The new selector is saved here when we are unable to sync it before invoking the recompiled code. */
#define CPU_NB_REGS_VER16 8
/* Version 1.6 structure; just for loading the old saved state */
typedef struct CPUX86State_Ver16 {
/* temporaries if we cannot store them in host registers */
#endif
/* standard registers */
flags and DF are set to zero because they are
stored elsewhere */
/* emulator internal eflags handling */
/* segments */
/* FPU state */
unsigned int fpstt; /* top of stack index */
unsigned int fpus;
unsigned int fpuc;
union {
#ifdef USE_X86LDOUBLE
#else
#endif
} fpregs[8];
/* emulator internal variables */
#ifdef VBOX
#endif
#endif
union {
float f;
double d;
int i32;
} fp_convert;
/* sysenter registers */
#ifdef VBOX
#endif
/* temporary data for USE_CODE_COPY mode */
#ifdef USE_CODE_COPY
int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
#endif
/** CPUX86State state flags
* @{ */
/** @} */
#endif /* !VBOX */
#ifdef VBOX
#else /* !VBOX */
#endif /* !VBOX */
int cpu_x86_exec(CPUX86State *s);
void cpu_x86_close(CPUX86State *s);
...));
int cpu_get_pic_interrupt(CPUX86State *s);
/* MSDOS compatibility mode FPU exception support */
void cpu_set_ferr(CPUX86State *s);
/* this function must always be used to load data in the segment
cache: it synchronizes the hflags with the segment cache values */
unsigned int limit,
unsigned int flags)
{
unsigned int new_hflags;
#ifdef VBOX
sc->newselector = 0;
#endif
/* update the hidden flags */
{
#ifdef TARGET_X86_64
/* long mode */
} else
#endif
{
/* legacy / compatibility case */
>> (DESC_B_SHIFT - HF_CS32_SHIFT);
}
}
>> (DESC_B_SHIFT - HF_SS32_SHIFT);
/* zero base assumed for DS, ES and SS in long mode */
/* XXX: try to avoid this test. The problem comes from the
fact that is real mode or vm86 mode we only modify the
'base' and 'selector' fields of the segment cache to go
faster. A solution may be to force addseg to one in
translate-i386.c. */
} else {
}
}
}
/* wrapper, just in case memory mappings must be changed */
{
#if HF_CPL_MASK == 3
#else
#endif
}
/* the following helpers are only usable in user mode simulation as
they can trigger unexpected exceptions */
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
void *puc);
#ifndef NO_CPU_IO_DEFS
#endif
#ifdef VBOX
#endif
/* will be suppressed */
/* used to debug */
#ifdef USE_KQEMU
static inline int cpu_get_time_fast(void)
{
return low;
}
#endif
#ifdef VBOX
/* in helper.c */
/* in helper.c */
#endif
#define TARGET_PAGE_BITS 12
#define CPUState CPUX86State
#define cpu_init cpu_x86_init
#define cpu_exec cpu_x86_exec
#define cpu_gen_code cpu_x86_gen_code
#define cpu_list x86_cpu_list
#define CPU_SAVE_VERSION 7
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
{
}
void optimize_flags_init(void);
typedef struct CCTable {
int (*compute_all)(void); /* return all the flags */
int (*compute_c)(void); /* return the C flag */
} CCTable;
#if defined(CONFIG_USER_ONLY)
{
if (newsp)
}
#endif
#include "cpu-all.h"
#include "svm.h"
#endif /* CPU_I386_H */