tcg-target.c revision 88cc6bfb70dbd23172f00ed679d5f1df8e9d7f53
2N/Astatic const int tcg_target_reg_alloc_order[] = {
switch(type) {
case R_X86_64_32:
tcg_abort();
case R_X86_64_32S:
tcg_abort();
case R_386_PC32:
tcg_abort();
tcg_abort();
const char *ct_str;
switch(ct_str[0]) {
ct_str++;
int ct;
#define ARITH_ADD 0
int rex;
if (rm < 0) {
tcg_abort();
#if defined(CONFIG_SOFTMMU)
int mod;
tcg_abort();
mod = 0;
tcg_abort();
if (arg == 0) {
tcg_abort();
if (val != 0)
if (l->has_value) {
if (const_arg2) {
if (arg2 == 0) {
if (rexw)
#ifdef VBOX
#if defined(CONFIG_SOFTMMU)
#include "../../softmmu_defs.h"
static void *vbox_ld_helpers[] = {
static void *vbox_st_helpers[] = {
int opc)
#if defined(CONFIG_SOFTMMU)
rexw = 0;
#if defined(CONFIG_SOFTMMU)
s->code_ptr++;
#ifndef VBOX
switch(opc) {
s->code_ptr++;
#ifdef TARGET_WORDS_BIGENDIAN
bswap = 0;
switch(opc) {
if (bswap) {
if (bswap) {
if (bswap) {
if (bswap) {
if (bswap) {
tcg_abort();
#if defined(CONFIG_SOFTMMU)
int opc)
#if defined(CONFIG_SOFTMMU)
rexw = 0;
#if defined(CONFIG_SOFTMMU)
s->code_ptr++;
switch(opc) {
#ifndef VBOX
s->code_ptr++;
#ifdef TARGET_WORDS_BIGENDIAN
bswap = 0;
switch(opc) {
if (bswap) {
if (bswap) {
if (bswap) {
tcg_abort();
#if defined(CONFIG_SOFTMMU)
const int *const_args)
switch(opc) {
case INDEX_op_exit_tb:
#ifndef VBOX
case INDEX_op_goto_tb:
if (s->tb_jmp_offset) {
tcg_out32(s, 0);
#ifndef VBOX
args[0]));
case INDEX_op_call:
if (const_args[0]) {
#ifndef VBOX
case INDEX_op_jmp:
if (const_args[0]) {
case INDEX_op_br:
case INDEX_op_movi_i32:
case INDEX_op_movi_i64:
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
case INDEX_op_ld8s_i32:
case INDEX_op_ld8s_i64:
case INDEX_op_ld16u_i32:
case INDEX_op_ld16u_i64:
case INDEX_op_ld16s_i32:
case INDEX_op_ld16s_i64:
case INDEX_op_ld_i32:
case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64:
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
case INDEX_op_st16_i32:
case INDEX_op_st16_i64:
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
case INDEX_op_sub_i32:
c = ARITH_SUB;
goto gen_arith32;
case INDEX_op_and_i32:
c = ARITH_AND;
goto gen_arith32;
case INDEX_op_or_i32:
c = ARITH_OR;
goto gen_arith32;
case INDEX_op_xor_i32:
c = ARITH_XOR;
goto gen_arith32;
case INDEX_op_add_i32:
c = ARITH_ADD;
case INDEX_op_sub_i64:
c = ARITH_SUB;
goto gen_arith64;
case INDEX_op_and_i64:
c = ARITH_AND;
goto gen_arith64;
case INDEX_op_or_i64:
c = ARITH_OR;
goto gen_arith64;
case INDEX_op_xor_i64:
c = ARITH_XOR;
goto gen_arith64;
case INDEX_op_add_i64:
c = ARITH_ADD;
case INDEX_op_mul_i32:
case INDEX_op_mul_i64:
case INDEX_op_div2_i32:
case INDEX_op_divu2_i32:
case INDEX_op_div2_i64:
case INDEX_op_divu2_i64:
case INDEX_op_shl_i32:
c = SHIFT_SHL;
case INDEX_op_shr_i32:
c = SHIFT_SHR;
goto gen_shift32;
case INDEX_op_sar_i32:
c = SHIFT_SAR;
goto gen_shift32;
case INDEX_op_shl_i64:
c = SHIFT_SHL;
case INDEX_op_shr_i64:
c = SHIFT_SHR;
goto gen_shift64;
case INDEX_op_sar_i64:
c = SHIFT_SAR;
goto gen_shift64;
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
case INDEX_op_bswap_i32:
case INDEX_op_bswap_i64:
case INDEX_op_neg_i32:
case INDEX_op_neg_i64:
case INDEX_op_ext8s_i32:
case INDEX_op_ext16s_i32:
case INDEX_op_ext8s_i64:
case INDEX_op_ext16s_i64:
case INDEX_op_ext32s_i64:
case INDEX_op_qemu_ld8u:
case INDEX_op_qemu_ld8s:
case INDEX_op_qemu_ld16u:
case INDEX_op_qemu_ld16s:
case INDEX_op_qemu_ld32u:
case INDEX_op_qemu_ld32s:
case INDEX_op_qemu_ld64:
case INDEX_op_qemu_st8:
case INDEX_op_qemu_st16:
case INDEX_op_qemu_st32:
case INDEX_op_qemu_st64:
tcg_abort();
static int tcg_target_callee_save_regs[] = {
{ INDEX_op_exit_tb, { } },
{ INDEX_op_goto_tb, { } },
{ INDEX_op_br, { } },
tcg_abort();