tcg-target.c revision 4af48bf7c72ef1e201c64bd475377b5af9d8e8a1
/*
* Tiny Code Generator for QEMU
*
* Copyright (c) 2008 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef NDEBUG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"%rax",
"%rcx",
"%rdx",
"%rbx",
"%rsp",
"%rbp",
"%rsi",
"%rdi",
"%r8",
"%r9",
"%r10",
"%r11",
"%r12",
"%r13",
"%r14",
"%r15",
};
#endif
static const int tcg_target_reg_alloc_order[] = {
};
static const int tcg_target_call_iarg_regs[6] = {
};
static const int tcg_target_call_oarg_regs[2] = {
};
static uint8_t *tb_ret_addr;
{
switch(type) {
case R_X86_64_32:
tcg_abort();
break;
case R_X86_64_32S:
tcg_abort();
break;
case R_386_PC32:
tcg_abort();
break;
default:
tcg_abort();
}
}
/* maximum number of register used for input function arguments */
static inline int tcg_target_get_call_iarg_regs_count(int flags)
{
return 6;
}
/* parse target specific constraints */
{
const char *ct_str;
switch(ct_str[0]) {
case 'a':
break;
case 'b':
break;
case 'c':
break;
case 'd':
break;
case 'S':
break;
case 'D':
break;
case 'q':
break;
case 'r':
break;
break;
case 'e':
break;
case 'Z':
break;
default:
return -1;
}
ct_str++;
return 0;
}
/* test if a constant matches the constraint */
const TCGArgConstraint *arg_ct)
{
int ct;
if (ct & TCG_CT_CONST)
return 1;
return 1;
return 1;
else
return 0;
}
#define ARITH_ADD 0
#define ARITH_OR 1
#define ARITH_ADC 2
#define ARITH_SBB 3
#define ARITH_AND 4
#define ARITH_SUB 5
#define ARITH_XOR 6
#define ARITH_CMP 7
#define SHIFT_SHL 4
#define SHIFT_SHR 5
#define SHIFT_SAR 7
#define JCC_JMP (-1)
#define JCC_JO 0x0
#define JCC_JNO 0x1
#define JCC_JB 0x2
#define JCC_JAE 0x3
#define JCC_JE 0x4
#define JCC_JNE 0x5
#define JCC_JBE 0x6
#define JCC_JA 0x7
#define JCC_JS 0x8
#define JCC_JNS 0x9
#define JCC_JP 0xa
#define JCC_JNP 0xb
#define JCC_JL 0xc
#define JCC_JGE 0xd
#define JCC_JLE 0xe
#define JCC_JG 0xf
[TCG_COND_EQ] = JCC_JE,
[TCG_COND_NE] = JCC_JNE,
[TCG_COND_LT] = JCC_JL,
[TCG_COND_GE] = JCC_JGE,
[TCG_COND_LE] = JCC_JLE,
[TCG_COND_GT] = JCC_JG,
[TCG_COND_LTU] = JCC_JB,
[TCG_COND_GEU] = JCC_JAE,
[TCG_COND_LEU] = JCC_JBE,
[TCG_COND_GTU] = JCC_JA,
};
{
int rex;
}
tcg_out8(s, 0x0f);
}
{
}
/* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
{
if (rm < 0) {
tcg_out_opc(s, opc, r, 0, 0);
/* eip relative */
} else {
tcg_abort();
}
tcg_out8(s, 0x24);
} else {
}
tcg_out8(s, 0x24);
} else {
}
} else {
tcg_out8(s, 0x24);
} else {
}
}
}
#if defined(CONFIG_SOFTMMU)
/* XXX: incomplete. index must be different from ESP */
{
int mod;
if (rm == -1)
tcg_abort();
mod = 0;
mod = 0x40;
mod = 0x80;
} else {
tcg_abort();
}
if (index == -1) {
} else {
}
} else {
}
if (mod == 0x40) {
} else if (mod == 0x80) {
}
}
#endif
{
}
{
if (arg == 0) {
} else {
}
}
{
if (type == TCG_TYPE_I32)
else
}
{
if (type == TCG_TYPE_I32)
else
}
{
/* movzbl */
/* movzwl */
} else {
}
}
{
/* movzbl */
/* movzwl */
/* 32-bit mov zero extends */
} else {
tcg_abort();
}
}
{
if (val != 0)
}
{
if (l->has_value) {
if (opc == -1)
tcg_out8(s, 0xeb);
else
} else {
if (opc == -1) {
tcg_out8(s, 0xe9);
} else {
tcg_out8(s, 0x0f);
}
}
} else {
if (opc == -1) {
tcg_out8(s, 0xe9);
} else {
tcg_out8(s, 0x0f);
}
s->code_ptr += 4;
}
}
int label_index, int rexw)
{
if (const_arg2) {
if (arg2 == 0) {
/* test r, r */
} else {
if (rexw)
else
}
} else {
}
}
#ifdef VBOX
{
if ((val >> 32) != 0)
{
tcg_out8(s, 0x44);
tcg_out8(s, 0x24);
tcg_out8(s, 0x04);
}
}
{
/* can do normal call */
{
}
else
{
# if 0
/* Somewhat tricky, but allows long jump not touching registers */
off += 8;
if (dst >> 32)
off += 8;
/* return address */
/* destination */
tcg_out_pushq(s, dst);
# else
tcg_out8(s, 0xd0);
# endif
}
}
{
/* can do short relative jump */
{
return;
}
{
return;
}
# if 0
tcg_out_pushq(s, dst);
# else
tcg_out8(s, 0xe0);
# endif
}
#endif /* VBOX */
#if defined(CONFIG_SOFTMMU)
#include "../../softmmu_defs.h"
static void *qemu_ld_helpers[4] = {
};
static void *qemu_st_helpers[4] = {
};
#endif
#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
static void *vbox_ld_helpers[] = {
};
static void *vbox_st_helpers[] = {
};
if (addr_reg != TCG_REG_RDI)
/* mov addr_reg, %rdi */
/* mov %rax, data_reg*/
}
if (addr_reg != TCG_REG_RDI)
/* mov addr_reg, %rdi */
if (val_reg != TCG_REG_RSI)
/* mov addr_reg, %rsi */
}
#endif /* VBOX && REM_PHYS_ADDR_IN_TLB */
int opc)
{
#if defined(CONFIG_SOFTMMU)
#endif
r0 = TCG_REG_RDI;
r1 = TCG_REG_RSI;
#if TARGET_LONG_BITS == 32
rexw = 0;
#else
#endif
#if defined(CONFIG_SOFTMMU)
/* mov */
/* mov */
/* lea offset(r1, env), r1 */
/* cmp 0(r1), r0 */
/* mov */
/* je label1 */
label1_ptr = s->code_ptr;
s->code_ptr++;
/* XXX: move that code at the end of the TB */
#ifndef VBOX
tcg_out8(s, 0xe8);
#else
#endif
switch(opc) {
case 0 | 4:
/* movsbq */
break;
case 1 | 4:
/* movswq */
break;
case 2 | 4:
/* movslq */
break;
case 0:
/* movzbq */
break;
case 1:
/* movzwq */
break;
case 2:
default:
/* movl */
break;
case 3:
break;
}
/* jmp label2 */
tcg_out8(s, 0xeb);
label2_ptr = s->code_ptr;
s->code_ptr++;
/* label1: */
/* add x(r1), r0 */
#else
#endif
#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
#ifdef TARGET_WORDS_BIGENDIAN
bswap = 1;
#else
bswap = 0;
#endif
switch(opc) {
case 0:
/* movzbl */
break;
case 0 | 4:
/* movsbX */
break;
case 1:
/* movzwl */
if (bswap) {
/* rolw $8, data_reg */
tcg_out8(s, 0x66);
tcg_out8(s, 8);
}
break;
case 1 | 4:
if (bswap) {
/* movzwl */
/* rolw $8, data_reg */
tcg_out8(s, 0x66);
tcg_out8(s, 8);
/* movswX data_reg, data_reg */
} else {
/* movswX */
}
break;
case 2:
/* movl (r0), data_reg */
if (bswap) {
/* bswap */
}
break;
case 2 | 4:
if (bswap) {
/* movl (r0), data_reg */
/* bswap */
/* movslq */
} else {
/* movslq */
}
break;
case 3:
/* movq (r0), data_reg */
if (bswap) {
/* bswap */
}
break;
default:
tcg_abort();
}
#else /* VBOX && REM_PHYS_ADDR_IN_TLB */
#endif /* VBOX && REM_PHYS_ADDR_IN_TLB */
#if defined(CONFIG_SOFTMMU)
/* label2: */
#endif
}
int opc)
{
#if defined(CONFIG_SOFTMMU)
#endif
r0 = TCG_REG_RDI;
r1 = TCG_REG_RSI;
#if TARGET_LONG_BITS == 32
rexw = 0;
#else
#endif
#if defined(CONFIG_SOFTMMU)
/* mov */
/* mov */
/* lea offset(r1, env), r1 */
/* cmp 0(r1), r0 */
/* mov */
/* je label1 */
label1_ptr = s->code_ptr;
s->code_ptr++;
/* XXX: move that code at the end of the TB */
switch(opc) {
case 0:
/* movzbl */
break;
case 1:
/* movzwl */
break;
case 2:
/* movl */
break;
default:
case 3:
break;
}
#ifndef VBOX
tcg_out8(s, 0xe8);
#else
#endif
/* jmp label2 */
tcg_out8(s, 0xeb);
label2_ptr = s->code_ptr;
s->code_ptr++;
/* label1: */
/* add x(r1), r0 */
#else
#endif
#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
#ifdef TARGET_WORDS_BIGENDIAN
bswap = 1;
#else
bswap = 0;
#endif
switch(opc) {
case 0:
/* movb */
break;
case 1:
if (bswap) {
tcg_out8(s, 8);
}
/* movw */
tcg_out8(s, 0x66);
break;
case 2:
if (bswap) {
/* bswap data_reg */
}
/* movl */
break;
case 3:
if (bswap) {
/* bswap data_reg */
}
/* movq */
break;
default:
tcg_abort();
}
#else /* VBOX && REM_PHYS_ADDR_IN_TLB */
#endif /* VBOX && REM_PHYS_ADDR_IN_TLB */
#if defined(CONFIG_SOFTMMU)
/* label2: */
#endif
}
const int *const_args)
{
int c;
switch(opc) {
case INDEX_op_exit_tb:
#ifndef VBOX
#else
#endif
break;
case INDEX_op_goto_tb:
if (s->tb_jmp_offset) {
/* direct jump method */
tcg_out32(s, 0);
} else {
/* indirect jump method */
/* jmp Ev */
#ifndef VBOX
(tcg_target_long)(s->tb_next +
args[0]));
#else
/** @todo: can we clobber RAX here? */
#endif
}
break;
case INDEX_op_call:
if (const_args[0]) {
#ifndef VBOX
tcg_out8(s, 0xe8);
#else
tcg_out_long_call(s, args[0]);
#endif
} else {
}
break;
case INDEX_op_jmp:
if (const_args[0]) {
tcg_out8(s, 0xe9);
} else {
}
break;
case INDEX_op_br:
break;
case INDEX_op_movi_i32:
break;
case INDEX_op_movi_i64:
break;
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
/* movzbl */
break;
case INDEX_op_ld8s_i32:
/* movsbl */
break;
case INDEX_op_ld8s_i64:
/* movsbq */
break;
case INDEX_op_ld16u_i32:
case INDEX_op_ld16u_i64:
/* movzwl */
break;
case INDEX_op_ld16s_i32:
/* movswl */
break;
case INDEX_op_ld16s_i64:
/* movswq */
break;
case INDEX_op_ld_i32:
case INDEX_op_ld32u_i64:
/* movl */
break;
case INDEX_op_ld32s_i64:
/* movslq */
break;
case INDEX_op_ld_i64:
/* movq */
break;
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
/* movb */
break;
case INDEX_op_st16_i32:
case INDEX_op_st16_i64:
/* movw */
tcg_out8(s, 0x66);
break;
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
/* movl */
break;
case INDEX_op_st_i64:
/* movq */
break;
case INDEX_op_sub_i32:
c = ARITH_SUB;
goto gen_arith32;
case INDEX_op_and_i32:
c = ARITH_AND;
goto gen_arith32;
case INDEX_op_or_i32:
c = ARITH_OR;
goto gen_arith32;
case INDEX_op_xor_i32:
c = ARITH_XOR;
goto gen_arith32;
case INDEX_op_add_i32:
c = ARITH_ADD;
if (const_args[2]) {
} else {
}
break;
case INDEX_op_sub_i64:
c = ARITH_SUB;
goto gen_arith64;
case INDEX_op_and_i64:
c = ARITH_AND;
goto gen_arith64;
case INDEX_op_or_i64:
c = ARITH_OR;
goto gen_arith64;
case INDEX_op_xor_i64:
c = ARITH_XOR;
goto gen_arith64;
case INDEX_op_add_i64:
c = ARITH_ADD;
if (const_args[2]) {
} else {
}
break;
case INDEX_op_mul_i32:
if (const_args[2]) {
} else {
}
} else {
}
break;
case INDEX_op_mul_i64:
if (const_args[2]) {
} else {
}
} else {
}
break;
case INDEX_op_div2_i32:
break;
case INDEX_op_divu2_i32:
break;
case INDEX_op_div2_i64:
break;
case INDEX_op_divu2_i64:
break;
case INDEX_op_shl_i32:
c = SHIFT_SHL;
if (const_args[2]) {
} else {
}
} else {
}
break;
case INDEX_op_shr_i32:
c = SHIFT_SHR;
goto gen_shift32;
case INDEX_op_sar_i32:
c = SHIFT_SAR;
goto gen_shift32;
case INDEX_op_shl_i64:
c = SHIFT_SHL;
if (const_args[2]) {
} else {
}
} else {
}
break;
case INDEX_op_shr_i64:
c = SHIFT_SHR;
goto gen_shift64;
case INDEX_op_sar_i64:
c = SHIFT_SAR;
goto gen_shift64;
case INDEX_op_brcond_i32:
args[3], 0);
break;
case INDEX_op_brcond_i64:
break;
case INDEX_op_bswap_i32:
break;
case INDEX_op_bswap_i64:
break;
case INDEX_op_neg_i32:
break;
case INDEX_op_neg_i64:
break;
case INDEX_op_ext8s_i32:
break;
case INDEX_op_ext16s_i32:
break;
case INDEX_op_ext8s_i64:
break;
case INDEX_op_ext16s_i64:
break;
case INDEX_op_ext32s_i64:
break;
case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0);
break;
case INDEX_op_qemu_ld8s:
break;
case INDEX_op_qemu_ld16u:
break;
case INDEX_op_qemu_ld16s:
break;
case INDEX_op_qemu_ld32u:
break;
case INDEX_op_qemu_ld32s:
break;
case INDEX_op_qemu_ld64:
break;
case INDEX_op_qemu_st8:
tcg_out_qemu_st(s, args, 0);
break;
case INDEX_op_qemu_st16:
break;
case INDEX_op_qemu_st32:
break;
case INDEX_op_qemu_st64:
break;
default:
tcg_abort();
}
}
static int tcg_target_callee_save_regs[] = {
/* TCG_REG_R14, */ /* currently used for the global env, so no
need to save */
};
{
}
{
}
/* Generate global QEMU prologue and epilogue code */
void tcg_target_qemu_prologue(TCGContext *s)
{
/* TB prologue */
/* save all callee saved registers */
for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
}
/* reserve some stack space */
~(TCG_TARGET_STACK_ALIGN - 1);
/* TB epilogue */
tb_ret_addr = s->code_ptr;
}
}
static const TCGTargetOpDef x86_64_op_defs[] = {
{ INDEX_op_exit_tb, { } },
{ INDEX_op_goto_tb, { } },
{ INDEX_op_br, { } },
{ INDEX_op_movi_i32, { "r" } },
{ INDEX_op_movi_i64, { "r" } },
{ -1 },
};
void tcg_target_init(TCGContext *s)
{
/* fail safe */
tcg_abort();
(1 << TCG_REG_RDI) |
(1 << TCG_REG_RSI) |
(1 << TCG_REG_RDX) |
(1 << TCG_REG_RCX) |
(1 << TCG_REG_R8) |
(1 << TCG_REG_R9) |
(1 << TCG_REG_RAX) |
(1 << TCG_REG_R10) |
(1 << TCG_REG_R11));
}