/*
* Tiny Code Generator for QEMU
*
* Copyright (c) 2008 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "tcg.h"
int gen_new_label(void);
{
*gen_opc_ptr++ = opc;
}
{
*gen_opc_ptr++ = opc;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg1;
}
{
*gen_opc_ptr++ = opc;
}
{
*gen_opc_ptr++ = opc;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg2;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg2;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg1;
*gen_opparam_ptr++ = arg2;
}
{
*gen_opc_ptr++ = opc;
}
{
*gen_opc_ptr++ = opc;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg3;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg3;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = offset;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = offset;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = mem_index;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = mem_index;
}
{
*gen_opc_ptr++ = opc;
}
{
*gen_opc_ptr++ = opc;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg4;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg4;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg3;
*gen_opparam_ptr++ = arg4;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg3;
*gen_opparam_ptr++ = arg4;
}
{
*gen_opc_ptr++ = opc;
}
{
*gen_opc_ptr++ = opc;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg5;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg5;
}
{
*gen_opc_ptr++ = opc;
}
{
*gen_opc_ptr++ = opc;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg6;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg6;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg5;
*gen_opparam_ptr++ = arg6;
}
{
*gen_opc_ptr++ = opc;
*gen_opparam_ptr++ = arg5;
*gen_opparam_ptr++ = arg6;
}
static inline void gen_set_label(int n)
{
}
{
}
{
}
{
}
/* A version of dh_sizemask from def-helper.h that doesn't rely on
preprocessor magic. */
{
}
/* helper calls */
{
}
/* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
reserved for helpers in tcg-runtime.c. These helpers are all const
and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST |
TCG_CALL_PURE. This may need to be adjusted if these functions
start to be used with other helpers. */
{
args[0] = GET_TCGV_I32(a);
}
{
args[0] = GET_TCGV_I64(a);
}
/* 32 bit ops */
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
/* some cases can be optimized here */
if (arg2 == 0) {
} else {
}
}
{
}
{
}
{
/* some cases can be optimized here */
if (arg2 == 0) {
} else {
}
}
{
} else {
}
}
{
/* some cases can be optimized here */
if (arg2 == 0) {
tcg_gen_movi_i32(ret, 0);
} else if (arg2 == 0xffffffff) {
} else {
}
}
{
} else {
}
}
{
/* some cases can be optimized here */
if (arg2 == 0xffffffff) {
} else if (arg2 == 0) {
} else {
}
}
{
tcg_gen_movi_i32(ret, 0);
} else {
}
}
{
/* some cases can be optimized here */
if (arg2 == 0) {
} else {
}
}
{
}
{
if (arg2 == 0) {
} else {
}
}
{
}
{
if (arg2 == 0) {
} else {
}
}
{
}
{
if (arg2 == 0) {
} else {
}
}
{
}
{
}
{
}
{
}
{
}
{
}
#ifdef TCG_TARGET_HAS_div_i32
{
}
{
}
{
}
{
}
#elif defined(TCG_TARGET_HAS_div2_i32)
{
t0 = tcg_temp_new_i32();
}
{
t0 = tcg_temp_new_i32();
}
{
t0 = tcg_temp_new_i32();
tcg_gen_movi_i32(t0, 0);
}
{
t0 = tcg_temp_new_i32();
tcg_gen_movi_i32(t0, 0);
}
#else
{
int sizemask = 0;
/* Return value and both arguments are 32-bit and signed. */
}
{
int sizemask = 0;
/* Return value and both arguments are 32-bit and signed. */
}
{
int sizemask = 0;
/* Return value and both arguments are 32-bit and unsigned. */
sizemask |= tcg_gen_sizemask(0, 0, 0);
}
{
int sizemask = 0;
/* Return value and both arguments are 32-bit and unsigned. */
sizemask |= tcg_gen_sizemask(0, 0, 0);
}
#endif
#if TCG_TARGET_REG_BITS == 32
{
}
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
/* since arg2 and ret have different types, they cannot be the
same temporary */
#ifdef TCG_TARGET_WORDS_BIGENDIAN
#else
#endif
}
{
}
{
}
{
}
{
#ifdef TCG_TARGET_WORDS_BIGENDIAN
#else
#endif
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
/* XXX: use generic code when basic block handling is OK or CPU
specific code (x86) */
{
int sizemask = 0;
/* Return value and both arguments are 64-bit and signed. */
}
{
}
{
int sizemask = 0;
/* Return value and both arguments are 64-bit and signed. */
}
{
}
{
int sizemask = 0;
/* Return value and both arguments are 64-bit and signed. */
}
{
}
{
}
{
}
{
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i32();
}
{
int sizemask = 0;
/* Return value and both arguments are 64-bit and signed. */
}
{
int sizemask = 0;
/* Return value and both arguments are 64-bit and signed. */
}
{
int sizemask = 0;
/* Return value and both arguments are 64-bit and unsigned. */
}
{
int sizemask = 0;
/* Return value and both arguments are 64-bit and unsigned. */
}
#else
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
} else {
}
}
{
}
{
} else {
}
}
{
}
{
tcg_gen_movi_i64(ret, 0);
} else {
}
}
{
}
{
}
{
if (arg2 == 0) {
} else {
}
}
{
}
{
if (arg2 == 0) {
} else {
}
}
{
}
{
if (arg2 == 0) {
} else {
}
}
{
}
{
}
{
}
#ifdef TCG_TARGET_HAS_div_i64
{
}
{
}
{
}
{
}
#elif defined(TCG_TARGET_HAS_div2_i64)
{
t0 = tcg_temp_new_i64();
}
{
t0 = tcg_temp_new_i64();
}
{
t0 = tcg_temp_new_i64();
tcg_gen_movi_i64(t0, 0);
}
{
t0 = tcg_temp_new_i64();
tcg_gen_movi_i64(t0, 0);
}
#else
{
int sizemask = 0;
/* Return value and both arguments are 64-bit and signed. */
}
{
int sizemask = 0;
/* Return value and both arguments are 64-bit and signed. */
}
{
int sizemask = 0;
/* Return value and both arguments are 64-bit and unsigned. */
}
{
int sizemask = 0;
/* Return value and both arguments are 64-bit and unsigned. */
}
#endif
#endif
{
/* some cases can be optimized here */
if (arg2 == 0) {
} else {
}
}
{
}
{
/* some cases can be optimized here */
if (arg2 == 0) {
} else {
}
}
{
}
{
}
{
}
/***************************************/
/* optional operations */
{
#ifdef TCG_TARGET_HAS_ext8s_i32
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_ext16s_i32
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_ext8u_i32
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_ext16u_i32
#else
#endif
}
/* Note: we assume the two high bytes are set to zero */
{
#ifdef TCG_TARGET_HAS_bswap16_i32
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_bswap32_i32
#else
t0 = tcg_temp_new_i32();
t1 = tcg_temp_new_i32();
#endif
}
#if TCG_TARGET_REG_BITS == 32
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
{
}
/* Note: we assume the six high bytes are set to zero */
{
}
/* Note: we assume the four high bytes are set to zero */
{
}
{
t0 = tcg_temp_new_i32();
t1 = tcg_temp_new_i32();
}
#else
{
#ifdef TCG_TARGET_HAS_ext8s_i64
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_ext16s_i64
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_ext32s_i64
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_ext8u_i64
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_ext16u_i64
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_ext32u_i64
#else
#endif
}
/* Note: we assume the target supports move between 32 and 64 bit
registers. This will probably break MIPS64 targets. */
{
}
/* Note: we assume the target supports move between 32 and 64 bit
registers */
{
}
/* Note: we assume the target supports move between 32 and 64 bit
registers */
{
}
/* Note: we assume the six high bytes are set to zero */
{
#ifdef TCG_TARGET_HAS_bswap16_i64
#else
#endif
}
/* Note: we assume the four high bytes are set to zero */
{
#ifdef TCG_TARGET_HAS_bswap32_i64
#else
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
#endif
}
{
#ifdef TCG_TARGET_HAS_bswap64_i64
#else
#endif
}
#endif
{
#ifdef TCG_TARGET_HAS_neg_i32
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_neg_i64
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_not_i32
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_not_i64
#else
#endif
}
{
}
#if TCG_TARGET_REG_BITS == 32
{
}
#else
{
}
#endif
{
#if TCG_TARGET_REG_BITS == 32
#else
/* This extension is only needed for type correctness.
We may be able to do better given target specific information. */
#endif
}
{
#if TCG_TARGET_REG_BITS == 32
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_andc_i32
#else
t0 = tcg_temp_new_i32();
#endif
}
{
#ifdef TCG_TARGET_HAS_andc_i64
#else
t0 = tcg_temp_new_i64();
#endif
}
{
#ifdef TCG_TARGET_HAS_eqv_i32
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_eqv_i64
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_nand_i32
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_nand_i64
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_nor_i32
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_nor_i64
#else
#endif
}
{
#ifdef TCG_TARGET_HAS_orc_i32
#else
t0 = tcg_temp_new_i32();
#endif
}
{
#ifdef TCG_TARGET_HAS_orc_i64
#else
t0 = tcg_temp_new_i64();
#endif
}
{
#ifdef TCG_TARGET_HAS_rot_i32
#else
t0 = tcg_temp_new_i32();
t1 = tcg_temp_new_i32();
#endif
}
{
#ifdef TCG_TARGET_HAS_rot_i64
#else
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
#endif
}
{
/* some cases can be optimized here */
if (arg2 == 0) {
} else {
#ifdef TCG_TARGET_HAS_rot_i32
#else
t0 = tcg_temp_new_i32();
t1 = tcg_temp_new_i32();
#endif
}
}
{
/* some cases can be optimized here */
if (arg2 == 0) {
} else {
#ifdef TCG_TARGET_HAS_rot_i64
#else
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
#endif
}
}
{
#ifdef TCG_TARGET_HAS_rot_i32
#else
t0 = tcg_temp_new_i32();
t1 = tcg_temp_new_i32();
#endif
}
{
#ifdef TCG_TARGET_HAS_rot_i64
#else
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
#endif
}
{
/* some cases can be optimized here */
if (arg2 == 0) {
} else {
}
}
{
/* some cases can be optimized here */
if (arg2 == 0) {
} else {
}
}
/***************************************/
/* QEMU specific operations. Their type depend on the QEMU CPU
type. */
#ifndef TARGET_LONG_BITS
#endif
#if TARGET_LONG_BITS == 32
#else
#endif
/* debug info: write the PC of the corresponding QEMU CPU instruction */
{
/* XXX: must really use a 32 bit size for TCGArg in all cases */
#else
#endif
}
{
}
{
}
#if TCG_TARGET_REG_BITS == 32
{
#if TARGET_LONG_BITS == 32
#else
#endif
}
{
#if TARGET_LONG_BITS == 32
#else
#endif
}
{
#if TARGET_LONG_BITS == 32
#else
#endif
}
{
#if TARGET_LONG_BITS == 32
#else
#endif
}
{
#if TARGET_LONG_BITS == 32
#else
#endif
}
{
#if TARGET_LONG_BITS == 32
#else
#endif
}
{
#if TARGET_LONG_BITS == 32
#else
#endif
}
{
#if TARGET_LONG_BITS == 32
#else
#endif
}
{
#if TARGET_LONG_BITS == 32
#else
#endif
}
{
#if TARGET_LONG_BITS == 32
#else
#endif
}
{
#if TARGET_LONG_BITS == 32
#else
#endif
}
#else /* TCG_TARGET_REG_BITS == 32 */
{
}
{
}
{
}
{
}
{
#if TARGET_LONG_BITS == 32
#else
#endif
}
{
#if TARGET_LONG_BITS == 32
#else
#endif
}
{
}
{
}
{
}
{
}
{
}
#endif /* TCG_TARGET_REG_BITS != 32 */
#if TARGET_LONG_BITS == 64
#else
#endif
#if TCG_TARGET_REG_BITS == 32
#else /* TCG_TARGET_REG_BITS == 32 */
#endif /* TCG_TARGET_REG_BITS != 32 */