tcg-target.c revision 3d40f685fa5cdd9cb665ae3cbf5f76113dafcb99
/*
* Tiny Code Generator for QEMU
*
* Copyright (c) 2008 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef NDEBUG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#if TCG_TARGET_REG_BITS == 64
"%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
"%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
#else
"%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
#endif
};
#endif
static const int tcg_target_reg_alloc_order[] = {
#if TCG_TARGET_REG_BITS == 64
# if !defined(VBOX) || !defined(__MINGW64__)
# endif
# if defined(VBOX) && defined(__MINGW64__)
# endif
#else
#endif
};
static const int tcg_target_call_iarg_regs[] = {
#if TCG_TARGET_REG_BITS == 64
# if defined(VBOX) && defined(__MINGW64__)
# else
# endif
#else
#endif
};
static const int tcg_target_call_oarg_regs[2] = {
};
static uint8_t *tb_ret_addr;
{
switch(type) {
case R_386_PC32:
tcg_abort();
}
break;
case R_386_PC8:
tcg_abort();
}
break;
default:
tcg_abort();
}
}
#ifdef VBOX
/* emits stack alignment checks for strict builds. */
{
# else
NOREF(s);
# endif
}
#endif /* VBOX */
/* maximum number of register used for input function arguments */
static inline int tcg_target_get_call_iarg_regs_count(int flags)
{
if (TCG_TARGET_REG_BITS == 64) {
return 6;
}
switch(flags) {
case TCG_CALL_TYPE_STD:
return 0;
case TCG_CALL_TYPE_REGPARM_1:
case TCG_CALL_TYPE_REGPARM_2:
case TCG_CALL_TYPE_REGPARM:
default:
tcg_abort();
}
}
/* parse target specific constraints */
{
const char *ct_str;
switch(ct_str[0]) {
case 'a':
break;
case 'b':
break;
case 'c':
break;
case 'd':
break;
case 'S':
break;
case 'D':
break;
case 'q':
if (TCG_TARGET_REG_BITS == 64) {
} else {
}
break;
case 'r':
if (TCG_TARGET_REG_BITS == 64) {
} else {
}
break;
case 'L':
if (TCG_TARGET_REG_BITS == 64) {
#if defined(VBOX) && defined(__MINGW64__)
#else
/** @todo figure why RDX isn't mentioned here. */
#endif
} else {
}
break;
case 'e':
break;
case 'Z':
break;
default:
return -1;
}
ct_str++;
return 0;
}
/* test if a constant matches the constraint */
const TCGArgConstraint *arg_ct)
{
if (ct & TCG_CT_CONST) {
return 1;
}
return 1;
}
return 1;
}
return 0;
}
#if TCG_TARGET_REG_BITS == 64
# define LOWREGMASK(x) ((x) & 7)
#else
# define LOWREGMASK(x) (x)
#endif
#if TCG_TARGET_REG_BITS == 64
#else
# define P_ADDR32 0
# define P_REXW 0
# define P_REXB_R 0
# define P_REXB_RM 0
#endif
#define OPC_ARITH_EvIz (0x81)
#define OPC_ARITH_EvIb (0x83)
#define OPC_CALL_Jz (0xe8)
#define OPC_DEC_r32 (0x48)
#define OPC_IMUL_GvEvIb (0x6b)
#define OPC_IMUL_GvEvIz (0x69)
#define OPC_INC_r32 (0x40)
#define OPC_JMP_long (0xe9)
#define OPC_JMP_short (0xeb)
#define OPC_LEA (0x8d)
#define OPC_MOVL_EvIz (0xc7)
#define OPC_MOVL_Iv (0xb8)
#define OPC_POP_r32 (0x58)
#define OPC_PUSH_r32 (0x50)
#define OPC_PUSH_Iv (0x68)
#define OPC_PUSH_Ib (0x6a)
#define OPC_RET (0xc3)
#define OPC_SHIFT_1 (0xd1)
#define OPC_SHIFT_Ib (0xc1)
#define OPC_SHIFT_cl (0xd3)
#define OPC_TESTL (0x85)
#define OPC_XCHG_ax_r32 (0x90)
#define OPC_GRP3_Ev (0xf7)
#define OPC_GRP5 (0xff)
/* Group 1 opcode extensions for 0x80-0x83.
These are also used as modifiers for OPC_ARITH. */
#define ARITH_ADD 0
#define ARITH_OR 1
#define ARITH_ADC 2
#define ARITH_SBB 3
#define ARITH_AND 4
#define ARITH_SUB 5
#define ARITH_XOR 6
#define ARITH_CMP 7
/* Group 2 opcode extensions for 0xc0, 0xc1, 0xd0-0xd3. */
#define SHIFT_ROL 0
#define SHIFT_ROR 1
#define SHIFT_SHL 4
#define SHIFT_SHR 5
#define SHIFT_SAR 7
/* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */
#define EXT3_NOT 2
#define EXT3_NEG 3
#define EXT3_MUL 4
#define EXT3_IMUL 5
#define EXT3_DIV 6
#define EXT3_IDIV 7
/* Group 5 opcode extensions for 0xff. To be used with OPC_GRP5. */
#define EXT5_INC_Ev 0
#define EXT5_DEC_Ev 1
#define EXT5_CALLN_Ev 2
#define EXT5_JMPN_Ev 4
/* Condition codes to be added to OPC_JCC_{long,short}. */
#define JCC_JMP (-1)
#define JCC_JO 0x0
#define JCC_JNO 0x1
#define JCC_JB 0x2
#define JCC_JAE 0x3
#define JCC_JE 0x4
#define JCC_JNE 0x5
#define JCC_JBE 0x6
#define JCC_JA 0x7
#define JCC_JS 0x8
#define JCC_JNS 0x9
#define JCC_JP 0xa
#define JCC_JNP 0xb
#define JCC_JL 0xc
#define JCC_JGE 0xd
#define JCC_JLE 0xe
#define JCC_JG 0xf
[TCG_COND_EQ] = JCC_JE,
[TCG_COND_NE] = JCC_JNE,
[TCG_COND_LT] = JCC_JL,
[TCG_COND_GE] = JCC_JGE,
[TCG_COND_LE] = JCC_JLE,
[TCG_COND_GT] = JCC_JG,
[TCG_COND_LTU] = JCC_JB,
[TCG_COND_GEU] = JCC_JAE,
[TCG_COND_LEU] = JCC_JBE,
[TCG_COND_GTU] = JCC_JA,
};
#if defined(VBOX)
/* Calc the size of the tcg_out_opc() result. */
{
unsigned char len = 1;
# if TCG_TARGET_REG_BITS == 64
unsigned rex;
rex = 0;
# endif
return len;
}
#endif
#if TCG_TARGET_REG_BITS == 64
{
int rex;
/* We should never be asking for both 16 and 64-bit operation. */
tcg_out8(s, 0x66);
}
tcg_out8(s, 0x67);
}
rex = 0;
/* P_REXB_{R,RM} indicates that the given register is the low byte.
For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do,
as otherwise the encoding indicates %[abcd]h. Note that the values
that are ORed in merely indicate that the REX byte must be present;
those bits get discarded in output. */
if (rex) {
}
tcg_out8(s, 0x0f);
}
}
#else
{
tcg_out8(s, 0x66);
}
tcg_out8(s, 0x0f);
}
}
/* Discard the register arguments to tcg_out_opc early, so as not to penalize
the 32-bit compilation paths. This method works with all versions of gcc,
whereas relying on optimization may not be able to exclude them. */
#endif
{
}
/* Output an opcode with a full "rm + (index<<shift) + offset" address mode.
We handle either RM and INDEX missing with a negative value. In 64-bit
mode for absolute addresses, ~RM is the size of the immediate operand
that will follow the instruction. */
{
if (TCG_TARGET_REG_BITS == 64) {
/* Try for a rip-relative addressing mode. This has replaced
the 32-bit-mode absolute addressing encoding. */
#ifdef VBOX
#else
#endif
tcg_out_opc(s, opc, r, 0, 0);
#ifdef VBOX
#endif
return;
}
/* Try for an absolute address encoding. This requires the
use of the MODRM+SIB encoding and is therefore larger than
rip-relative addressing. */
tcg_out_opc(s, opc, r, 0, 0);
return;
}
/* ??? The memory isn't directly addressable. */
tcg_abort();
} else {
/* Absolute address. */
tcg_out_opc(s, opc, r, 0, 0);
return;
}
}
/* Find the length of the immediate addend. Note that the encoding
that would be used for (%ebp) indicates absolute addressing. */
if (rm < 0) {
} else {
}
/* Use a single byte MODRM format if possible. Note that the encoding
that would be used for %esp is the escape to the two byte form. */
/* Single byte MODRM format. */
} else {
/* Two byte MODRM+SIB format. */
/* Note that the encoding that would place %esp into the index
field indicates no index register. In 64-bit mode, the REX.X
bit counts, so %r12 can be used as the index. */
if (index < 0) {
index = 4;
} else {
}
}
if (len == 1) {
} else if (len == 4) {
}
}
/* A simplification of the above with no index or shift. */
{
}
/* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */
{
/* Propagate an opcode prefix, such as P_REXW. */
subop &= 0x7;
}
{
}
}
{
if (arg == 0) {
return;
} else {
}
}
{
tcg_out_opc(s, OPC_PUSH_Ib, 0, 0, 0);
tcg_out_opc(s, OPC_PUSH_Iv, 0, 0, 0);
} else {
tcg_abort();
}
}
{
}
{
}
{
}
{
}
{
/* Propagate an opcode prefix, such as P_DATA16. */
subopc &= 0x7;
if (count == 1) {
} else {
}
}
{
}
{
}
{
/* movzbl */
}
{
/* movsbl */
}
{
/* movzwl */
}
{
/* movsw[lq] */
}
{
/* 32-bit mov zero extends. */
}
{
}
{
}
{
int rexw = 0;
if (TCG_TARGET_REG_BITS == 64) {
rexw = c & -8;
c &= 7;
}
/* ??? While INC is 2 bytes shorter than ADDL $1, they also induce
partial flags update stalls on Pentium4 and are not recommended
by current Intel optimization manuals. */
if (TCG_TARGET_REG_BITS == 64) {
/* The single-byte increment encodings are re-tasked as the
REX prefixes. Use the MODRM encoding. */
} else {
}
return;
}
if (c == ARITH_AND) {
if (TCG_TARGET_REG_BITS == 64) {
if (val == 0xffffffffu) {
return;
}
/* AND with no high bits set can use a 32-bit operation. */
rexw = 0;
}
}
return;
}
if (val == 0xffffu) {
return;
}
}
return;
}
return;
}
tcg_abort();
}
{
if (val != 0) {
}
}
#ifdef VBOX_16_BYTE_STACK_ALIGN
{
if (val != 0) {
}
}
#endif
/* Use SMALL != 0 to force a short forward branch. */
{
if (l->has_value) {
if (opc == -1) {
tcg_out8(s, OPC_JMP_short);
} else {
}
} else {
if (small) {
tcg_abort();
}
if (opc == -1) {
tcg_out8(s, OPC_JMP_long);
} else {
}
}
} else if (small) {
if (opc == -1) {
tcg_out8(s, OPC_JMP_short);
} else {
}
s->code_ptr += 1;
} else {
if (opc == -1) {
tcg_out8(s, OPC_JMP_long);
} else {
}
s->code_ptr += 4;
}
}
int const_arg2, int rexw)
{
if (const_arg2) {
if (arg2 == 0) {
/* test r, r */
} else {
}
} else {
}
}
int label_index, int small)
{
}
#if TCG_TARGET_REG_BITS == 64
int label_index, int small)
{
}
#else
/* XXX: we implement it at the target level to avoid having to
handle cross basic blocks temporaries */
const int *const_args, int small)
{
int label_next;
label_next = gen_new_label();
switch(args[4]) {
case TCG_COND_EQ:
label_next, 1);
break;
case TCG_COND_NE:
break;
case TCG_COND_LT:
break;
case TCG_COND_LE:
break;
case TCG_COND_GT:
break;
case TCG_COND_GE:
break;
case TCG_COND_LTU:
break;
case TCG_COND_LEU:
break;
case TCG_COND_GTU:
break;
case TCG_COND_GEU:
break;
default:
tcg_abort();
}
}
#endif
{
}
#if TCG_TARGET_REG_BITS == 64
{
}
#else
const int *const_args)
{
int label_true, label_over;
/* When the destination overlaps with one of the argument
registers, don't do anything tricky. */
label_true = gen_new_label();
label_over = gen_new_label();
} else {
/* When the destination does not overlap one of the arguments,
clear the destination first, jump if cond false, and emit an
increment in the true case. This results in smaller code. */
label_over = gen_new_label();
}
}
#endif
{
#ifdef VBOX
- 4;
#else
#endif
} else {
}
}
{
#ifdef VBOX
#endif
}
{
tcg_out_branch(s, 0, dest);
}
#if defined(CONFIG_SOFTMMU)
#include "../../softmmu_defs.h"
static void *qemu_ld_helpers[4] = {
};
static void *qemu_st_helpers[4] = {
};
/* Perform the TLB load and compare.
Inputs:
ADDRLO_IDX contains the index into ARGS of the low part of the
address; the high part of the address is at ADDR_LOW_IDX+1.
MEM_INDEX and S_BITS are the memory context and log2 size of the load.
WHICH is the offset into the CPUTLBEntry structure of the slot to read.
This should be offsetof addr_read or addr_write.
Outputs:
LABEL_PTRS is filled with 1 (32-bit addresses) or 2 (64-bit addresses)
positions of the displacements of forward jumps to the TLB miss case.
First argument register is loaded with the low part of the address.
In the TLB hit case, it has been adjusted as indicated by the TLB
and so is a host address. In the TLB miss case, it continues to
hold a guest address.
Second argument register is clobbered. */
{
const int r0 = tcg_target_call_iarg_regs[0];
int rexw = 0;
type = TCG_TYPE_I64;
}
+ which);
/* cmp 0(r1), r0 */
/* jne label1 */
s->code_ptr++;
if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
/* cmp 4(r1), addrhi */
/* jne label1 */
s->code_ptr++;
}
/* TLB Hit. */
/* add addend(r1), r0 */
}
#endif
{
#ifdef TARGET_WORDS_BIGENDIAN
const int bswap = 1;
#else
const int bswap = 0;
#endif
switch (sizeop) {
case 0:
break;
case 0 | 4:
break;
case 1:
if (bswap) {
tcg_out_rolw_8(s, datalo);
}
break;
case 1 | 4:
if (bswap) {
tcg_out_rolw_8(s, datalo);
} else {
}
break;
case 2:
if (bswap) {
tcg_out_bswap32(s, datalo);
}
break;
#if TCG_TARGET_REG_BITS == 64
case 2 | 4:
if (bswap) {
tcg_out_bswap32(s, datalo);
} else {
}
break;
#endif
case 3:
if (TCG_TARGET_REG_BITS == 64) {
if (bswap) {
tcg_out_bswap64(s, datalo);
}
} else {
if (bswap) {
int t = datalo;
datahi = t;
}
} else {
}
if (bswap) {
tcg_out_bswap32(s, datalo);
tcg_out_bswap32(s, datahi);
}
}
break;
default:
tcg_abort();
}
}
#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
static void * const vbox_ld_helpers[] = {
};
static void * const vbox_st_helpers[] = {
};
{
# ifdef VBOX
# endif
}
int addr_reg,
{
/** @todo: should we make phys address accessors fastcalls - probably not a big deal */
/* out parameter (address), note that phys address is always 64-bit */
# if 0
tcg_out_push(s, addr_reg);
# else
/* mov addr_reg, %eax */
# endif
/* mov %eax, data_reg */
/* returned 64-bit value */
if (useReg2)
}
int addr_reg,
# if 0
/* out parameter (value2) */
if (useReg2)
tcg_out_push(s, val_reg2);
/* out parameter (value) */
tcg_out_push(s, val_reg);
/* out parameter (address), note that phys address is always 64-bit */
tcg_out_push(s, addr_reg);
# else
/* mov addr_reg, %eax */
/* mov val_reg, %edx */
if (useReg2)
# endif
/* call it */
/* clean stack after us */
# if 0
# endif
}
#endif /* defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB) */
/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
EAX. It will be useful once fixed registers globals are less
common. */
int opc)
{
int addrlo_idx;
#if defined(CONFIG_SOFTMMU)
#endif
addrlo_idx = 1;
addrlo_idx = 2;
}
#if defined(CONFIG_SOFTMMU)
/* TLB Hit. */
tcg_target_call_iarg_regs[0], 0, opc);
/* jmp label2 */
tcg_out8(s, OPC_JMP_short);
s->code_ptr++;
/* TLB Miss. */
/* label1: */
if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
}
/* XXX: move that code at the end of the TB */
/* The first argument is already loaded with addrlo. */
arg_idx = 1;
}
switch(opc) {
case 0 | 4:
break;
case 1 | 4:
break;
case 0:
break;
case 1:
break;
case 2:
break;
#if TCG_TARGET_REG_BITS == 64
case 2 | 4:
break;
#endif
case 3:
if (TCG_TARGET_REG_BITS == 64) {
} else if (data_reg == TCG_REG_EDX) {
/* xchg %edx, %eax */
} else {
}
break;
default:
tcg_abort();
}
/* label2: */
#else
# if defined(VBOX) && defined(__MINGW64__)
# endif
{
if (TCG_TARGET_REG_BITS == 64) {
/* ??? We assume all operations have left us with register
contents that are zero extended. So far this appears to
be true. If we want to enforce this, we can either do
an explicit zero-extension here, or (if GUEST_BASE == 0)
use the ADDR32 prefix. For now, do nothing. */
if (offset != GUEST_BASE) {
}
}
}
#endif
}
{
#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
#ifdef TARGET_WORDS_BIGENDIAN
const int bswap = 1;
#else
const int bswap = 0;
#endif
/* ??? Ideally we wouldn't need a scratch register. For user-only,
we could perform the bswap twice to restore the original value
instead of moving to the scratch. But as it is, the L constraint
means that the second argument reg is definitely free here. */
switch (sizeop) {
case 0:
break;
case 1:
if (bswap) {
tcg_out_rolw_8(s, scratch);
}
break;
case 2:
if (bswap) {
tcg_out_bswap32(s, scratch);
}
break;
case 3:
if (TCG_TARGET_REG_BITS == 64) {
if (bswap) {
tcg_out_bswap64(s, scratch);
}
} else if (bswap) {
tcg_out_bswap32(s, scratch);
tcg_out_bswap32(s, scratch);
} else {
}
break;
default:
tcg_abort();
}
#else /* VBOX */
# error "broken"
#endif
}
int opc)
{
int addrlo_idx;
#if defined(CONFIG_SOFTMMU)
int stack_adjust;
#endif
addrlo_idx = 1;
addrlo_idx = 2;
}
#if defined(CONFIG_SOFTMMU)
/* TLB Hit. */
tcg_target_call_iarg_regs[0], 0, opc);
/* jmp label2 */
tcg_out8(s, OPC_JMP_short);
s->code_ptr++;
/* TLB Miss. */
/* label1: */
if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
}
# if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
# define VBOX_16_BYTE_STACK_ALIGN
# endif
/* XXX: move that code at the end of the TB */
if (TCG_TARGET_REG_BITS == 64) {
# if defined(VBOX) && defined(__MINGW64__)
# else
# endif
stack_adjust = 0;
} else if (TARGET_LONG_BITS == 32) {
if (opc == 3) {
# ifdef VBOX_16_BYTE_STACK_ALIGN
# endif
tcg_out_pushi(s, mem_index);
stack_adjust = 4;
} else {
stack_adjust = 0;
}
} else {
if (opc == 3) {
# ifdef VBOX_16_BYTE_STACK_ALIGN
tcg_out_pushi(s, 0);
# endif
tcg_out_pushi(s, mem_index);
tcg_out_push(s, data_reg2);
tcg_out_push(s, data_reg);
stack_adjust = 12;
} else {
switch(opc) {
case 0:
break;
case 1:
break;
case 2:
break;
}
# ifdef VBOX_16_BYTE_STACK_ALIGN
# endif
tcg_out_pushi(s, mem_index);
stack_adjust = 4;
}
}
# ifdef VBOX_16_BYTE_STACK_ALIGN
if (stack_adjust != 0) {
}
# else
/* Pop and discard. This is 2 bytes smaller than the add. */
tcg_out_pop(s, TCG_REG_ECX);
} else if (stack_adjust != 0) {
}
# endif
# else /* VBOX && REM_PHYS_ADDR_IN_TLB */
# endif /* VBOX && REM_PHYS_ADDR_IN_TLB */
/* label2: */
#else
# if defined(VBOX) && defined(__MINGW64__)
# endif
{
if (TCG_TARGET_REG_BITS == 64) {
/* ??? We assume all operations have left us with register
contents that are zero extended. So far this appears to
be true. If we want to enforce this, we can either do
an explicit zero-extension here, or (if GUEST_BASE == 0)
use the ADDR32 prefix. For now, do nothing. */
if (offset != GUEST_BASE) {
}
}
}
#endif
}
{
int c, rexw = 0;
#if TCG_TARGET_REG_BITS == 64
# define OP_32_64(x) \
#else
# define OP_32_64(x) \
#endif
switch(opc) {
case INDEX_op_exit_tb:
break;
case INDEX_op_goto_tb:
if (s->tb_jmp_offset) {
/* direct jump method */
tcg_out32(s, 0);
} else {
/* indirect jump method */
}
break;
case INDEX_op_call:
if (const_args[0]) {
tcg_out_calli(s, args[0]);
} else {
/* call *reg */
}
break;
case INDEX_op_jmp:
if (const_args[0]) {
tcg_out_jmp(s, args[0]);
} else {
/* jmp *reg */
}
break;
case INDEX_op_br:
break;
case INDEX_op_movi_i32:
break;
/* Note that we can ignore REXW for the zero-extend to 64-bit. */
break;
break;
/* Note that we can ignore REXW for the zero-extend to 64-bit. */
break;
break;
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_ld32u_i64:
#endif
case INDEX_op_ld_i32:
break;
break;
break;
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_st32_i64:
#endif
case INDEX_op_st_i32:
break;
/* For 3-operand addition, use LEA. */
if (const_args[2]) {
/* Watch out for dest = src + dest, since we've removed
the matching constraint on the add. */
break;
}
break;
}
c = ARITH_ADD;
goto gen_arith;
c = ARITH_SUB;
goto gen_arith;
c = ARITH_AND;
goto gen_arith;
c = ARITH_OR;
goto gen_arith;
c = ARITH_XOR;
goto gen_arith;
if (const_args[2]) {
} else {
}
break;
if (const_args[2]) {
} else {
}
} else {
}
break;
break;
break;
c = SHIFT_SHL;
goto gen_shift;
c = SHIFT_SHR;
goto gen_shift;
c = SHIFT_SAR;
goto gen_shift;
c = SHIFT_ROL;
goto gen_shift;
c = SHIFT_ROR;
goto gen_shift;
if (const_args[2]) {
} else {
}
break;
case INDEX_op_brcond_i32:
args[3], 0);
break;
case INDEX_op_setcond_i32:
break;
tcg_out_rolw_8(s, args[0]);
break;
tcg_out_bswap32(s, args[0]);
break;
break;
break;
break;
break;
break;
break;
case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0);
break;
case INDEX_op_qemu_ld8s:
break;
case INDEX_op_qemu_ld16u:
break;
case INDEX_op_qemu_ld16s:
break;
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_qemu_ld32u:
#endif
case INDEX_op_qemu_ld32:
break;
case INDEX_op_qemu_ld64:
break;
case INDEX_op_qemu_st8:
tcg_out_qemu_st(s, args, 0);
break;
case INDEX_op_qemu_st16:
break;
case INDEX_op_qemu_st32:
break;
case INDEX_op_qemu_st64:
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_brcond2_i32:
break;
case INDEX_op_setcond2_i32:
break;
case INDEX_op_mulu2_i32:
break;
case INDEX_op_add2_i32:
if (const_args[4]) {
} else {
}
if (const_args[5]) {
} else {
}
break;
case INDEX_op_sub2_i32:
if (const_args[4]) {
} else {
}
if (const_args[5]) {
} else {
}
break;
#else /* TCG_TARGET_REG_BITS == 64 */
case INDEX_op_movi_i64:
break;
case INDEX_op_ld32s_i64:
break;
case INDEX_op_ld_i64:
break;
case INDEX_op_st_i64:
break;
case INDEX_op_qemu_ld32s:
break;
case INDEX_op_brcond_i64:
args[3], 0);
break;
case INDEX_op_setcond_i64:
break;
case INDEX_op_bswap64_i64:
tcg_out_bswap64(s, args[0]);
break;
case INDEX_op_ext32u_i64:
break;
case INDEX_op_ext32s_i64:
break;
#endif
default:
tcg_abort();
}
}
static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_exit_tb, { } },
{ INDEX_op_goto_tb, { } },
{ INDEX_op_call, { "ri" } },
{ INDEX_op_jmp, { "ri" } },
{ INDEX_op_br, { } },
{ INDEX_op_movi_i32, { "r" } },
#if TCG_TARGET_REG_BITS == 32
#else
{ INDEX_op_movi_i64, { "r" } },
#endif
#if TCG_TARGET_REG_BITS == 64
#else
#endif
{ -1 },
};
static int tcg_target_callee_save_regs[] = {
#if TCG_TARGET_REG_BITS == 64
# if defined(VBOX) && defined(__MINGW64__)
# endif
/* TCG_REG_R14, */ /* Currently used for the global env. */
#else
# ifndef VBOX
/* TCG_REG_EBP, */ /* Currently used for the global env. */
# else
/* TCG_REG_ESI, */ /* Currently used for the global env. */
# endif
#endif
};
/* Generate global QEMU prologue and epilogue code */
static void tcg_target_qemu_prologue(TCGContext *s)
{
/* TB prologue */
/* Save all callee saved registers. */
for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
}
# if defined(VBOX_STRICT) && defined(RT_ARCH_X86)
tcg_out8(s, 0xed);
# endif
/* Reserve some stack space. */
#if defined(VBOX) && defined(__MINGW64__)
#endif
~(TCG_TARGET_STACK_ALIGN - 1);
/* jmp *tb. */
# ifdef VBOX
# endif
/* TB epilogue */
tb_ret_addr = s->code_ptr;
}
tcg_out_opc(s, OPC_RET, 0, 0, 0);
}
static void tcg_target_init(TCGContext *s)
{
#if !defined(CONFIG_USER_ONLY)
/* fail safe */
tcg_abort();
#endif
if (TCG_TARGET_REG_BITS == 64) {
} else {
}
if (TCG_TARGET_REG_BITS == 64) {
# if !defined(VBOX) || !defined(__MINGW64__)
# endif
}
}