tcg-target.c revision 178d85b8274f9ac82fb553c80760bbbb4044401c
/*
* Tiny Code Generator for QEMU
*
* Copyright (c) 2008 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef NDEBUG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"%eax",
"%ecx",
"%edx",
"%ebx",
"%esp",
"%ebp",
"%esi",
"%edi",
};
#endif
static const int tcg_target_reg_alloc_order[] = {
};
static uint8_t *tb_ret_addr;
{
switch(type) {
case R_386_32:
break;
case R_386_PC32:
break;
default:
tcg_abort();
}
}
#ifdef VBOX
/* emits stack alignment checks for strict builds. */
{
# else
NOREF(s);
# endif
}
#endif /* VBOX */
/* maximum number of register used for input function arguments */
static inline int tcg_target_get_call_iarg_regs_count(int flags)
{
switch(flags) {
case TCG_CALL_TYPE_STD:
return 0;
case TCG_CALL_TYPE_REGPARM_1:
case TCG_CALL_TYPE_REGPARM_2:
case TCG_CALL_TYPE_REGPARM:
default:
tcg_abort();
}
}
/* parse target specific constraints */
{
const char *ct_str;
switch(ct_str[0]) {
case 'a':
break;
case 'b':
break;
case 'c':
break;
case 'd':
break;
case 'S':
break;
case 'D':
break;
case 'q':
break;
case 'r':
break;
case 'L':
break;
default:
return -1;
}
ct_str++;
return 0;
}
/* test if a constant matches the constraint */
const TCGArgConstraint *arg_ct)
{
int ct;
if (ct & TCG_CT_CONST)
return 1;
else
return 0;
}
#define ARITH_ADD 0
#define ARITH_OR 1
#define ARITH_ADC 2
#define ARITH_SBB 3
#define ARITH_AND 4
#define ARITH_SUB 5
#define ARITH_XOR 6
#define ARITH_CMP 7
#define SHIFT_SHL 4
#define SHIFT_SHR 5
#define SHIFT_SAR 7
#define JCC_JMP (-1)
#define JCC_JO 0x0
#define JCC_JNO 0x1
#define JCC_JB 0x2
#define JCC_JAE 0x3
#define JCC_JE 0x4
#define JCC_JNE 0x5
#define JCC_JBE 0x6
#define JCC_JA 0x7
#define JCC_JS 0x8
#define JCC_JNS 0x9
#define JCC_JP 0xa
#define JCC_JNP 0xb
#define JCC_JL 0xc
#define JCC_JGE 0xd
#define JCC_JLE 0xe
#define JCC_JG 0xf
[TCG_COND_EQ] = JCC_JE,
[TCG_COND_NE] = JCC_JNE,
[TCG_COND_LT] = JCC_JL,
[TCG_COND_GE] = JCC_JGE,
[TCG_COND_LE] = JCC_JLE,
[TCG_COND_GT] = JCC_JG,
[TCG_COND_LTU] = JCC_JB,
[TCG_COND_GEU] = JCC_JAE,
[TCG_COND_LEU] = JCC_JBE,
[TCG_COND_GTU] = JCC_JA,
};
{
tcg_out8(s, 0x0f);
}
{
tcg_out_opc(s, opc);
}
/* rm == -1 means no register index */
{
tcg_out_opc(s, opc);
if (rm == -1) {
if (rm == TCG_REG_ESP) {
tcg_out8(s, 0x24);
} else {
}
if (rm == TCG_REG_ESP) {
tcg_out8(s, 0x24);
} else {
}
} else {
if (rm == TCG_REG_ESP) {
tcg_out8(s, 0x24);
} else {
}
}
}
{
}
{
if (arg == 0) {
/* xor r0,r0 */
} else {
}
}
{
/* movl */
}
{
/* movl */
}
{
} else {
}
}
{
if (val != 0)
}
#ifdef VBOX
{
if (val != 0)
}
#endif
{
if (l->has_value) {
if (opc == -1)
tcg_out8(s, 0xeb);
else
} else {
if (opc == -1) {
tcg_out8(s, 0xe9);
} else {
tcg_out8(s, 0x0f);
}
}
} else {
if (opc == -1) {
tcg_out8(s, 0xe9);
} else {
tcg_out8(s, 0x0f);
}
s->code_ptr += 4;
}
}
int label_index)
{
if (const_arg2) {
if (arg2 == 0) {
/* test r, r */
} else {
}
} else {
}
}
#ifdef VBOX
{
# ifdef VBOX
# endif
}
{
}
#endif /* VBOX */
/* XXX: we implement it at the target level to avoid having to
handle cross basic blocks temporaries */
static void tcg_out_brcond2(TCGContext *s,
{
int label_next;
label_next = gen_new_label();
switch(args[4]) {
case TCG_COND_EQ:
break;
case TCG_COND_NE:
break;
case TCG_COND_LT:
break;
case TCG_COND_LE:
break;
case TCG_COND_GT:
break;
case TCG_COND_GE:
break;
case TCG_COND_LTU:
break;
case TCG_COND_LEU:
break;
case TCG_COND_GTU:
break;
case TCG_COND_GEU:
break;
default:
tcg_abort();
}
}
#if defined(CONFIG_SOFTMMU)
#include "../../softmmu_defs.h"
static void *qemu_ld_helpers[4] = {
};
static void *qemu_st_helpers[4] = {
};
#endif
#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
static void *vbox_ld_helpers[] = {
};
static void *vbox_st_helpers[] = {
};
int addr_reg,
{
/** @todo: should we make phys address accessors fastcalls - probably not a big deal */
/* out parameter (address), note that phys address is always 64-bit */
#if 0
tcg_out_push(s, addr_reg);
#else
/* mov addr_reg, %eax */
#endif
/* mov %eax, data_reg */
/* returned 64-bit value */
if (useReg2)
}
int addr_reg,
#if 0
/* out parameter (value2) */
if (useReg2)
tcg_out_push(s, val_reg2);
/* out parameter (value) */
tcg_out_push(s, val_reg);
/* out parameter (address), note that phys address is always 64-bit */
tcg_out_push(s, addr_reg);
#else
/* mov addr_reg, %eax */
/* mov val_reg, %edx */
if (useReg2)
#endif
/* call it */
/* clean stack after us */
#if 0
# endif
}
#endif /* defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB) */
/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
EAX. It will be useful once fixed registers globals are less
common. */
int opc)
{
#if defined(CONFIG_SOFTMMU)
#endif
#if TARGET_LONG_BITS == 64
#if defined(CONFIG_SOFTMMU)
#endif
int addr_reg2;
#endif
if (opc == 3)
else
data_reg2 = 0;
#if TARGET_LONG_BITS == 64
#endif
r0 = TCG_REG_EAX;
r1 = TCG_REG_EDX;
#if defined(CONFIG_SOFTMMU)
#ifndef VBOX
#else
#endif
/* cmp 0(r1), r0 */
#if TARGET_LONG_BITS == 32
/* je label1 */
label1_ptr = s->code_ptr;
s->code_ptr++;
#else
/* jne label3 */
label3_ptr = s->code_ptr;
s->code_ptr++;
/* cmp 4(r1), addr_reg2 */
/* je label1 */
label1_ptr = s->code_ptr;
s->code_ptr++;
/* label3: */
#endif
/* XXX: move that code at the end of the TB */
#if TARGET_LONG_BITS == 32
#else
#endif
#ifdef VBOX
#endif
tcg_out8(s, 0xe8);
switch(opc) {
case 0 | 4:
/* movsbl */
break;
case 1 | 4:
/* movswl */
break;
case 0:
case 1:
case 2:
default:
break;
case 3:
if (data_reg == TCG_REG_EDX) {
} else {
}
break;
}
/* jmp label2 */
tcg_out8(s, 0xeb);
label2_ptr = s->code_ptr;
s->code_ptr++;
/* label1: */
/* add x(r1), r0 */
#else
#endif
#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
#ifdef TARGET_WORDS_BIGENDIAN
bswap = 1;
#else
bswap = 0;
#endif
switch(opc) {
case 0:
/* movzbl */
break;
case 0 | 4:
/* movsbl */
break;
case 1:
/* movzwl */
if (bswap) {
/* rolw $8, data_reg */
tcg_out8(s, 0x66);
tcg_out8(s, 8);
}
break;
case 1 | 4:
/* movswl */
if (bswap) {
/* rolw $8, data_reg */
tcg_out8(s, 0x66);
tcg_out8(s, 8);
/* movswl data_reg, data_reg */
}
break;
case 2:
/* movl (r0), data_reg */
if (bswap) {
/* bswap */
}
break;
case 3:
/* XXX: could be nicer */
r1 = TCG_REG_EDX;
r1 = TCG_REG_EAX;
}
if (!bswap) {
} else {
/* bswap */
}
break;
default:
tcg_abort();
}
#else /* VBOX */
#endif
#if defined(CONFIG_SOFTMMU)
/* label2: */
# ifdef VBOX
# endif
#endif
}
int opc)
{
#if defined(CONFIG_SOFTMMU)
#endif
#if TARGET_LONG_BITS == 64
#if defined(CONFIG_SOFTMMU)
#endif
int addr_reg2;
#endif
#ifdef VBOX
# ifdef RT_OS_DARWIN
# else
# endif
#endif
if (opc == 3)
else
data_reg2 = 0;
#if TARGET_LONG_BITS == 64
#endif
r0 = TCG_REG_EAX;
r1 = TCG_REG_EDX;
#if defined(CONFIG_SOFTMMU)
#ifndef VBOX
#else
#endif
/* cmp 0(r1), r0 */
#if TARGET_LONG_BITS == 32
/* je label1 */
label1_ptr = s->code_ptr;
s->code_ptr++;
#else
/* jne label3 */
label3_ptr = s->code_ptr;
s->code_ptr++;
/* cmp 4(r1), addr_reg2 */
/* je label1 */
label1_ptr = s->code_ptr;
s->code_ptr++;
/* label3: */
#endif
/* XXX: move that code at the end of the TB */
#if TARGET_LONG_BITS == 32
if (opc == 3) {
#ifdef VBOX
#endif
# ifdef VBOX
# endif
tcg_out8(s, 0xe8);
#ifdef VBOX
#else
#endif
} else {
switch(opc) {
case 0:
/* movzbl */
break;
case 1:
/* movzwl */
break;
case 2:
break;
}
# ifdef VBOX
# endif
tcg_out8(s, 0xe8);
}
#else
if (opc == 3) {
# ifdef VBOX
# endif
# ifdef VBOX
# endif
tcg_out8(s, 0xe8);
#ifdef VBOX
#else
#endif
} else {
switch(opc) {
case 0:
/* movzbl */
break;
case 1:
/* movzwl */
break;
case 2:
break;
}
# ifdef VBOX
# endif
# ifdef VBOX
# endif
tcg_out8(s, 0xe8);
# if defined(VBOX)
# else
# endif
}
#endif
/* jmp label2 */
tcg_out8(s, 0xeb);
label2_ptr = s->code_ptr;
s->code_ptr++;
/* label1: */
/* add x(r1), r0 */
#else
#endif
#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
#ifdef TARGET_WORDS_BIGENDIAN
bswap = 1;
#else
bswap = 0;
#endif
switch(opc) {
case 0:
/* movb */
break;
case 1:
if (bswap) {
tcg_out8(s, 8);
}
/* movw */
tcg_out8(s, 0x66);
break;
case 2:
if (bswap) {
/* bswap data_reg */
}
/* movl */
break;
case 3:
if (bswap) {
/* bswap data_reg */
/* bswap data_reg */
} else {
}
break;
default:
tcg_abort();
}
#else /* VBOX && REM_PHYS_ADDR_IN_TLB */
#endif /* VBOX && REM_PHYS_ADDR_IN_TLB */
#if defined(CONFIG_SOFTMMU)
/* label2: */
# ifdef VBOX
# endif
#endif
}
{
int c;
switch(opc) {
case INDEX_op_exit_tb:
break;
case INDEX_op_goto_tb:
if (s->tb_jmp_offset) {
/* direct jump method */
tcg_out32(s, 0);
} else {
/* indirect jump method */
/* jmp Ev */
}
break;
case INDEX_op_call:
#ifdef VBOX
#endif
if (const_args[0]) {
tcg_out8(s, 0xe8);
} else {
}
break;
case INDEX_op_jmp:
if (const_args[0]) {
tcg_out8(s, 0xe9);
} else {
}
break;
case INDEX_op_br:
break;
case INDEX_op_movi_i32:
break;
case INDEX_op_ld8u_i32:
/* movzbl */
break;
case INDEX_op_ld8s_i32:
/* movsbl */
break;
case INDEX_op_ld16u_i32:
/* movzwl */
break;
case INDEX_op_ld16s_i32:
/* movswl */
break;
case INDEX_op_ld_i32:
/* movl */
break;
case INDEX_op_st8_i32:
/* movb */
break;
case INDEX_op_st16_i32:
/* movw */
tcg_out8(s, 0x66);
break;
case INDEX_op_st_i32:
/* movl */
break;
case INDEX_op_sub_i32:
c = ARITH_SUB;
goto gen_arith;
case INDEX_op_and_i32:
c = ARITH_AND;
goto gen_arith;
case INDEX_op_or_i32:
c = ARITH_OR;
goto gen_arith;
case INDEX_op_xor_i32:
c = ARITH_XOR;
goto gen_arith;
case INDEX_op_add_i32:
c = ARITH_ADD;
if (const_args[2]) {
} else {
}
break;
case INDEX_op_mul_i32:
if (const_args[2]) {
} else {
}
} else {
}
break;
case INDEX_op_mulu2_i32:
break;
case INDEX_op_div2_i32:
break;
case INDEX_op_divu2_i32:
break;
case INDEX_op_shl_i32:
c = SHIFT_SHL;
if (const_args[2]) {
} else {
}
} else {
}
break;
case INDEX_op_shr_i32:
c = SHIFT_SHR;
goto gen_shift32;
case INDEX_op_sar_i32:
c = SHIFT_SAR;
goto gen_shift32;
case INDEX_op_add2_i32:
if (const_args[4])
else
if (const_args[5])
else
break;
case INDEX_op_sub2_i32:
if (const_args[4])
else
if (const_args[5])
else
break;
case INDEX_op_brcond_i32:
break;
case INDEX_op_brcond2_i32:
break;
case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0);
break;
case INDEX_op_qemu_ld8s:
break;
case INDEX_op_qemu_ld16u:
break;
case INDEX_op_qemu_ld16s:
break;
case INDEX_op_qemu_ld32u:
break;
case INDEX_op_qemu_ld64:
break;
case INDEX_op_qemu_st8:
tcg_out_qemu_st(s, args, 0);
break;
case INDEX_op_qemu_st16:
break;
case INDEX_op_qemu_st32:
break;
case INDEX_op_qemu_st64:
break;
default:
tcg_abort();
}
}
static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_movi_i32, { "r" } },
#if TARGET_LONG_BITS == 32
#else
#endif
#ifndef VBOX
{ -1 },
#else
{ -1, {"", "", "", ""} },
#endif
};
static int tcg_target_callee_save_regs[] = {
#ifndef VBOX
/* TCG_REG_EBP, */ /* currently used for the global env, so no
need to save */
#else
/* TCG_REG_ESI, */ /* currently used for the global env, so no
need to save */
#endif
};
{
}
{
}
/* Generate global QEMU prologue and epilogue code */
void tcg_target_qemu_prologue(TCGContext *s)
{
/* TB prologue */
/* save all callee saved registers */
for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
}
/* reserve some stack space */
~(TCG_TARGET_STACK_ALIGN - 1);
# ifdef VBOX
# endif
/* TB epilogue */
tb_ret_addr = s->code_ptr;
}
}
void tcg_target_init(TCGContext *s)
{
/* fail safe */
tcg_abort();
(1 << TCG_REG_EAX) |
(1 << TCG_REG_EDX) |
(1 << TCG_REG_ECX));
}