helper2.c revision d65680efa46fa49e8bf14e67b29b782510ff934c
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * i386 helpers (without register variable usage)
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * Copyright (c) 2003 Fabrice Bellard
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * This library is free software; you can redistribute it and/or
f6b53aa7a361c1f26a3287a95172653219470233vboxsync * modify it under the terms of the GNU Lesser General Public
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * License as published by the Free Software Foundation; either
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * version 2 of the License, or (at your option) any later version.
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * This library is distributed in the hope that it will be useful,
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * but WITHOUT ANY WARRANTY; without even the implied warranty of
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * Lesser General Public License for more details.
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * You should have received a copy of the GNU Lesser General Public
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * License along with this library; if not, write to the Free Software
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * other than GPL or LGPL is available it will apply instead, Sun elects to use only
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * a choice of LGPL license versions is made available with the language indicating
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * that LGPLv2 or any later version may be used, or where a choice of which version
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync * of the LGPL is applied is otherwise unspecified.
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync//#define DEBUG_MMU
4328e87247f4a96449677e199c7e99ef516fc1cevboxsyncint modify_ldt(int func, void *ptr, unsigned long bytecount)
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync return syscall(__NR_modify_ldt, func, ptr, bytecount);
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync#endif /* USE_CODE_COPY */
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync#else /* !VBOX */
89aedeb1d8af54aba6ae46dbbd256281315c1be6vboxsync#endif /* !VBOX */
89aedeb1d8af54aba6ae46dbbd256281315c1be6vboxsync#endif /* !VBOX */
89aedeb1d8af54aba6ae46dbbd256281315c1be6vboxsync /* init various static tables */
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync /* testing code for code copy case */
508452243fd3328f7b9e0405d39fb9dc004e31b8vboxsync modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync asm volatile ("movl %0, %%fs" : : "r" ((1 << 3) | 7));
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync#ifndef VBOX /* cpuid_features is initialized by caller */
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync /* pentium 75-200 */
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync /* pentium pro */
6e12ccc60ac657fb87e27b7a2b26e0a63bebe024vboxsync env->cpuid_version = (family << 8) | (model << 4) | stepping;
6e12ccc60ac657fb87e27b7a2b26e0a63bebe024vboxsync env->cpuid_features = (CPUID_FP87 | CPUID_DE | CPUID_PSE |
6e12ccc60ac657fb87e27b7a2b26e0a63bebe024vboxsync env->cpuid_features |= CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | CPUID_PAE | CPUID_SEP;
6e12ccc60ac657fb87e27b7a2b26e0a63bebe024vboxsync const char *model_id = "QEMU Virtual CPU version " QEMU_VERSION;
6e12ccc60ac657fb87e27b7a2b26e0a63bebe024vboxsync for(i = 0; i < 48; i++) {
657b2c9f6d33f08001e5fa6f6e0572dcf0391013vboxsync /* currently not enabled for std i386 because not fully tested */
657b2c9f6d33f08001e5fa6f6e0572dcf0391013vboxsync env->cpuid_ext2_features = (env->cpuid_features & 0x0183F3FF);
657b2c9f6d33f08001e5fa6f6e0572dcf0391013vboxsync env->cpuid_ext2_features |= CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX;
657b2c9f6d33f08001e5fa6f6e0572dcf0391013vboxsync /* these features are needed for Win64 and aren't fully implemented */
657b2c9f6d33f08001e5fa6f6e0572dcf0391013vboxsync env->cpuid_features |= CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA;
657b2c9f6d33f08001e5fa6f6e0572dcf0391013vboxsync /* this feature is needed for Solaris and isn't fully implemented */
9cb702c3a5fd2287c57c7c1e98a61ba9e357b4devboxsync#endif /* VBOX */
6fe1329154975472e055284198df7fa8e64dee3avboxsync/* NOTE: must be called outside the CPU execute loop */
6fe1329154975472e055284198df7fa8e64dee3avboxsync memset(env, 0, offsetof(CPUX86State, breakpoints));
6fe1329154975472e055284198df7fa8e64dee3avboxsync /* init to reset state */
2a171646d32f8a15e9820d6fb3bf3f9b9990ca3fvboxsync cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 0);
2a171646d32f8a15e9820d6fb3bf3f9b9990ca3fvboxsync cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 0);
2a171646d32f8a15e9820d6fb3bf3f9b9990ca3fvboxsync cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 0);
2a171646d32f8a15e9820d6fb3bf3f9b9990ca3fvboxsync cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 0);
2a171646d32f8a15e9820d6fb3bf3f9b9990ca3fvboxsync cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 0);
2a171646d32f8a15e9820d6fb3bf3f9b9990ca3fvboxsync cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 0);
2a171646d32f8a15e9820d6fb3bf3f9b9990ca3fvboxsync env->regs[R_EDX] = 0x600; /* indicate P6 processor */
2a171646d32f8a15e9820d6fb3bf3f9b9990ca3fvboxsync /* FPU init */
069b9101fbd3b049610c5511b1cc9534d01ea472vboxsync for(i = 0;i < 8; i++)
2a171646d32f8a15e9820d6fb3bf3f9b9990ca3fvboxsync/***********************************************************/
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync/* x86 debug */
4328e87247f4a96449677e199c7e99ef516fc1cevboxsyncstatic const char *cc_op_str[] = {
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
29d55b79593710186ceda5a557fdab1727972175vboxsync "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
29d55b79593710186ceda5a557fdab1727972175vboxsync "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
29d55b79593710186ceda5a557fdab1727972175vboxsync "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
29d55b79593710186ceda5a557fdab1727972175vboxsync "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync cpu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync for(i = 0; i < 6; i++) {
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync cpu_fprintf(f, "%s =%04x %016" PRIx64 " %08x %08x\n",
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync cpu_fprintf(f, "LDT=%04x %016" PRIx64 " %08x %08x\n",
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync cpu_fprintf(f, "TR =%04x %016" PRIx64 " %08x %08x\n",
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync cpu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync for(i = 0; i < 6; i++) {
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync cpu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync qemu_snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync qemu_snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync cpu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
89aedeb1d8af54aba6ae46dbbd256281315c1be6vboxsync for(i = 0; i < 8; i++) {
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync cpu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync for(i=0;i<8;i++) {
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync long double d;
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync for(i=0;i<nb;i++) {
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync/***********************************************************/
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync/* x86 mmu */
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync/* XXX: add PGE support */
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsyncvoid cpu_x86_set_a20(CPUX86State *env, int a20_state)
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync /* if the cpu is currently executing code, we must unlink it and
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync all the potentially executing TB */
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync /* when a20 is changed, all the MMU mappings are invalid, so
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync we must flush everything */
1cd59fdf671ca60c64d77e3f7046aaecf7003824vboxsyncvoid cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
4f3d37f3c8ea851c3d57304fac430764b77a84dcvboxsync (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync /* enter in long mode */
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync /* XXX: generate an exception */
8ccde4f32d77b1ad3f02111f28a48ee85abf6779vboxsync } else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) &&
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync /* exit long mode */
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync /* update PE flag in hidden flags */
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync /* ensure that ADDSEG is always set in real mode */
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync /* update FPU flags */
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync ((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync/* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync the PDPT */
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsyncvoid cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
8ccde4f32d77b1ad3f02111f28a48ee85abf6779vboxsyncvoid cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync printf("CR4 update: CR4=%08x\n", (uint32_t)env->cr[4]);
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync if ((new_cr4 & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK)) !=
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync (env->cr[4] & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK))) {
b4bcdbd7ac35c938e6f71a6403fe9f3ebf106a07vboxsync /* SSE handling */
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsync/* XXX: also flush 4MB pages */
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsyncvoid cpu_x86_flush_tlb(CPUX86State *env, target_ulong addr)
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsync /* page directory entry */
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsync pde = remR3PhysReadU32(((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & env->a20_mask);
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsync /* if PSE bit is set, then we use a 4MB page */
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsync if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsyncint cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsync /* user mode only emulation */
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsynctarget_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsync/* return value:
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsync -1 = cannot handle fault
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsync 0 = nothing more to do
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsync 1 = generate PF fault
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsync 2 = soft MMU activation required for this block
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsyncint cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
a38afdea3cc827dc5964b4ba39a5cae6dbae23bdvboxsync int error_code, is_dirty, prot, page_size, ret, is_write;
a38afdea3cc827dc5964b4ba39a5cae6dbae23bdvboxsync printf("MMU fault: addr=" TARGET_FMT_lx " w=%d u=%d eip=" TARGET_FMT_lx "\n",
a38afdea3cc827dc5964b4ba39a5cae6dbae23bdvboxsync /* XXX: we only use 32 bit physical addresses */
a38afdea3cc827dc5964b4ba39a5cae6dbae23bdvboxsync /* test virtual address sign extension */
a38afdea3cc827dc5964b4ba39a5cae6dbae23bdvboxsync pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
a38afdea3cc827dc5964b4ba39a5cae6dbae23bdvboxsync if (!(env->efer & MSR_EFER_NXE) && (pml4e & PG_NX_MASK)) {
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync if (!(env->efer & MSR_EFER_NXE) && (pdpe & PG_NX_MASK)) {
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync /* XXX: load them when cr3 is loaded ? */
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync pde_addr = ((pdpe & PHYS_ADDR_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync if (!(env->efer & MSR_EFER_NXE) && (pde & PG_NX_MASK)) {
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync /* 2 MB page */
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync /* align to page_size */
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsync pte = pde & ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xfff);
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync /* 4 KB page */
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsync pte_addr = ((pde & PHYS_ADDR_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
aa0553becec2abc2e781f839ba1d399c31c2c07fvboxsync if (!(env->efer & MSR_EFER_NXE) && (pte & PG_NX_MASK)) {
4b9a9888c020ed3508c8ac3a5b47842d6aa3f8d2vboxsync /* combine pde and pte nx, user and rw protections */
f80ead6d4496030f4b89cfcbd3a1569c8f39f7cevboxsync /* page directory entry */
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync /* if PSE bit is set, then we use a 4MB page */
3933885bc0c2c93436d858a14564c6179ec72872vboxsync if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
3933885bc0c2c93436d858a14564c6179ec72872vboxsync pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
f80ead6d4496030f4b89cfcbd3a1569c8f39f7cevboxsync /* page directory entry */
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
36a04912b64bea8318327fe0723535f1b3f041b0vboxsync /* combine pde and pte user and rw protections */
3933885bc0c2c93436d858a14564c6179ec72872vboxsync /* the page can be put in the TLB */
3933885bc0c2c93436d858a14564c6179ec72872vboxsync /* only set write access if already dirty... otherwise wait
3933885bc0c2c93436d858a14564c6179ec72872vboxsync for dirty access */
060f7ec6ae5c99df18341ef2e1f3e91f4b0c89f1vboxsync /* Even if 4MB pages, we map only one 4KB page in the cache to
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync avoid filling it too fast */
060f7ec6ae5c99df18341ef2e1f3e91f4b0c89f1vboxsync page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
3933885bc0c2c93436d858a14564c6179ec72872vboxsynctarget_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
f80ead6d4496030f4b89cfcbd3a1569c8f39f7cevboxsync /* XXX: we only use 32 bit physical addresses */
3933885bc0c2c93436d858a14564c6179ec72872vboxsync /* test virtual address sign extension */
3933885bc0c2c93436d858a14564c6179ec72872vboxsync pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
3933885bc0c2c93436d858a14564c6179ec72872vboxsync pdpe_addr = ((pml4e & ~0xfff) + (((addr >> 30) & 0x1ff) << 3)) &
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
dcc837f3a6f10996beb8aa7965f67f7f6c273fb4vboxsync pde_addr = ((pdpe & ~0xfff) + (((addr >> 21) & 0x1ff) << 3)) &
dcc837f3a6f10996beb8aa7965f67f7f6c273fb4vboxsync /* 2 MB page */
dcc837f3a6f10996beb8aa7965f67f7f6c273fb4vboxsync pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
dcc837f3a6f10996beb8aa7965f67f7f6c273fb4vboxsync /* 4 KB page */
dcc837f3a6f10996beb8aa7965f67f7f6c273fb4vboxsync pte_addr = ((pde & ~0xfff) + (((addr >> 12) & 0x1ff) << 3)) &
501181107e73684ab109521ba371063734cd1d76vboxsync /* page directory entry */
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask;
c970e7d40b648d5c8f3e2b060692e670d85997d1vboxsync if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
c970e7d40b648d5c8f3e2b060692e670d85997d1vboxsync /* page directory entry */
1207f59aa62006952dbb0bf7700decf34d8caeb2vboxsync pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask;
1207f59aa62006952dbb0bf7700decf34d8caeb2vboxsync page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
501181107e73684ab109521ba371063734cd1d76vboxsync#endif /* !CONFIG_USER_ONLY */
28ae9ced88db55943497a8bb98682bc2be513476vboxsync fp->fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
28ae9ced88db55943497a8bb98682bc2be513476vboxsync for (i=7; i>=0; i--) {
28ae9ced88db55943497a8bb98682bc2be513476vboxsync /* the FPU automatically computes it */
28ae9ced88db55943497a8bb98682bc2be513476vboxsync for(i = 0;i < 8; i++) {
28ae9ced88db55943497a8bb98682bc2be513476vboxsync memcpy(&fp->fpregs1[i * 10], &env->fpregs[j].d, 10);
03a954338932c2b34361f1d27ae2029828db0958vboxsync for(i = 0;i < 8; i++) {
03a954338932c2b34361f1d27ae2029828db0958vboxsync for(i = 0;i < 8; i++) {
03a954338932c2b34361f1d27ae2029828db0958vboxsync memcpy(&env->fpregs[j].d, &fp->fpregs1[i * 10], 10);
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync /* we must restore the default rounding state */
4328e87247f4a96449677e199c7e99ef516fc1cevboxsync /* XXX: we do not restore the exception state */