cpu.h revision d65680efa46fa49e8bf14e67b29b782510ff934c
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/*
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * i386 virtual CPU header
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync *
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * Copyright (c) 2003 Fabrice Bellard
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync *
c7814cf6e1240a519cbec0441e033d0e2470ed00vboxsync * This library is free software; you can redistribute it and/or
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * modify it under the terms of the GNU Lesser General Public
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * License as published by the Free Software Foundation; either
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * version 2 of the License, or (at your option) any later version.
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync *
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * This library is distributed in the hope that it will be useful,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * but WITHOUT ANY WARRANTY; without even the implied warranty of
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * Lesser General Public License for more details.
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync *
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * You should have received a copy of the GNU Lesser General Public
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * License along with this library; if not, write to the Free Software
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/*
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * other than GPL or LGPL is available it will apply instead, Sun elects to use only
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * a choice of LGPL license versions is made available with the language indicating
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * that LGPLv2 or any later version may be used, or where a choice of which version
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * of the LGPL is applied is otherwise unspecified.
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#ifndef CPU_I386_H
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPU_I386_H
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#include "config.h"
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#ifdef TARGET_X86_64
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define TARGET_LONG_BITS 64
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#else
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define TARGET_LONG_BITS 32
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#endif
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* target supports implicit self modifying code */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define TARGET_HAS_SMC
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* support for self modifying code even if the modified instruction is
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync close to the modifying instruction */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define TARGET_HAS_PRECISE_SMC
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define TARGET_HAS_ICE 1
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#ifdef TARGET_X86_64
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define ELF_MACHINE EM_X86_64
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#else
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define ELF_MACHINE EM_386
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#endif
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#include "cpu-defs.h"
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#include "softfloat.h"
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#if defined(VBOX)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync# include <iprt/critsect.h>
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync# include <iprt/thread.h>
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync# include <iprt/assert.h>
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync# include <iprt/asm.h>
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync# include <VBox/vmm.h>
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#endif /* VBOX */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define USE_CODE_COPY
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#endif
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_EAX 0
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_ECX 1
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_EDX 2
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_EBX 3
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_ESP 4
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_EBP 5
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_ESI 6
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_EDI 7
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_AL 0
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_CL 1
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_DL 2
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_BL 3
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_AH 4
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_CH 5
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_DH 6
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_BH 7
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_ES 0
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_CS 1
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_SS 2
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_DS 3
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_FS 4
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define R_GS 5
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* segment descriptor fields */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_G_MASK (1 << 23)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_B_SHIFT 22
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_B_MASK (1 << DESC_B_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_L_MASK (1 << DESC_L_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_AVL_MASK (1 << 20)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_P_MASK (1 << 15)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_DPL_SHIFT 13
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_S_MASK (1 << 12)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_TYPE_SHIFT 8
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_A_MASK (1 << 8)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_C_MASK (1 << 10) /* code: conforming */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_R_MASK (1 << 9) /* code: readable */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_E_MASK (1 << 10) /* data: expansion direction */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_W_MASK (1 << 9) /* data: writable */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_TSS_BUSY_MASK (1 << 9)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* eflags masks */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CC_C 0x0001
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CC_P 0x0004
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CC_A 0x0010
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CC_Z 0x0040
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CC_S 0x0080
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CC_O 0x0800
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define TF_SHIFT 8
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define IOPL_SHIFT 12
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define VM_SHIFT 17
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define TF_MASK 0x00000100
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define IF_MASK 0x00000200
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DF_MASK 0x00000400
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define IOPL_MASK 0x00003000
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define NT_MASK 0x00004000
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define RF_MASK 0x00010000
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define VM_MASK 0x00020000
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define AC_MASK 0x00040000
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define VIF_MASK 0x00080000
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define VIP_MASK 0x00100000
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define ID_MASK 0x00200000
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* hidden flags - used internally by qemu to represent additionnal cpu
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync with eflags. */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* current cpl */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_CPL_SHIFT 0
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* true if soft mmu is being used */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_SOFTMMU_SHIFT 2
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* true if hardware interrupts must be disabled for next instruction */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_INHIBIT_IRQ_SHIFT 3
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* 16 or 32 segments */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_CS32_SHIFT 4
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_SS32_SHIFT 5
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_ADDSEG_SHIFT 6
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* copy of CR0.PE (protected mode) */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_PE_SHIFT 7
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_TF_SHIFT 8 /* must be same as eflags */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_EM_SHIFT 10
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_TS_SHIFT 11
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_IOPL_SHIFT 12 /* must be same as eflags */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_VM_SHIFT 17 /* must be same as eflags */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_HALTED_SHIFT 18 /* CPU halted */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_SMM_SHIFT 19 /* CPU in SMM mode */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_PE_MASK (1 << HF_PE_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_TF_MASK (1 << HF_TF_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_MP_MASK (1 << HF_MP_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_EM_MASK (1 << HF_EM_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_TS_MASK (1 << HF_TS_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_HALTED_MASK (1 << HF_HALTED_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR0_PE_MASK (1 << 0)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR0_MP_MASK (1 << 1)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR0_EM_MASK (1 << 2)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR0_TS_MASK (1 << 3)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR0_ET_MASK (1 << 4)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR0_NE_MASK (1 << 5)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR0_WP_MASK (1 << 16)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR0_AM_MASK (1 << 18)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR0_PG_MASK (1 << 31)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR4_VME_MASK (1 << 0)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR4_PVI_MASK (1 << 1)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR4_TSD_MASK (1 << 2)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR4_DE_MASK (1 << 3)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR4_PSE_MASK (1 << 4)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR4_PAE_MASK (1 << 5)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR4_PGE_MASK (1 << 7)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR4_PCE_MASK (1 << 8)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR4_OSFXSR_MASK (1 << 9)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CR4_OSXMMEXCPT_MASK (1 << 10)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_PRESENT_BIT 0
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_RW_BIT 1
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_USER_BIT 2
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_PWT_BIT 3
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define PG_PCD_BIT 4
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_ACCESSED_BIT 5
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_DIRTY_BIT 6
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_PSE_BIT 7
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_GLOBAL_BIT 8
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_NX_BIT 63
c4e146628a037393bad1d63b1860e97606277f48vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_RW_MASK (1 << PG_RW_BIT)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define PG_USER_MASK (1 << PG_USER_BIT)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define PG_PWT_MASK (1 << PG_PWT_BIT)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define PG_PCD_MASK (1 << PG_PCD_BIT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define PG_PSE_MASK (1 << PG_PSE_BIT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_NX_MASK (1LL << PG_NX_BIT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_ERROR_W_BIT 1
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define PG_ERROR_P_MASK 0x01
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_ERROR_U_MASK 0x04
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_ERROR_RSVD_MASK 0x08
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define PG_ERROR_I_D_MASK 0x10
c4e146628a037393bad1d63b1860e97606277f48vboxsync
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_IA32_APICBASE 0x1b
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_IA32_APICBASE_BSP (1<<8)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_IA32_APICBASE_ENABLE (1<<11)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#ifndef MSR_IA32_SYSENTER_CS /* VBox x86.h klugde */
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_IA32_SYSENTER_CS 0x174
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MSR_IA32_SYSENTER_ESP 0x175
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MSR_IA32_SYSENTER_EIP 0x176
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#endif
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MSR_MCG_CAP 0x179
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MSR_MCG_STATUS 0x17a
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MSR_MCG_CTL 0x17b
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MSR_PAT 0x277
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MSR_EFER 0xc0000080
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_EFER_SCE (1 << 0)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_EFER_LME (1 << 8)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_EFER_LMA (1 << 10)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_EFER_NXE (1 << 11)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_EFER_FFXSR (1 << 14)
c4e146628a037393bad1d63b1860e97606277f48vboxsync
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_STAR 0xc0000081
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MSR_LSTAR 0xc0000082
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_CSTAR 0xc0000083
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_FMASK 0xc0000084
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_FSBASE 0xc0000100
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_GSBASE 0xc0000101
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define MSR_KERNELGSBASE 0xc0000102
c4e146628a037393bad1d63b1860e97606277f48vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* cpuid_features bits */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_FP87 (1 << 0)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define CPUID_VME (1 << 1)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_DE (1 << 2)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_PSE (1 << 3)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_TSC (1 << 4)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_MSR (1 << 5)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_PAE (1 << 6)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_MCE (1 << 7)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_CX8 (1 << 8)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_APIC (1 << 9)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_SEP (1 << 11) /* sysenter/sysexit */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_MTRR (1 << 12)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define CPUID_PGE (1 << 13)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define CPUID_MCA (1 << 14)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_CMOV (1 << 15)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define CPUID_PAT (1 << 16)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define CPUID_PSE36 (1 << 17)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define CPUID_CLFLUSH (1 << 19)
c4e146628a037393bad1d63b1860e97606277f48vboxsync/* ... */
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define CPUID_MMX (1 << 23)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_FXSR (1 << 24)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_SSE (1 << 25)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_SSE2 (1 << 26)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#ifdef VBOX
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_HTT (1 << 28)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#endif
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT_SSE3 (1 << 0)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT_MONITOR (1 << 3)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT_DSCPL (1 << 4)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT_VMX (1 << 5)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define CPUID_EXT_SMX (1 << 6)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT_EST (1 << 7)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT_TM2 (1 << 8)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT_SSSE3 (1 << 9)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT_CID (1 << 10)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT_CX16 (1 << 13)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT_XTPR (1 << 14)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT_DCA (1 << 17)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define CPUID_EXT_POPCNT (1 << 22)
c4e146628a037393bad1d63b1860e97606277f48vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT2_SYSCALL (1 << 11)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define CPUID_EXT2_MP (1 << 19)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define CPUID_EXT2_NX (1 << 20)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define CPUID_EXT2_MMXEXT (1 << 22)
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define CPUID_EXT2_FFXSR (1 << 25)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT2_PDPE1GB (1 << 26)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT2_RDTSCP (1 << 27)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT2_LM (1 << 29)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT2_3DNOWEXT (1 << 30)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT2_3DNOW (1 << 31)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT3_LAHF_LM (1 << 0)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT3_CMP_LEG (1 << 1)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT3_SVM (1 << 2)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT3_EXTAPIC (1 << 3)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT3_CR8LEG (1 << 4)
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync#define CPUID_EXT3_ABM (1 << 5)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT3_SSE4A (1 << 6)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT3_MISALIGNSSE (1 << 7)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT3_OSVW (1 << 9)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPUID_EXT3_IBS (1 << 10)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP00_DIVZ 0
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP01_SSTP 1
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP02_NMI 2
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP03_INT3 3
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP04_INTO 4
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP05_BOUND 5
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP06_ILLOP 6
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP07_PREX 7
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP08_DBLE 8
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP09_XERR 9
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP0A_TSS 10
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP0B_NOSEG 11
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP0C_STACK 12
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP0D_GPF 13
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP0E_PAGE 14
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP10_COPR 16
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP11_ALGN 17
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define EXCP12_MCHK 18
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsyncenum {
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_MULW,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_MULL,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_MULQ,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_ADDW,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_ADDL,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_ADDQ,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_ADCW,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_ADCL,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_ADCQ,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_SUBW,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_SUBL,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_SUBQ,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_SBBW,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_SBBL,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_SBBQ,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_LOGICB, /* modify all flags, CC_DST = res */
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_LOGICW,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_LOGICL,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_LOGICQ,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_INCW,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_INCL,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_INCQ,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_DECW,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_DECL,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_DECQ,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_SHLW,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_SHLL,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_SHLQ,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_SARW,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_SARL,
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_SARQ,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_NB,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync};
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#ifdef FLOATX80
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define USE_X86LDOUBLE
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#endif
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#ifdef USE_X86LDOUBLE
e4f367251aede667a6de69baa54ef9eb5f150871vboxsynctypedef floatx80 CPU86_LDouble;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#else
e4f367251aede667a6de69baa54ef9eb5f150871vboxsynctypedef float64 CPU86_LDouble;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#endif
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsynctypedef struct SegmentCache {
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t selector;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync target_ulong base;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t limit;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t flags;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#ifdef VBOX
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync /** The new selector is saved here when we are unable to sync it before invoking the recompiled code. */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t newselector;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#endif
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync} SegmentCache;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsynctypedef union {
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint8_t _b[16];
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint16_t _w[8];
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t _l[4];
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint64_t _q[2];
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync float32 _s[4];
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync float64 _d[2];
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync} XMMReg;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsynctypedef union {
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint8_t _b[8];
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint16_t _w[2];
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t _l[1];
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint64_t q;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync} MMXReg;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#ifdef WORDS_BIGENDIAN
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define XMM_B(n) _b[15 - (n)]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define XMM_W(n) _w[7 - (n)]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define XMM_L(n) _l[3 - (n)]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define XMM_S(n) _s[3 - (n)]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define XMM_Q(n) _q[1 - (n)]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define XMM_D(n) _d[1 - (n)]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MMX_B(n) _b[7 - (n)]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MMX_W(n) _w[3 - (n)]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MMX_L(n) _l[1 - (n)]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#else
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define XMM_B(n) _b[n]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define XMM_W(n) _w[n]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define XMM_L(n) _l[n]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define XMM_S(n) _s[n]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define XMM_Q(n) _q[n]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define XMM_D(n) _d[n]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MMX_B(n) _b[n]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MMX_W(n) _w[n]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MMX_L(n) _l[n]
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#endif
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define MMX_Q(n) q
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#ifdef TARGET_X86_64
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define CPU_NB_REGS 16
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#else
c4e146628a037393bad1d63b1860e97606277f48vboxsync#define CPU_NB_REGS 8
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#endif
c4e146628a037393bad1d63b1860e97606277f48vboxsync
c4e146628a037393bad1d63b1860e97606277f48vboxsynctypedef struct CPUX86State {
c4e146628a037393bad1d63b1860e97606277f48vboxsync#if TARGET_LONG_BITS > HOST_LONG_BITS
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync /* temporaries if we cannot store them in host registers */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync target_ulong t0, t1, t2;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#endif
c4e146628a037393bad1d63b1860e97606277f48vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync /* standard registers */
c4e146628a037393bad1d63b1860e97606277f48vboxsync target_ulong regs[CPU_NB_REGS];
c4e146628a037393bad1d63b1860e97606277f48vboxsync target_ulong eip;
c4e146628a037393bad1d63b1860e97606277f48vboxsync target_ulong eflags; /* eflags register. During CPU emulation, CC
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync flags and DF are set to zero because they are
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync stored elsewhere */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync /* emulator internal eflags handling */
c4e146628a037393bad1d63b1860e97606277f48vboxsync target_ulong cc_src;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync target_ulong cc_dst;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t cc_op;
c4e146628a037393bad1d63b1860e97606277f48vboxsync int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
c4e146628a037393bad1d63b1860e97606277f48vboxsync uint32_t hflags; /* hidden flags, see HF_xxx constants */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
c4e146628a037393bad1d63b1860e97606277f48vboxsync /* segments */
c4e146628a037393bad1d63b1860e97606277f48vboxsync SegmentCache segs[6]; /* selector values */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync SegmentCache ldt;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync SegmentCache tr;
c4e146628a037393bad1d63b1860e97606277f48vboxsync SegmentCache gdt; /* only base and limit are used */
c4e146628a037393bad1d63b1860e97606277f48vboxsync SegmentCache idt; /* only base and limit are used */
c4e146628a037393bad1d63b1860e97606277f48vboxsync
c4e146628a037393bad1d63b1860e97606277f48vboxsync target_ulong cr[5]; /* NOTE: cr1 is unused */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t a20_mask;
c4e146628a037393bad1d63b1860e97606277f48vboxsync
c4e146628a037393bad1d63b1860e97606277f48vboxsync /* FPU state */
c4e146628a037393bad1d63b1860e97606277f48vboxsync unsigned int fpstt; /* top of stack index */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync unsigned int fpus;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync unsigned int fpuc;
c4e146628a037393bad1d63b1860e97606277f48vboxsync uint8_t fptags[8]; /* 0 = valid, 1 = empty */
c4e146628a037393bad1d63b1860e97606277f48vboxsync union {
c4e146628a037393bad1d63b1860e97606277f48vboxsync#ifdef USE_X86LDOUBLE
c4e146628a037393bad1d63b1860e97606277f48vboxsync CPU86_LDouble d __attribute__((aligned(16)));
c4e146628a037393bad1d63b1860e97606277f48vboxsync#else
c4e146628a037393bad1d63b1860e97606277f48vboxsync CPU86_LDouble d;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#endif
c4e146628a037393bad1d63b1860e97606277f48vboxsync MMXReg mmx;
c4e146628a037393bad1d63b1860e97606277f48vboxsync } fpregs[8];
c4e146628a037393bad1d63b1860e97606277f48vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync /* emulator internal variables */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync float_status fp_status;
c4e146628a037393bad1d63b1860e97606277f48vboxsync#ifdef VBOX
c4e146628a037393bad1d63b1860e97606277f48vboxsync uint32_t alignment3[3]; /* force the long double to start a 16 byte line. */
c4e146628a037393bad1d63b1860e97606277f48vboxsync#endif
c4e146628a037393bad1d63b1860e97606277f48vboxsync CPU86_LDouble ft0;
c4e146628a037393bad1d63b1860e97606277f48vboxsync#if defined(VBOX) && defined(RT_ARCH_X86) && !defined(RT_OS_DARWIN)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t alignment4; /* long double is 12 byte, pad it to 16. */
c4e146628a037393bad1d63b1860e97606277f48vboxsync#endif
c4e146628a037393bad1d63b1860e97606277f48vboxsync union {
c4e146628a037393bad1d63b1860e97606277f48vboxsync float f;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync double d;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync int i32;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync int64_t i64;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync } fp_convert;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync float_status sse_status;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t mxcsr;
c4e146628a037393bad1d63b1860e97606277f48vboxsync XMMReg xmm_regs[CPU_NB_REGS];
c4e146628a037393bad1d63b1860e97606277f48vboxsync XMMReg xmm_t0;
c4e146628a037393bad1d63b1860e97606277f48vboxsync MMXReg mmx_t0;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
c4e146628a037393bad1d63b1860e97606277f48vboxsync /* sysenter registers */
c4e146628a037393bad1d63b1860e97606277f48vboxsync uint32_t sysenter_cs;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint64_t sysenter_esp;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint64_t sysenter_eip;
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync#ifdef VBOX
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync uint32_t alignment0;
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync#endif
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync uint64_t efer;
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync uint64_t star;
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync#ifdef TARGET_X86_64
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync target_ulong lstar;
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync target_ulong cstar;
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync target_ulong fmask;
6fd8db3822fa68ed84bee1743ab6a0d046c7e8c8vboxsync target_ulong kernelgsbase;
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync#endif
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint64_t pat;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync /* temporary data for USE_CODE_COPY mode */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#ifdef USE_CODE_COPY
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t tmp0;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t saved_esp;
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync#endif
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync /* exception/interrupt handling */
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync jmp_buf jmp_env;
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync#if defined(VBOX) && defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync /* This will be removed when switching to the no-crt code everywhere. */
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync uint32_t alignment1[23];
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync#endif
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync int exception_index;
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync int error_code;
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync int exception_is_int;
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync target_ulong exception_next_eip;
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync target_ulong dr[8]; /* debug registers */
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync uint32_t smbase;
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync int interrupt_request;
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync int user_mode_only; /* user mode only simulation */
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CPU_COMMON
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#ifdef VBOX
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync /** cpu state flags. (see defines below) */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync uint32_t state;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync /** The VM handle. */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync PVM pVM;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync /** code buffer for instruction emulation */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync void *pvCodeBuffer;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync /** code buffer size */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync uint32_t cbCodeBuffer;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#endif /* VBOX */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync /* processor features (e.g. for CPUID insn) */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#ifndef VBOX /* remR3CpuId deals with these */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync uint32_t cpuid_level;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync uint32_t cpuid_vendor1;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync uint32_t cpuid_vendor2;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync uint32_t cpuid_vendor3;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync uint32_t cpuid_version;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#endif /* !VBOX */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync uint32_t cpuid_features;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync uint32_t cpuid_ext_features;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#ifndef VBOX
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync uint32_t cpuid_xlevel;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync uint32_t cpuid_model[12];
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#endif /* !VBOX */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync uint32_t cpuid_ext2_features;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync uint32_t cpuid_ext3_features;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#ifndef VBOX
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#ifdef USE_KQEMU
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync int kqemu_enabled;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync int last_io_time;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#endif
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync /* in order to simplify APIC support, we leave this pointer to the
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync user */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync struct APICState *apic_state;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#else
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync uint32_t alignment2[3];
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#endif
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync} CPUX86State;
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#ifdef VBOX
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync/* Version 1.6 structure; just for loading the old saved state */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsynctypedef struct SegmentCache_Ver16 {
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t selector;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t base;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t limit;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t flags;
#ifdef VBOX
/** The new selector is saved here when we are unable to sync it before invoking the recompiled code. */
uint32_t newselector;
#endif
} SegmentCache_Ver16;
#define CPU_NB_REGS_VER16 8
/* Version 1.6 structure; just for loading the old saved state */
typedef struct CPUX86State_Ver16 {
#if TARGET_LONG_BITS > HOST_LONG_BITS
/* temporaries if we cannot store them in host registers */
uint32_t t0, t1, t2;
#endif
/* standard registers */
uint32_t regs[CPU_NB_REGS_VER16];
uint32_t eip;
uint32_t eflags; /* eflags register. During CPU emulation, CC
flags and DF are set to zero because they are
stored elsewhere */
/* emulator internal eflags handling */
uint32_t cc_src;
uint32_t cc_dst;
uint32_t cc_op;
int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
uint32_t hflags; /* hidden flags, see HF_xxx constants */
/* segments */
SegmentCache_Ver16 segs[6]; /* selector values */
SegmentCache_Ver16 ldt;
SegmentCache_Ver16 tr;
SegmentCache_Ver16 gdt; /* only base and limit are used */
SegmentCache_Ver16 idt; /* only base and limit are used */
uint32_t cr[5]; /* NOTE: cr1 is unused */
uint32_t a20_mask;
/* FPU state */
unsigned int fpstt; /* top of stack index */
unsigned int fpus;
unsigned int fpuc;
uint8_t fptags[8]; /* 0 = valid, 1 = empty */
union {
#ifdef USE_X86LDOUBLE
CPU86_LDouble d __attribute__((aligned(16)));
#else
CPU86_LDouble d;
#endif
MMXReg mmx;
} fpregs[8];
/* emulator internal variables */
float_status fp_status;
#ifdef VBOX
uint32_t alignment3[3]; /* force the long double to start a 16 byte line. */
#endif
CPU86_LDouble ft0;
#if defined(VBOX) && defined(RT_ARCH_X86) && !defined(RT_OS_DARWIN)
uint32_t alignment4; /* long double is 12 byte, pad it to 16. */
#endif
union {
float f;
double d;
int i32;
int64_t i64;
} fp_convert;
float_status sse_status;
uint32_t mxcsr;
XMMReg xmm_regs[CPU_NB_REGS_VER16];
XMMReg xmm_t0;
MMXReg mmx_t0;
/* sysenter registers */
uint32_t sysenter_cs;
uint32_t sysenter_esp;
uint32_t sysenter_eip;
#ifdef VBOX
uint32_t alignment0;
#endif
uint64_t efer;
uint64_t star;
uint64_t pat;
/* temporary data for USE_CODE_COPY mode */
#ifdef USE_CODE_COPY
uint32_t tmp0;
uint32_t saved_esp;
int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
#endif
/* exception/interrupt handling */
jmp_buf jmp_env;
} CPUX86State_Ver16;
/** CPUX86State state flags
* @{ */
#define CPU_RAW_RING0 0x0002 /* Set after first time RawR0 is executed, never cleared. */
#define CPU_EMULATE_SINGLE_INSTR 0x0040 /* Execute a single instruction in emulation mode */
#define CPU_EMULATE_SINGLE_STEP 0x0080 /* go into single step mode */
#define CPU_RAW_HWACC 0x0100 /* Set after first time HWACC is executed, never cleared. */
/** @} */
#endif /* !VBOX */
#ifdef VBOX
CPUX86State *cpu_x86_init(CPUX86State *env);
#else /* !VBOX */
CPUX86State *cpu_x86_init(void);
#endif /* !VBOX */
int cpu_x86_exec(CPUX86State *s);
void cpu_x86_close(CPUX86State *s);
int cpu_get_pic_interrupt(CPUX86State *s);
/* MSDOS compatibility mode FPU exception support */
void cpu_set_ferr(CPUX86State *s);
/* this function must always be used to load data in the segment
cache: it synchronizes the hflags with the segment cache values */
static inline void cpu_x86_load_seg_cache(CPUX86State *env,
int seg_reg, unsigned int selector,
target_ulong base,
unsigned int limit,
unsigned int flags)
{
SegmentCache *sc;
unsigned int new_hflags;
sc = &env->segs[seg_reg];
sc->selector = selector;
sc->base = base;
sc->limit = limit;
sc->flags = flags;
#ifdef VBOX
sc->newselector = 0;
#endif
/* update the hidden flags */
{
if (seg_reg == R_CS) {
#ifdef TARGET_X86_64
if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
/* long mode */
env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
env->hflags &= ~(HF_ADDSEG_MASK);
} else
#endif
{
/* legacy / compatibility case */
new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
>> (DESC_B_SHIFT - HF_CS32_SHIFT);
env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
new_hflags;
}
}
new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
>> (DESC_B_SHIFT - HF_SS32_SHIFT);
if (env->hflags & HF_CS64_MASK) {
/* zero base assumed for DS, ES and SS in long mode */
} else if (!(env->cr[0] & CR0_PE_MASK) ||
(env->eflags & VM_MASK) ||
!(env->hflags & HF_CS32_MASK)) {
/* XXX: try to avoid this test. The problem comes from the
fact that is real mode or vm86 mode we only modify the
'base' and 'selector' fields of the segment cache to go
faster. A solution may be to force addseg to one in
translate-i386.c. */
new_hflags |= HF_ADDSEG_MASK;
} else {
new_hflags |= ((env->segs[R_DS].base |
env->segs[R_ES].base |
env->segs[R_SS].base) != 0) <<
HF_ADDSEG_SHIFT;
}
env->hflags = (env->hflags &
~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
}
}
/* wrapper, just in case memory mappings must be changed */
static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
{
#if HF_CPL_MASK == 3
s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
#else
#error HF_CPL_MASK is hardcoded
#endif
}
/* used for debug or cpu save/restore */
void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
/* the following helpers are only usable in user mode simulation as
they can trigger unexpected exceptions */
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
int cpu_x86_signal_handler(int host_signum, void *pinfo,
void *puc);
void cpu_x86_set_a20(CPUX86State *env, int a20_state);
uint64_t cpu_get_tsc(CPUX86State *env);
void cpu_set_apic_base(CPUX86State *env, uint64_t val);
uint64_t cpu_get_apic_base(CPUX86State *env);
void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
#ifndef NO_CPU_IO_DEFS
uint8_t cpu_get_apic_tpr(CPUX86State *env);
#endif
void cpu_smm_update(CPUX86State *env);
/* will be suppressed */
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
/* used to debug */
#define X86_DUMP_FPU 0x0001 /* dump FPU state too */
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
#ifdef USE_KQEMU
static inline int cpu_get_time_fast(void)
{
int low, high;
asm volatile("rdtsc" : "=a" (low), "=d" (high));
return low;
}
#endif
#ifdef VBOX
void cpu_trap_raw(CPUX86State *env1);
/* in helper.c */
uint8_t read_byte(CPUX86State *env1, target_ulong addr);
uint16_t read_word(CPUX86State *env1, target_ulong addr);
void write_byte(CPUX86State *env1, target_ulong addr, uint8_t val);
uint32_t read_dword(CPUX86State *env1, target_ulong addr);
void write_word(CPUX86State *env1, target_ulong addr, uint16_t val);
void write_dword(CPUX86State *env1, target_ulong addr, uint32_t val);
/* in helper.c */
int emulate_single_instr(CPUX86State *env1);
int get_ss_esp_from_tss_raw(CPUX86State *env1, uint32_t *ss_ptr, uint32_t *esp_ptr, int dpl);
void restore_raw_fp_state(CPUX86State *env, uint8_t *ptr);
void save_raw_fp_state(CPUX86State *env, uint8_t *ptr);
#endif
#define TARGET_PAGE_BITS 12
#include "cpu-all.h"
#endif /* CPU_I386_H */