cpu.h revision d65680efa46fa49e8bf14e67b29b782510ff934c
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * i386 virtual CPU header
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * Copyright (c) 2003 Fabrice Bellard
c7814cf6e1240a519cbec0441e033d0e2470ed00vboxsync * This library is free software; you can redistribute it and/or
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * modify it under the terms of the GNU Lesser General Public
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * License as published by the Free Software Foundation; either
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * version 2 of the License, or (at your option) any later version.
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * This library is distributed in the hope that it will be useful,
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * but WITHOUT ANY WARRANTY; without even the implied warranty of
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * Lesser General Public License for more details.
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * You should have received a copy of the GNU Lesser General Public
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * License along with this library; if not, write to the Free Software
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * other than GPL or LGPL is available it will apply instead, Sun elects to use only
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * a choice of LGPL license versions is made available with the language indicating
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * that LGPLv2 or any later version may be used, or where a choice of which version
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync * of the LGPL is applied is otherwise unspecified.
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* target supports implicit self modifying code */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* support for self modifying code even if the modified instruction is
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync close to the modifying instruction */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#if defined(VBOX)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#endif /* VBOX */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* segment descriptor fields */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_C_MASK (1 << 10) /* code: conforming */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define DESC_E_MASK (1 << 10) /* data: expansion direction */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* eflags masks */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* hidden flags - used internally by qemu to represent additionnal cpu
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync with eflags. */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* current cpl */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* true if soft mmu is being used */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* true if hardware interrupts must be disabled for next instruction */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* 16 or 32 segments */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* copy of CR0.PE (protected mode) */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_IOPL_SHIFT 12 /* must be same as eflags */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync#ifndef MSR_IA32_SYSENTER_CS /* VBox x86.h klugde */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync/* cpuid_features bits */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsynctypedef struct SegmentCache {
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync /** The new selector is saved here when we are unable to sync it before invoking the recompiled code. */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsynctypedef union {
e4f367251aede667a6de69baa54ef9eb5f150871vboxsynctypedef union {
c4e146628a037393bad1d63b1860e97606277f48vboxsynctypedef struct CPUX86State {
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync /* temporaries if we cannot store them in host registers */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync /* standard registers */
c4e146628a037393bad1d63b1860e97606277f48vboxsync target_ulong eflags; /* eflags register. During CPU emulation, CC
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync flags and DF are set to zero because they are
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync stored elsewhere */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync /* emulator internal eflags handling */
c4e146628a037393bad1d63b1860e97606277f48vboxsync uint32_t hflags; /* hidden flags, see HF_xxx constants */
c4e146628a037393bad1d63b1860e97606277f48vboxsync /* segments */
c4e146628a037393bad1d63b1860e97606277f48vboxsync SegmentCache gdt; /* only base and limit are used */
c4e146628a037393bad1d63b1860e97606277f48vboxsync SegmentCache idt; /* only base and limit are used */
c4e146628a037393bad1d63b1860e97606277f48vboxsync /* FPU state */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync unsigned int fpus;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync unsigned int fpuc;
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync /* emulator internal variables */
c4e146628a037393bad1d63b1860e97606277f48vboxsync uint32_t alignment3[3]; /* force the long double to start a 16 byte line. */
c4e146628a037393bad1d63b1860e97606277f48vboxsync#if defined(VBOX) && defined(RT_ARCH_X86) && !defined(RT_OS_DARWIN)
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync uint32_t alignment4; /* long double is 12 byte, pad it to 16. */
c4e146628a037393bad1d63b1860e97606277f48vboxsync /* sysenter registers */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsync /* temporary data for USE_CODE_COPY mode */
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync /* exception/interrupt handling */
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync#if defined(VBOX) && defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
d7856d565919537fcfd3ea1630608ba3ed2a25bcvboxsync /* This will be removed when switching to the no-crt code everywhere. */
5eca1f6baf7020cb7a872fbf7086872e7e812301vboxsync int user_mode_only; /* user mode only simulation */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync /** cpu state flags. (see defines below) */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync /** The VM handle. */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync /** code buffer for instruction emulation */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync /** code buffer size */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#endif /* VBOX */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync /* processor features (e.g. for CPUID insn) */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#endif /* !VBOX */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync#endif /* !VBOX */
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync /* in order to simplify APIC support, we leave this pointer to the
5af981fb39925101cec5e22afb746e2125b55ce4vboxsync/* Version 1.6 structure; just for loading the old saved state */
e4f367251aede667a6de69baa54ef9eb5f150871vboxsynctypedef struct SegmentCache_Ver16 {
#ifdef VBOX
/** The new selector is saved here when we are unable to sync it before invoking the recompiled code. */
typedef struct CPUX86State_Ver16 {
unsigned int fpus;
unsigned int fpuc;
#ifdef USE_X86LDOUBLE
#ifdef VBOX
int i32;
} fp_convert;
#ifdef VBOX
#ifdef USE_CODE_COPY
#ifdef VBOX
unsigned int limit,
unsigned int flags)
unsigned int new_hflags;
#ifdef VBOX
#ifdef TARGET_X86_64
translate-i386.c. */
void *puc);
#ifndef NO_CPU_IO_DEFS
#ifdef USE_KQEMU
static inline int cpu_get_time_fast(void)
return low;
#ifdef VBOX
/* in helper.c */
/* in helper.c */
#include "cpu-all.h"