softmmu_header.h revision 178d85b8274f9ac82fb553c80760bbbb4044401c
/*
* Software MMU support
*
* Copyright (c) 2003 Fabrice Bellard
*
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
* other than GPL or LGPL is available it will apply instead, Oracle elects to use only
* the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
* a choice of LGPL license versions is made available with the language indicating
* that LGPLv2 or any later version may be used, or where a choice of which version
* of the LGPL is applied is otherwise unspecified.
*/
#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define SUFFIX l
#define USUFFIX l
#define SUFFIX w
#define DATA_STYPE int16_t
#define SUFFIX b
#define DATA_STYPE int8_t
#else
#endif
#if ACCESS_TYPE < (NB_MMU_MODES)
#define CPU_MMU_INDEX ACCESS_TYPE
#else
#endif
#if DATA_SIZE == 8
#else
#define RES_TYPE int
#endif
#else
#endif
{
int res;
asm volatile ("movl %1, %%edx\n"
"movl %1, %%eax\n"
"shrl %3, %%edx\n"
"andl %4, %%eax\n"
"andl %2, %%edx\n"
"leal %5(%%edx, %%ebp), %%edx\n"
"cmpl (%%edx), %%eax\n"
"movl %1, %%eax\n"
"je 1f\n"
"movl %6, %%edx\n"
"call %7\n"
"movl %%eax, %0\n"
"jmp 2f\n"
"1:\n"
"addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
"movzbl (%%eax), %0\n"
"movzwl (%%eax), %0\n"
"movl (%%eax), %0\n"
#else
#endif
"2:\n"
: "=r" (res)
: "r" (ptr),
"i" (CPU_MMU_INDEX),
: "%eax", "%ecx", "%edx", "memory", "cc");
return res;
}
#if DATA_SIZE <= 2
{
int res;
asm volatile ("movl %1, %%edx\n"
"movl %1, %%eax\n"
"shrl %3, %%edx\n"
"andl %4, %%eax\n"
"andl %2, %%edx\n"
"leal %5(%%edx, %%ebp), %%edx\n"
"cmpl (%%edx), %%eax\n"
"movl %1, %%eax\n"
"je 1f\n"
"movl %6, %%edx\n"
"call %7\n"
#if DATA_SIZE == 1
"movsbl %%al, %0\n"
"movswl %%ax, %0\n"
#else
#endif
"jmp 2f\n"
"1:\n"
"addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
"movsbl (%%eax), %0\n"
"movswl (%%eax), %0\n"
#else
#endif
"2:\n"
: "=r" (res)
: "r" (ptr),
"i" (CPU_MMU_INDEX),
: "%eax", "%ecx", "%edx", "memory", "cc");
return res;
}
#endif
{
asm volatile ("movl %0, %%edx\n"
"movl %0, %%eax\n"
"shrl %3, %%edx\n"
"andl %4, %%eax\n"
"andl %2, %%edx\n"
"leal %5(%%edx, %%ebp), %%edx\n"
"cmpl (%%edx), %%eax\n"
"movl %0, %%eax\n"
"je 1f\n"
#if DATA_SIZE == 1
"movzbl %b1, %%edx\n"
"movzwl %w1, %%edx\n"
"movl %1, %%edx\n"
#else
#endif
"movl %6, %%ecx\n"
"call %7\n"
"jmp 2f\n"
"1:\n"
"addl 8(%%edx), %%eax\n"
#if DATA_SIZE == 1
"movb %b1, (%%eax)\n"
"movw %w1, (%%eax)\n"
"movl %1, (%%eax)\n"
#else
#endif
"2:\n"
:
: "r" (ptr),
#if DATA_SIZE == 1
"q" (v),
#else
"r" (v),
#endif
"i" (CPU_MMU_INDEX),
: "%eax", "%ecx", "%edx", "memory", "cc");
}
#else
{
int page_index;
unsigned long physaddr;
int mmu_idx;
} else {
}
return res;
}
#if DATA_SIZE <= 2
{
int res, page_index;
unsigned long physaddr;
int mmu_idx;
} else {
}
return res;
}
#endif
/* generic store macro */
{
int page_index;
unsigned long physaddr;
int mmu_idx;
} else {
}
}
#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
#endif /* !asm */
#if DATA_SIZE == 8
{
union {
float64 d;
uint64_t i;
} u;
return u.d;
}
{
union {
float64 d;
uint64_t i;
} u;
u.d = v;
}
#endif /* DATA_SIZE == 8 */
#if DATA_SIZE == 4
{
union {
float32 f;
uint32_t i;
} u;
return u.f;
}
{
union {
float32 f;
uint32_t i;
} u;
u.f = v;
}
#endif /* DATA_SIZE == 4 */
#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */