exec.c revision 178d85b8274f9ac82fb553c80760bbbb4044401c
5fc50ecb8dc8ef74adfc1c1f0d4e144d7f4d8faestoddard/*
4ed92248676a091e0d73db61773d9059b36d0861stoddard * virtual page mapping and translated block handling
4ed92248676a091e0d73db61773d9059b36d0861stoddard *
4ed92248676a091e0d73db61773d9059b36d0861stoddard * Copyright (c) 2003 Fabrice Bellard
4ed92248676a091e0d73db61773d9059b36d0861stoddard *
4ed92248676a091e0d73db61773d9059b36d0861stoddard * This library is free software; you can redistribute it and/or
4ed92248676a091e0d73db61773d9059b36d0861stoddard * modify it under the terms of the GNU Lesser General Public
4ed92248676a091e0d73db61773d9059b36d0861stoddard * License as published by the Free Software Foundation; either
4ed92248676a091e0d73db61773d9059b36d0861stoddard * version 2 of the License, or (at your option) any later version.
4ed92248676a091e0d73db61773d9059b36d0861stoddard *
b4b458e66e24979631466a69c4bae3090a7e50fewrowe * This library is distributed in the hope that it will be useful,
4ed92248676a091e0d73db61773d9059b36d0861stoddard * but WITHOUT ANY WARRANTY; without even the implied warranty of
fa29e798c69385995c601ddfe75cbd5cf29244efwrowe * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
4ed92248676a091e0d73db61773d9059b36d0861stoddard * Lesser General Public License for more details.
fa29e798c69385995c601ddfe75cbd5cf29244efwrowe *
752c83c97683b1fb9879ba874593a135155a043cwrowe * You should have received a copy of the GNU Lesser General Public
fa29e798c69385995c601ddfe75cbd5cf29244efwrowe * License along with this library; if not, write to the Free Software
6b441c81aae632befd971e634b4a36780c71d18ewrowe * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
424303d026faabb9e9752310911d00fa737b603awrowe */
424303d026faabb9e9752310911d00fa737b603awrowe
424303d026faabb9e9752310911d00fa737b603awrowe/*
9d134be9b7d1d6f0f9e910346a8075dac77b3d69ianh * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowe * a choice of LGPL license versions is made available with the language indicating
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowe * that LGPLv2 or any later version may be used, or where a choice of which version
a04a085d201d1620c077ba6ecaa7022b417b1cd5tdonovan * of the LGPL is applied is otherwise unspecified.
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowe */
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowe
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowe#include "config.h"
fa29e798c69385995c601ddfe75cbd5cf29244efwrowe#ifndef VBOX
4ed92248676a091e0d73db61773d9059b36d0861stoddard#ifdef _WIN32
ea0acbc141b3ca2ef21666bd23bfea9af9a758aawrowe#define WIN32_LEAN_AND_MEAN
9d134be9b7d1d6f0f9e910346a8075dac77b3d69ianh#include <windows.h>
38c8e9fef8d0536fb150af3be396f41a32d687adwrowe#else
bcd36d1522403b4387451f8a17a528e632915e8dwrowe#include <sys/types.h>
bcd36d1522403b4387451f8a17a528e632915e8dwrowe#include <sys/mman.h>
4ed92248676a091e0d73db61773d9059b36d0861stoddard#endif
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe#include <stdlib.h>
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe#include <stdio.h>
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe#include <stdarg.h>
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe#include <string.h>
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe#include <errno.h>
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe#include <unistd.h>
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe#include <inttypes.h>
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe#else /* VBOX */
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe# include <stdlib.h>
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe# include <stdio.h>
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe# include <iprt/alloc.h>
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe# include <iprt/string.h>
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe# include <iprt/param.h>
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe# include <VBox/vmm/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe#endif /* VBOX */
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe#include "cpu.h"
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe#include "exec-all.h"
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe#include "qemu-common.h"
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe#include "tcg.h"
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe#ifndef VBOX
0ea0379ff6438182ac3c9d8f108deb3c82210319wrowe#include "hw/hw.h"
6173077ec421fe85891d4b914c87175beb0a9293wrowe#endif
c71d15c4b41b9d89e90e936d49b4e5a6db19244ewrowe#include "osdep.h"
6173077ec421fe85891d4b914c87175beb0a9293wrowe#if defined(CONFIG_USER_ONLY)
6173077ec421fe85891d4b914c87175beb0a9293wrowe#include <qemu.h>
c71d15c4b41b9d89e90e936d49b4e5a6db19244ewrowe#endif
6173077ec421fe85891d4b914c87175beb0a9293wrowe
6173077ec421fe85891d4b914c87175beb0a9293wrowe//#define DEBUG_TB_INVALIDATE
b4b458e66e24979631466a69c4bae3090a7e50fewrowe//#define DEBUG_FLUSH
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe//#define DEBUG_TLB
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe//#define DEBUG_UNASSIGNED
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe
6166dacd3c3d034394c1f8c131919ea7452835a7wrowe/* make various TB consistency checks */
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe//#define DEBUG_TB_CHECK
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe//#define DEBUG_TLB_CHECK
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe//#define DEBUG_IOPORT
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe//#define DEBUG_SUBPAGE
b4b458e66e24979631466a69c4bae3090a7e50fewrowe
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe#if !defined(CONFIG_USER_ONLY)
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe/* TB consistency checks only implemented for usermode emulation. */
fa3f183306fa2ec98249f2afec904d403643a015wrowe#undef DEBUG_TB_CHECK
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe#endif
743aeb835754aadabaec38c00742899668eb9dd1wrowe
fa3f183306fa2ec98249f2afec904d403643a015wrowe#define SMC_BITMAP_USE_THRESHOLD 10
a78b700fa90213df137e4178a9bd9c81aadd39d3wrowe
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe#define MMAP_AREA_START 0x00000000
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe#define MMAP_AREA_END 0xa8000000
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe#if defined(TARGET_SPARC64)
549b1f3d6860ae792e6a8c8d3a483140bdb857a5wrowe#define TARGET_PHYS_ADDR_SPACE_BITS 41
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe#elif defined(TARGET_SPARC)
743aeb835754aadabaec38c00742899668eb9dd1wrowe#define TARGET_PHYS_ADDR_SPACE_BITS 36
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe#elif defined(TARGET_ALPHA)
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe#define TARGET_PHYS_ADDR_SPACE_BITS 42
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe#define TARGET_VIRT_ADDR_SPACE_BITS 42
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe#elif defined(TARGET_PPC64)
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe#define TARGET_PHYS_ADDR_SPACE_BITS 42
b4b458e66e24979631466a69c4bae3090a7e50fewrowe#elif defined(TARGET_X86_64) && !defined(USE_KQEMU)
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe#define TARGET_PHYS_ADDR_SPACE_BITS 42
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe#elif defined(TARGET_I386) && !defined(USE_KQEMU)
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe#define TARGET_PHYS_ADDR_SPACE_BITS 36
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe#else
032eeda9f618fa26f635c9e8dfd854c17e76262fwrowe/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe#define TARGET_PHYS_ADDR_SPACE_BITS 32
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe#endif
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowestatic TranslationBlock *tbs;
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawroweint code_gen_max_blocks;
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawroweTranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowestatic int nb_tbs;
92fb4b4faaea055db085fc0864950c2a5edd0de2jwoolley/* any access to the tbs or the page table must use this lock */
fa3f183306fa2ec98249f2afec904d403643a015wrowespinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe#ifndef VBOX
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe#if defined(__arm__) || defined(__sparc_v9__)
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe/* The prologue must be reachable with a direct jump. ARM and Sparc64
549b1f3d6860ae792e6a8c8d3a483140bdb857a5wrowe have limited branch ranges (possibly also PPC) so place it in a
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe section close to code segment. */
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe#define code_gen_section \
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe __attribute__((__section__(".gen_code"))) \
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe __attribute__((aligned (32)))
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe#else
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe#define code_gen_section \
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe __attribute__((aligned (32)))
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe#endif
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe
6a5b8f7bd9abe819babda806a7245a31cd0dd2fbwroweuint8_t code_gen_prologue[1024] code_gen_section;
6a5b8f7bd9abe819babda806a7245a31cd0dd2fbwrowe#else /* VBOX */
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawroweextern uint8_t* code_gen_prologue;
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe#endif /* VBOX */
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowestatic uint8_t *code_gen_buffer;
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowestatic unsigned long code_gen_buffer_size;
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowe/* threshold to flush the translated code buffer */
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowestatic unsigned long code_gen_buffer_max_size;
cfab5b5b6dc82c578597b582f76491c96b86eeb7wroweuint8_t *code_gen_ptr;
413043ed189411cd1c673fc4911b583cb85c2c39wrowe
a04a085d201d1620c077ba6ecaa7022b417b1cd5tdonovan#ifndef VBOX
7a9d2ce2e2f592e97c0d4819e0e6567efcc4ba7bwrowe#if !defined(CONFIG_USER_ONLY)
413043ed189411cd1c673fc4911b583cb85c2c39wroweram_addr_t phys_ram_size;
cfab5b5b6dc82c578597b582f76491c96b86eeb7wroweint phys_ram_fd;
a04a085d201d1620c077ba6ecaa7022b417b1cd5tdonovanuint8_t *phys_ram_base;
cfab5b5b6dc82c578597b582f76491c96b86eeb7wroweuint8_t *phys_ram_dirty;
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowestatic int in_migration;
a04a085d201d1620c077ba6ecaa7022b417b1cd5tdonovanstatic ram_addr_t phys_ram_alloc_offset = 0;
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowe#endif
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowe#else /* VBOX */
cfab5b5b6dc82c578597b582f76491c96b86eeb7wroweRTGCPHYS phys_ram_size;
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowe/* we have memory ranges (the high PC-BIOS mapping) which
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowe causes some pages to fall outside the dirty map here. */
4ed92248676a091e0d73db61773d9059b36d0861stoddardRTGCPHYS phys_ram_dirty_size;
071646a05417cc437fcffec9512588f75bd39a03wrowe#endif /* VBOX */
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe#if !defined(VBOX)
424303d026faabb9e9752310911d00fa737b603awroweuint8_t *phys_ram_base;
424303d026faabb9e9752310911d00fa737b603awrowe#endif
424303d026faabb9e9752310911d00fa737b603awroweuint8_t *phys_ram_dirty;
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe
424303d026faabb9e9752310911d00fa737b603awroweCPUState *first_cpu;
424303d026faabb9e9752310911d00fa737b603awrowe/* current CPU in the current thread. It is only valid inside
424303d026faabb9e9752310911d00fa737b603awrowe cpu_exec() */
424303d026faabb9e9752310911d00fa737b603awroweCPUState *cpu_single_env;
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe/* 0 = Do not count executed instructions.
fa29e798c69385995c601ddfe75cbd5cf29244efwrowe 1 = Precise instruction counting.
f397bb616fba8b3a5a9b3c57a5c89ad0e254b673mturk 2 = Adaptive rate instruction counting. */
9d134be9b7d1d6f0f9e910346a8075dac77b3d69ianhint use_icount = 0;
6b441c81aae632befd971e634b4a36780c71d18ewrowe/* Current instruction counter. While executing translated code this may
6b441c81aae632befd971e634b4a36780c71d18ewrowe include some instructions that have not yet been executed. */
6b441c81aae632befd971e634b4a36780c71d18ewroweint64_t qemu_icount;
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowetypedef struct PageDesc {
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe /* list of TBs intersecting this ram page */
7ffdcdd65e145ef18d9193d89bffff10c5da4961wrowe TranslationBlock *first_tb;
7ffdcdd65e145ef18d9193d89bffff10c5da4961wrowe /* in order to optimize self modifying code, we count the number
7ffdcdd65e145ef18d9193d89bffff10c5da4961wrowe of lookups we do to a given page to use a bitmap */
7ffdcdd65e145ef18d9193d89bffff10c5da4961wrowe unsigned int code_write_count;
7ffdcdd65e145ef18d9193d89bffff10c5da4961wrowe uint8_t *code_bitmap;
6b441c81aae632befd971e634b4a36780c71d18ewrowe#if defined(CONFIG_USER_ONLY)
7ffdcdd65e145ef18d9193d89bffff10c5da4961wrowe unsigned long flags;
6b441c81aae632befd971e634b4a36780c71d18ewrowe#endif
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe} PageDesc;
ea0acbc141b3ca2ef21666bd23bfea9af9a758aawrowe
ea0acbc141b3ca2ef21666bd23bfea9af9a758aawrowetypedef struct PhysPageDesc {
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe /* offset in host memory of the page + io_index in the low bits */
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe ram_addr_t phys_offset;
fa29e798c69385995c601ddfe75cbd5cf29244efwrowe} PhysPageDesc;
4ed92248676a091e0d73db61773d9059b36d0861stoddard
50feafa397d01128b8cf94ad1602d3d78e1a4169wrowe#define L2_BITS 10
50feafa397d01128b8cf94ad1602d3d78e1a4169wrowe#if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS)
ea0acbc141b3ca2ef21666bd23bfea9af9a758aawrowe/* XXX: this is a temporary hack for alpha target.
ea0acbc141b3ca2ef21666bd23bfea9af9a758aawrowe * In the future, this is to be replaced by a multi-level table
50feafa397d01128b8cf94ad1602d3d78e1a4169wrowe * to actually be able to handle the complete 64 bits address space.
ea0acbc141b3ca2ef21666bd23bfea9af9a758aawrowe */
ea0acbc141b3ca2ef21666bd23bfea9af9a758aawrowe#define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
ea0acbc141b3ca2ef21666bd23bfea9af9a758aawrowe#else
ea0acbc141b3ca2ef21666bd23bfea9af9a758aawrowe#define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
50feafa397d01128b8cf94ad1602d3d78e1a4169wrowe#endif
50feafa397d01128b8cf94ad1602d3d78e1a4169wrowe#ifdef VBOX
98086904a5df1d6127b49bf06af39f23ff844889wrowe#define L0_BITS (TARGET_PHYS_ADDR_SPACE_BITS - 32)
98086904a5df1d6127b49bf06af39f23ff844889wrowe#endif
b4b458e66e24979631466a69c4bae3090a7e50fewrowe
b4b458e66e24979631466a69c4bae3090a7e50fewrowe#ifdef VBOX
b4b458e66e24979631466a69c4bae3090a7e50fewrowe#define L0_SIZE (1 << L0_BITS)
b4b458e66e24979631466a69c4bae3090a7e50fewrowe#endif
b4b458e66e24979631466a69c4bae3090a7e50fewrowe#define L1_SIZE (1 << L1_BITS)
4ed92248676a091e0d73db61773d9059b36d0861stoddard#define L2_SIZE (1 << L2_BITS)
549b1f3d6860ae792e6a8c8d3a483140bdb857a5wrowe
4ed92248676a091e0d73db61773d9059b36d0861stoddardunsigned long qemu_real_host_page_size;
4ed92248676a091e0d73db61773d9059b36d0861stoddardunsigned long qemu_host_page_bits;
549b1f3d6860ae792e6a8c8d3a483140bdb857a5wroweunsigned long qemu_host_page_size;
4ed92248676a091e0d73db61773d9059b36d0861stoddardunsigned long qemu_host_page_mask;
4ed92248676a091e0d73db61773d9059b36d0861stoddard
549b1f3d6860ae792e6a8c8d3a483140bdb857a5wrowe/* XXX: for system emulation, it could just be an array */
4ed92248676a091e0d73db61773d9059b36d0861stoddard#ifndef VBOX
4ed92248676a091e0d73db61773d9059b36d0861stoddardstatic PageDesc *l1_map[L1_SIZE];
549b1f3d6860ae792e6a8c8d3a483140bdb857a5wrowestatic PhysPageDesc **l1_phys_map;
4ed92248676a091e0d73db61773d9059b36d0861stoddard#else
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowestatic unsigned l0_map_max_used = 0;
90f3e85cc3332e202aa198786798709fc55505d9wrowestatic PageDesc **l0_map[L0_SIZE];
b4b458e66e24979631466a69c4bae3090a7e50fewrowestatic void **l0_phys_map[L0_SIZE];
b4b458e66e24979631466a69c4bae3090a7e50fewrowe#endif
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe#if !defined(CONFIG_USER_ONLY)
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowestatic void io_mem_init(void);
b4b458e66e24979631466a69c4bae3090a7e50fewrowe
50feafa397d01128b8cf94ad1602d3d78e1a4169wrowe/* io memory support */
4ed92248676a091e0d73db61773d9059b36d0861stoddardCPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
4ed92248676a091e0d73db61773d9059b36d0861stoddardCPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
50feafa397d01128b8cf94ad1602d3d78e1a4169wrowevoid *io_mem_opaque[IO_MEM_NB_ENTRIES];
4ed92248676a091e0d73db61773d9059b36d0861stoddardstatic int io_mem_nb;
4ed92248676a091e0d73db61773d9059b36d0861stoddardstatic int io_mem_watch;
4ed92248676a091e0d73db61773d9059b36d0861stoddard#endif
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe
1e83c8de3aa48b316b28057d53995272baf1260cwrowe#ifndef VBOX
1e83c8de3aa48b316b28057d53995272baf1260cwrowe/* log support */
4ed92248676a091e0d73db61773d9059b36d0861stoddardstatic const char *logfilename = "/tmp/qemu.log";
0ea0379ff6438182ac3c9d8f108deb3c82210319wrowe#endif /* !VBOX */
0ea0379ff6438182ac3c9d8f108deb3c82210319wroweFILE *logfile;
0ea0379ff6438182ac3c9d8f108deb3c82210319wroweint loglevel;
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwrowe#ifndef VBOX
ea0acbc141b3ca2ef21666bd23bfea9af9a758aawrowestatic int log_append = 0;
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwrowe#endif
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwrowe
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwrowe/* statistics */
ea0acbc141b3ca2ef21666bd23bfea9af9a758aawrowe#ifndef VBOX
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwrowestatic int tlb_flush_count;
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwrowestatic int tb_flush_count;
ea0acbc141b3ca2ef21666bd23bfea9af9a758aawrowestatic int tb_phys_invalidate_count;
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwrowe#else /* VBOX - Resettable U32 stats, see VBoxRecompiler.c. */
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwroweuint32_t tlb_flush_count;
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwroweuint32_t tb_flush_count;
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwroweuint32_t tb_phys_invalidate_count;
06bd11dc20356466f38185ddb47fc798b4508d5fwrowe#endif /* VBOX */
1e83c8de3aa48b316b28057d53995272baf1260cwrowe
1e83c8de3aa48b316b28057d53995272baf1260cwrowe#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
1e83c8de3aa48b316b28057d53995272baf1260cwrowetypedef struct subpage_t {
1e83c8de3aa48b316b28057d53995272baf1260cwrowe target_phys_addr_t base;
413043ed189411cd1c673fc4911b583cb85c2c39wrowe CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4];
5158d1bbe54607d02bb5e5b2219e7aed4684e41btdonovan CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4];
413043ed189411cd1c673fc4911b583cb85c2c39wrowe void *opaque[TARGET_PAGE_SIZE][2][4];
413043ed189411cd1c673fc4911b583cb85c2c39wrowe} subpage_t;
a04a085d201d1620c077ba6ecaa7022b417b1cd5tdonovan
7a9d2ce2e2f592e97c0d4819e0e6567efcc4ba7bwrowe#ifndef VBOX
413043ed189411cd1c673fc4911b583cb85c2c39wrowe#ifdef _WIN32
413043ed189411cd1c673fc4911b583cb85c2c39wrowestatic void map_exec(void *addr, long size)
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe{
1e83c8de3aa48b316b28057d53995272baf1260cwrowe DWORD old_protect;
1e83c8de3aa48b316b28057d53995272baf1260cwrowe VirtualProtect(addr, size,
c3200c488bb3f941a88d5bed94abef0f46946bd3wrowe PAGE_EXECUTE_READWRITE, &old_protect);
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe
1e83c8de3aa48b316b28057d53995272baf1260cwrowe}
4ed92248676a091e0d73db61773d9059b36d0861stoddard#else
1e83c8de3aa48b316b28057d53995272baf1260cwrowestatic void map_exec(void *addr, long size)
14d27a22a8fdb25e6e82d8af853a63bd4c6bd894wrowe{
6a5b8f7bd9abe819babda806a7245a31cd0dd2fbwrowe unsigned long start, end, page_size;
6a5b8f7bd9abe819babda806a7245a31cd0dd2fbwrowe
6a5b8f7bd9abe819babda806a7245a31cd0dd2fbwrowe page_size = getpagesize();
6a5b8f7bd9abe819babda806a7245a31cd0dd2fbwrowe start = (unsigned long)addr;
9106bbba512da6e81bb4feb268bbd17435354d79wrowe start &= ~(page_size - 1);
9106bbba512da6e81bb4feb268bbd17435354d79wrowe
9106bbba512da6e81bb4feb268bbd17435354d79wrowe end = (unsigned long)addr + size;
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe end += page_size - 1;
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe end &= ~(page_size - 1);
14d5b1a7866541c4eb974f2d213d2aea59743c95wrowe
1a1462ebfd091853d54071a693fc7ad4c5573f8awrowe mprotect((void *)start, end - start,
483ed5892604266e702d65db4d0b2b621c488a09wrowe PROT_READ | PROT_WRITE | PROT_EXEC);
14d5b1a7866541c4eb974f2d213d2aea59743c95wrowe}
bc21ce13cec2409c8fdb7122154636b2df97715ajerenkrantz#endif
34e753c9dba1e821f54f0d4179f8774f854123eecolm#else /* VBOX */
14d5b1a7866541c4eb974f2d213d2aea59743c95wrowestatic void map_exec(void *addr, long size)
14d5b1a7866541c4eb974f2d213d2aea59743c95wrowe{
14d5b1a7866541c4eb974f2d213d2aea59743c95wrowe RTMemProtect(addr, size,
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe RTMEM_PROT_EXEC | RTMEM_PROT_READ | RTMEM_PROT_WRITE);
ac19b3a64a76401bc7e4e378b51c245a7e8516a5mturk}
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe#endif /* VBOX */
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe
14d5b1a7866541c4eb974f2d213d2aea59743c95wrowestatic void page_init(void)
14d5b1a7866541c4eb974f2d213d2aea59743c95wrowe{
14d5b1a7866541c4eb974f2d213d2aea59743c95wrowe /* NOTE: we can always suppose that qemu_host_page_size >=
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe TARGET_PAGE_SIZE */
14d5b1a7866541c4eb974f2d213d2aea59743c95wrowe#ifdef VBOX
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe RTMemProtect(code_gen_buffer, sizeof(code_gen_buffer),
1e83c8de3aa48b316b28057d53995272baf1260cwrowe RTMEM_PROT_EXEC | RTMEM_PROT_READ | RTMEM_PROT_WRITE);
1e83c8de3aa48b316b28057d53995272baf1260cwrowe qemu_real_host_page_size = PAGE_SIZE;
1e83c8de3aa48b316b28057d53995272baf1260cwrowe#else /* !VBOX */
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe#ifdef _WIN32
bf03ef02d5f0f64ee0e91f3c4007154897d4dd34mturk {
1e83c8de3aa48b316b28057d53995272baf1260cwrowe SYSTEM_INFO system_info;
bf03ef02d5f0f64ee0e91f3c4007154897d4dd34mturk DWORD old_protect;
bf03ef02d5f0f64ee0e91f3c4007154897d4dd34mturk
483ed5892604266e702d65db4d0b2b621c488a09wrowe GetSystemInfo(&system_info);
483ed5892604266e702d65db4d0b2b621c488a09wrowe qemu_real_host_page_size = system_info.dwPageSize;
483ed5892604266e702d65db4d0b2b621c488a09wrowe }
483ed5892604266e702d65db4d0b2b621c488a09wrowe#else
483ed5892604266e702d65db4d0b2b621c488a09wrowe qemu_real_host_page_size = getpagesize();
483ed5892604266e702d65db4d0b2b621c488a09wrowe#endif
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe#endif /* !VBOX */
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe
1e83c8de3aa48b316b28057d53995272baf1260cwrowe if (qemu_host_page_size == 0)
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe qemu_host_page_size = qemu_real_host_page_size;
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe if (qemu_host_page_size < TARGET_PAGE_SIZE)
1e83c8de3aa48b316b28057d53995272baf1260cwrowe qemu_host_page_size = TARGET_PAGE_SIZE;
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe qemu_host_page_bits = 0;
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe#ifndef VBOX
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe while ((1 << qemu_host_page_bits) < qemu_host_page_size)
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe#else
0f488df653e7e8cf4ee0006a3138f9474ca1d375wrowe while ((1 << qemu_host_page_bits) < (int)qemu_host_page_size)
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe#endif
538b2b76902ad0b42b4fb2c8ace94bf74d8100cewrowe qemu_host_page_bits++;
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe qemu_host_page_mask = ~(qemu_host_page_size - 1);
538b2b76902ad0b42b4fb2c8ace94bf74d8100cewrowe#ifndef VBOX
538b2b76902ad0b42b4fb2c8ace94bf74d8100cewrowe l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *));
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe memset(l1_phys_map, 0, L1_SIZE * sizeof(void *));
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe#endif
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe#ifdef VBOX
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe /* We use other means to set reserved bit on our pages */
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe#else /* !VBOX */
b23117c3c7034b6e61dac1b0ffebd256950abb56wrowe#if !defined(_WIN32) && defined(CONFIG_USER_ONLY)
483ed5892604266e702d65db4d0b2b621c488a09wrowe {
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe long long startaddr, endaddr;
b23117c3c7034b6e61dac1b0ffebd256950abb56wrowe FILE *f;
483ed5892604266e702d65db4d0b2b621c488a09wrowe int n;
b23117c3c7034b6e61dac1b0ffebd256950abb56wrowe
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe mmap_lock();
175ab758dce807990c2cfd281ffced0dd8f7d2f4nd last_brk = (unsigned long)sbrk(0);
92e403ad9206eea8af7bd426fd1a19d531816d83wrowe f = fopen("/proc/self/maps", "r");
58b8ccdd4dbf4b314e016de6eeebfe45be45451end if (f) {
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe do {
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr);
255d4d329b2d41e4ac0c3ade5cfe528a078ef682wrowe if (n == 2) {
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe startaddr = MIN(startaddr,
1e83c8de3aa48b316b28057d53995272baf1260cwrowe (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
483ed5892604266e702d65db4d0b2b621c488a09wrowe endaddr = MIN(endaddr,
3e156d3e4514cf57f8ac77e275a68d1c12a3b937wrowe (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
1e83c8de3aa48b316b28057d53995272baf1260cwrowe page_set_flags(startaddr & TARGET_PAGE_MASK,
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe TARGET_PAGE_ALIGN(endaddr),
1e83c8de3aa48b316b28057d53995272baf1260cwrowe PAGE_RESERVED);
1e83c8de3aa48b316b28057d53995272baf1260cwrowe }
1e83c8de3aa48b316b28057d53995272baf1260cwrowe } while (!feof(f));
1e83c8de3aa48b316b28057d53995272baf1260cwrowe fclose(f);
1e83c8de3aa48b316b28057d53995272baf1260cwrowe }
1e83c8de3aa48b316b28057d53995272baf1260cwrowe mmap_unlock();
1e83c8de3aa48b316b28057d53995272baf1260cwrowe }
1e83c8de3aa48b316b28057d53995272baf1260cwrowe#endif
1e83c8de3aa48b316b28057d53995272baf1260cwrowe#endif /* !VBOX */
1e83c8de3aa48b316b28057d53995272baf1260cwrowe}
1e83c8de3aa48b316b28057d53995272baf1260cwrowe
24b0a59507af2a3621f586fa2a2aafc3640aa3d2ndstatic inline PageDesc **page_l1_map(target_ulong index)
5a51653135041ee35b24fa67453bff4e9f8e3591wrowe{
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe#ifndef VBOX
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe#if TARGET_LONG_BITS > 32
1e83c8de3aa48b316b28057d53995272baf1260cwrowe /* Host memory outside guest VM. For 32-bit targets we have already
1e83c8de3aa48b316b28057d53995272baf1260cwrowe excluded high addresses. */
1e83c8de3aa48b316b28057d53995272baf1260cwrowe if (index > ((target_ulong)L2_SIZE * L1_SIZE))
0e6bee8eb9112f77eb50766e58424afac61104d9wrowe return NULL;
1e83c8de3aa48b316b28057d53995272baf1260cwrowe#endif
1e83c8de3aa48b316b28057d53995272baf1260cwrowe return &l1_map[index >> L2_BITS];
1e83c8de3aa48b316b28057d53995272baf1260cwrowe#else /* VBOX */
1e83c8de3aa48b316b28057d53995272baf1260cwrowe PageDesc **l1_map;
995f5596d461cdd916f9ae5b7b4dcd27efbc3c2fwrowe AssertMsgReturn(index < (target_ulong)L2_SIZE * L1_SIZE * L0_SIZE,
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe ("index=%RGp >= %RGp; L1_SIZE=%#x L2_SIZE=%#x L0_SIZE=%#x\n",
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe (RTGCPHYS)index, (RTGCPHYS)L2_SIZE * L1_SIZE, L1_SIZE, L2_SIZE, L0_SIZE),
1e83c8de3aa48b316b28057d53995272baf1260cwrowe NULL);
1e83c8de3aa48b316b28057d53995272baf1260cwrowe l1_map = l0_map[index >> (L1_BITS + L2_BITS)];
1e83c8de3aa48b316b28057d53995272baf1260cwrowe if (RT_UNLIKELY(!l1_map))
1e83c8de3aa48b316b28057d53995272baf1260cwrowe {
3ea7933c5a74b8d8d54ec2689190a865a0689420wrowe unsigned i0 = index >> (L1_BITS + L2_BITS);
1e83c8de3aa48b316b28057d53995272baf1260cwrowe l0_map[i0] = l1_map = qemu_mallocz(sizeof(PageDesc *) * L1_SIZE);
1e83c8de3aa48b316b28057d53995272baf1260cwrowe if (RT_UNLIKELY(!l1_map))
1e83c8de3aa48b316b28057d53995272baf1260cwrowe return NULL;
1e83c8de3aa48b316b28057d53995272baf1260cwrowe if (i0 >= l0_map_max_used)
a21b3b9d8ebb12fd51fa1d17e44d5644a35a9a5fnd l0_map_max_used = i0 + 1;
0b64c3e5c7379284f90efc7193f16b373df39fe1wrowe }
f4b681ff0aa05efee56b42a893911f28c3ad931ewrowe return &l1_map[(index >> L2_BITS) & (L1_SIZE - 1)];
1e83c8de3aa48b316b28057d53995272baf1260cwrowe#endif /* VBOX */
522c5d883dd6489e5b3583c52502365e09d64382mturk}
522c5d883dd6489e5b3583c52502365e09d64382mturk
2d7d2ccd828d0424f046b62d57e5551cf8ee293fwrowestatic inline PageDesc *page_find_alloc(target_ulong index)
50c06405bc48121db2913925549407fd3e79bcedmturk{
2d7d2ccd828d0424f046b62d57e5551cf8ee293fwrowe PageDesc **lp, *p;
2d7d2ccd828d0424f046b62d57e5551cf8ee293fwrowe lp = page_l1_map(index);
f4b681ff0aa05efee56b42a893911f28c3ad931ewrowe if (!lp)
483ed5892604266e702d65db4d0b2b621c488a09wrowe return NULL;
483ed5892604266e702d65db4d0b2b621c488a09wrowe
483ed5892604266e702d65db4d0b2b621c488a09wrowe p = *lp;
483ed5892604266e702d65db4d0b2b621c488a09wrowe if (!p) {
483ed5892604266e702d65db4d0b2b621c488a09wrowe /* allocate if not found */
483ed5892604266e702d65db4d0b2b621c488a09wrowe#if defined(CONFIG_USER_ONLY)
483ed5892604266e702d65db4d0b2b621c488a09wrowe unsigned long addr;
483ed5892604266e702d65db4d0b2b621c488a09wrowe size_t len = sizeof(PageDesc) * L2_SIZE;
483ed5892604266e702d65db4d0b2b621c488a09wrowe /* Don't use qemu_malloc because it may recurse. */
483ed5892604266e702d65db4d0b2b621c488a09wrowe p = mmap(0, len, PROT_READ | PROT_WRITE,
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
483ed5892604266e702d65db4d0b2b621c488a09wrowe *lp = p;
483ed5892604266e702d65db4d0b2b621c488a09wrowe addr = h2g(p);
483ed5892604266e702d65db4d0b2b621c488a09wrowe if (addr == (target_ulong)addr) {
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe page_set_flags(addr & TARGET_PAGE_MASK,
fa3f183306fa2ec98249f2afec904d403643a015wrowe TARGET_PAGE_ALIGN(addr + len),
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe PAGE_RESERVED);
743aeb835754aadabaec38c00742899668eb9dd1wrowe }
1e83c8de3aa48b316b28057d53995272baf1260cwrowe#else
743aeb835754aadabaec38c00742899668eb9dd1wrowe p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE);
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowe *lp = p;
91884afe32b87f355822244b8c123ea5b770368fwrowe#endif
1e83c8de3aa48b316b28057d53995272baf1260cwrowe }
ea63537bfba2de6945fb6b4e5ceddf130e3bc0ecwrowe return p + (index & (L2_SIZE - 1));
c82ccb99a59cb210c31b096a567e393e59d558f3colm}
1e83c8de3aa48b316b28057d53995272baf1260cwrowe
1e83c8de3aa48b316b28057d53995272baf1260cwrowestatic inline PageDesc *page_find(target_ulong index)
1e83c8de3aa48b316b28057d53995272baf1260cwrowe{
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe PageDesc **lp, *p;
1e83c8de3aa48b316b28057d53995272baf1260cwrowe lp = page_l1_map(index);
1e83c8de3aa48b316b28057d53995272baf1260cwrowe if (!lp)
91884afe32b87f355822244b8c123ea5b770368fwrowe return NULL;
29fc13ae8c586a980b0d4e8cba4546b370a951e6wrowe
1e83c8de3aa48b316b28057d53995272baf1260cwrowe p = *lp;
1e83c8de3aa48b316b28057d53995272baf1260cwrowe if (!p)
29fc13ae8c586a980b0d4e8cba4546b370a951e6wrowe return 0;
4ed92248676a091e0d73db61773d9059b36d0861stoddard return p + (index & (L2_SIZE - 1));
4c35be7cad99269afb697fccc1b9ba85dd2ce702wrowe}
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowestatic PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe{
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe void **lp, **p;
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe PhysPageDesc *pd;
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe#ifndef VBOX
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe p = (void **)l1_phys_map;
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe#if TARGET_PHYS_ADDR_SPACE_BITS > 32
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe#if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe#error unsupported TARGET_PHYS_ADDR_SPACE_BITS
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe#endif
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1));
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe p = *lp;
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe if (!p) {
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe /* allocate if not found */
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe if (!alloc)
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe return NULL;
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe p = qemu_vmalloc(sizeof(void *) * L1_SIZE);
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe memset(p, 0, sizeof(void *) * L1_SIZE);
b56ce33e3fe5670a4562de222c60ade06fe1bce0wrowe *lp = p;
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe }
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe#endif
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe#else /* VBOX */
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe /* level 0 lookup and lazy allocation of level 1 map. */
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe if (RT_UNLIKELY(index >= (target_phys_addr_t)L2_SIZE * L1_SIZE * L0_SIZE))
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe return NULL;
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe p = l0_phys_map[index >> (L1_BITS + L2_BITS)];
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe if (RT_UNLIKELY(!p)) {
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe if (!alloc)
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe return NULL;
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe p = qemu_vmalloc(sizeof(void **) * L1_SIZE);
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe memset(p, 0, sizeof(void **) * L1_SIZE);
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe l0_phys_map[index >> (L1_BITS + L2_BITS)] = p;
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe }
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe
634c70c6512b0ae61fb1ee130266e6e9af170803wrowe /* level 1 lookup and lazy allocation of level 2 map. */
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe#endif /* VBOX */
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwrowe lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwrowe pd = *lp;
ea0acbc141b3ca2ef21666bd23bfea9af9a758aawrowe if (!pd) {
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwrowe int i;
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwrowe /* allocate if not found */
d7f2b79379c5a3b849bf3d5dacf7180805ecba1fwrowe if (!alloc)
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe return NULL;
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE);
634c70c6512b0ae61fb1ee130266e6e9af170803wrowe *lp = pd;
743aeb835754aadabaec38c00742899668eb9dd1wrowe for (i = 0; i < L2_SIZE; i++)
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe pd[i].phys_offset = IO_MEM_UNASSIGNED;
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe }
9cef38b3a87190d0c4dcd5b389573418af9de73cwrowe return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe}
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowestatic inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe{
945f023c83c2d18bf5145a5b9af48fc3216fbef6wrowe return phys_page_find_alloc(index, 0);
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe}
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe
14d27a22a8fdb25e6e82d8af853a63bd4c6bd894wrowe#if !defined(CONFIG_USER_ONLY)
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowestatic void tlb_protect_code(ram_addr_t ram_addr);
6bc96ef510ce100bfdeefd80b8f05c010373ed13wrowestatic void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
6bc96ef510ce100bfdeefd80b8f05c010373ed13wrowe target_ulong vaddr);
6bc96ef510ce100bfdeefd80b8f05c010373ed13wrowe#define mmap_lock() do { } while(0)
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowe#define mmap_unlock() do { } while(0)
a04a085d201d1620c077ba6ecaa7022b417b1cd5tdonovan#endif
721a5708aab94cd3587ecff3c5775c985efb7125wrowe
cfab5b5b6dc82c578597b582f76491c96b86eeb7wrowe#ifdef VBOX /* We don't need such huge codegen buffer size, as execute
f71283367c234bf49ddc8ba7b23d3d3829db0d8dmturk most of the code in raw or hwacc mode. */
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#define DEFAULT_CODE_GEN_BUFFER_SIZE (8 * 1024 * 1024)
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#else /* !VBOX */
483ed5892604266e702d65db4d0b2b621c488a09wrowe#define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024)
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#endif /* !VBOX */
bc21ce13cec2409c8fdb7122154636b2df97715ajerenkrantz
34e753c9dba1e821f54f0d4179f8774f854123eecolm#if defined(CONFIG_USER_ONLY)
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe/* Currently it is not recommanded to allocate big chunks of data in
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe user mode. It will change when a dedicated libc will be used */
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#define USE_STATIC_CODE_GEN_BUFFER
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe#endif
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe/* VBox allocates codegen buffer dynamically */
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#ifndef VBOX
ac19b3a64a76401bc7e4e378b51c245a7e8516a5mturk#ifdef USE_STATIC_CODE_GEN_BUFFER
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowestatic uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE];
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#endif
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#endif
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowestatic void code_gen_alloc(unsigned long tb_size)
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe{
bf03ef02d5f0f64ee0e91f3c4007154897d4dd34mturk#ifdef USE_STATIC_CODE_GEN_BUFFER
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe code_gen_buffer = static_code_gen_buffer;
bf03ef02d5f0f64ee0e91f3c4007154897d4dd34mturk code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
bf03ef02d5f0f64ee0e91f3c4007154897d4dd34mturk map_exec(code_gen_buffer, code_gen_buffer_size);
483ed5892604266e702d65db4d0b2b621c488a09wrowe#else
483ed5892604266e702d65db4d0b2b621c488a09wrowe#ifdef VBOX
483ed5892604266e702d65db4d0b2b621c488a09wrowe /* We cannot use phys_ram_size here, as it's 0 now,
483ed5892604266e702d65db4d0b2b621c488a09wrowe * it only gets initialized once RAM registration callback
ee8892ba26f52316734c59d8002ab349c2e3fdbdcolm * (REMR3NotifyPhysRamRegister()) called.
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe */
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#else
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe code_gen_buffer_size = tb_size;
0f488df653e7e8cf4ee0006a3138f9474ca1d375wrowe if (code_gen_buffer_size == 0) {
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe#if defined(CONFIG_USER_ONLY)
0f488df653e7e8cf4ee0006a3138f9474ca1d375wrowe /* in user mode, phys_ram_size is not meaningful */
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe#else
483ed5892604266e702d65db4d0b2b621c488a09wrowe /* XXX: needs adjustments */
483ed5892604266e702d65db4d0b2b621c488a09wrowe code_gen_buffer_size = (unsigned long)(phys_ram_size / 4);
483ed5892604266e702d65db4d0b2b621c488a09wrowe#endif
483ed5892604266e702d65db4d0b2b621c488a09wrowe
7c11b20dfccedb7381518b3cc3cc9ef9e6731cb1wrowe }
7bffd59eadbb9e58f17fd29655fce6509fc1bb36niq if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE)
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#endif /* VBOX */
6a5b8f7bd9abe819babda806a7245a31cd0dd2fbwrowe
6a5b8f7bd9abe819babda806a7245a31cd0dd2fbwrowe /* The code gen buffer location may have constraints depending on
6a5b8f7bd9abe819babda806a7245a31cd0dd2fbwrowe the host cpu and OS */
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#ifdef VBOX
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe code_gen_buffer = RTMemExecAlloc(code_gen_buffer_size);
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe if (!code_gen_buffer) {
483ed5892604266e702d65db4d0b2b621c488a09wrowe LogRel(("REM: failed allocate codegen buffer %lld\n",
3e156d3e4514cf57f8ac77e275a68d1c12a3b937wrowe code_gen_buffer_size));
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe return;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe }
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#else //!VBOX
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#if defined(__linux__)
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe {
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe int flags;
6a5b8f7bd9abe819babda806a7245a31cd0dd2fbwrowe void *start = NULL;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe
24b0a59507af2a3621f586fa2a2aafc3640aa3d2nd flags = MAP_PRIVATE | MAP_ANONYMOUS;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#if defined(__x86_64__)
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe flags |= MAP_32BIT;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe /* Cannot map more than that */
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe if (code_gen_buffer_size > (800 * 1024 * 1024))
0e6bee8eb9112f77eb50766e58424afac61104d9wrowe code_gen_buffer_size = (800 * 1024 * 1024);
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#elif defined(__sparc_v9__)
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe // Map the buffer below 2G, so we can use direct calls and branches
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe flags |= MAP_FIXED;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe start = (void *) 0x60000000UL;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe if (code_gen_buffer_size > (512 * 1024 * 1024))
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe code_gen_buffer_size = (512 * 1024 * 1024);
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#endif
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe code_gen_buffer = mmap(start, code_gen_buffer_size,
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe PROT_WRITE | PROT_READ | PROT_EXEC,
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe flags, -1, 0);
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe if (code_gen_buffer == MAP_FAILED) {
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe fprintf(stderr, "Could not allocate dynamic translator buffer\n");
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe exit(1);
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe }
a21b3b9d8ebb12fd51fa1d17e44d5644a35a9a5fnd }
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#elif defined(__FreeBSD__)
522c5d883dd6489e5b3583c52502365e09d64382mturk {
522c5d883dd6489e5b3583c52502365e09d64382mturk int flags;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe void *addr = NULL;
50c06405bc48121db2913925549407fd3e79bcedmturk flags = MAP_PRIVATE | MAP_ANONYMOUS;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#if defined(__x86_64__)
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume
483ed5892604266e702d65db4d0b2b621c488a09wrowe * 0x40000000 is free */
483ed5892604266e702d65db4d0b2b621c488a09wrowe flags |= MAP_FIXED;
483ed5892604266e702d65db4d0b2b621c488a09wrowe addr = (void *)0x40000000;
483ed5892604266e702d65db4d0b2b621c488a09wrowe /* Cannot map more than that */
483ed5892604266e702d65db4d0b2b621c488a09wrowe if (code_gen_buffer_size > (800 * 1024 * 1024))
483ed5892604266e702d65db4d0b2b621c488a09wrowe code_gen_buffer_size = (800 * 1024 * 1024);
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#endif
483ed5892604266e702d65db4d0b2b621c488a09wrowe code_gen_buffer = mmap(addr, code_gen_buffer_size,
483ed5892604266e702d65db4d0b2b621c488a09wrowe PROT_WRITE | PROT_READ | PROT_EXEC,
483ed5892604266e702d65db4d0b2b621c488a09wrowe flags, -1, 0);
752c83c97683b1fb9879ba874593a135155a043cwrowe if (code_gen_buffer == MAP_FAILED) {
752c83c97683b1fb9879ba874593a135155a043cwrowe fprintf(stderr, "Could not allocate dynamic translator buffer\n");
752c83c97683b1fb9879ba874593a135155a043cwrowe exit(1);
752c83c97683b1fb9879ba874593a135155a043cwrowe }
752c83c97683b1fb9879ba874593a135155a043cwrowe }
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#else
752c83c97683b1fb9879ba874593a135155a043cwrowe code_gen_buffer = qemu_malloc(code_gen_buffer_size);
ea63537bfba2de6945fb6b4e5ceddf130e3bc0ecwrowe if (!code_gen_buffer) {
c82ccb99a59cb210c31b096a567e393e59d558f3colm fprintf(stderr, "Could not allocate dynamic translator buffer\n");
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe exit(1);
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe }
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe map_exec(code_gen_buffer, code_gen_buffer_size);
c639d9d16cb8ac0ea8163c8c46e34ef9c6810ce2wrowe#endif
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe map_exec(code_gen_prologue, sizeof(code_gen_prologue));
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#endif /* !VBOX */
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#endif /* !USE_STATIC_CODE_GEN_BUFFER */
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#ifndef VBOX
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe map_exec(code_gen_prologue, sizeof(code_gen_prologue));
287f1ad541b1b895b2e5c7150d47471713100d1emturk#else
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe map_exec(code_gen_prologue, _1K);
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#endif
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe code_gen_buffer_max_size = code_gen_buffer_size -
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe code_gen_max_block_size();
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
087e59fbe3a245960f2cbc9750181a9aba7a4f24wrowe}
18062914633d6aa27c5f07c6ed20e3d169714c89wrowe
18062914633d6aa27c5f07c6ed20e3d169714c89wrowe/* Must be called before using the QEMU cpus. 'tb_size' is the size
1462f24d09bed587fcdfb69abf1e858598a06382wrowe (in bytes) allocated to the translation buffer. Zero means default
1462f24d09bed587fcdfb69abf1e858598a06382wrowe size. */
bdf8917ac686167be51db99d7cf238fa51f5be02wrowevoid cpu_exec_init_all(unsigned long tb_size)
37e7fdce0a4809a6c4cd3c102fc4668a6659ca95wrowe{
1462f24d09bed587fcdfb69abf1e858598a06382wrowe cpu_gen_init();
25813a71353f3b45ca1ddda037b395cced603564slive code_gen_alloc(tb_size);
424303d026faabb9e9752310911d00fa737b603awrowe code_gen_ptr = code_gen_buffer;
424303d026faabb9e9752310911d00fa737b603awrowe page_init();
0bfd482e54583b43b826299aa6c9853f703191edwrowe#if !defined(CONFIG_USER_ONLY)
37e7fdce0a4809a6c4cd3c102fc4668a6659ca95wrowe io_mem_init();
341fe490659bc00823087e34c84ae13567d9fb8fwrowe#endif
37e7fdce0a4809a6c4cd3c102fc4668a6659ca95wrowe}
37e7fdce0a4809a6c4cd3c102fc4668a6659ca95wrowe
37e7fdce0a4809a6c4cd3c102fc4668a6659ca95wrowe#ifndef VBOX
1462f24d09bed587fcdfb69abf1e858598a06382wrowe#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
1462f24d09bed587fcdfb69abf1e858598a06382wrowe
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#define CPU_COMMON_SAVE_VERSION 1
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowestatic void cpu_common_save(QEMUFile *f, void *opaque)
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe{
fdc76d3c3f3fea82ba0f1d8af646f8ea5e4734a2wrowe CPUState *env = opaque;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe qemu_put_be32s(f, &env->halted);
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe qemu_put_be32s(f, &env->interrupt_request);
875f57a863e8f7522f78c370e25db2a552231ca8wrowe}
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe
a8f3504993ae9a401b6fc87c7a00b716b112e3d0wrowestatic int cpu_common_load(QEMUFile *f, void *opaque, int version_id)
752c83c97683b1fb9879ba874593a135155a043cwrowe{
875f57a863e8f7522f78c370e25db2a552231ca8wrowe CPUState *env = opaque;
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe if (version_id != CPU_COMMON_SAVE_VERSION)
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe return -EINVAL;
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe qemu_get_be32s(f, &env->halted);
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe qemu_get_be32s(f, &env->interrupt_request);
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe tlb_flush(env, 1);
f99d4fa2605925f385a184ba3789be3423690533wrowe
f99d4fa2605925f385a184ba3789be3423690533wrowe return 0;
25b0d23db56d263195cb27b77ee4c06a4bac92a3wrowe}
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe#endif
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe#endif //!VBOX
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowevoid cpu_exec_init(CPUState *env)
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe{
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe CPUState **penv;
f2f6daffb4236c6781e779e57561581c92a1f539wrowe int cpu_index;
19725e678f8b916b0952a002356d2098301e9727wrowe
032eeda9f618fa26f635c9e8dfd854c17e76262fwrowe env->next_cpu = NULL;
19725e678f8b916b0952a002356d2098301e9727wrowe penv = &first_cpu;
19725e678f8b916b0952a002356d2098301e9727wrowe cpu_index = 0;
032eeda9f618fa26f635c9e8dfd854c17e76262fwrowe while (*penv != NULL) {
f1b8465dec39c934d4bef4a2366139ffdd021851wrowe penv = (CPUState **)&(*penv)->next_cpu;
f1b8465dec39c934d4bef4a2366139ffdd021851wrowe cpu_index++;
19725e678f8b916b0952a002356d2098301e9727wrowe }
19725e678f8b916b0952a002356d2098301e9727wrowe env->cpu_index = cpu_index;
19725e678f8b916b0952a002356d2098301e9727wrowe env->nb_watchpoints = 0;
823627d210d6c8bf02aec333587428584b29b6e2wrowe *penv = env;
823627d210d6c8bf02aec333587428584b29b6e2wrowe#ifndef VBOX
823627d210d6c8bf02aec333587428584b29b6e2wrowe#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
19725e678f8b916b0952a002356d2098301e9727wrowe register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION,
75202015bdb6602aaea6d187db3e2a922dd2526ewrowe cpu_common_save, cpu_common_load, env);
19725e678f8b916b0952a002356d2098301e9727wrowe register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
f2f6daffb4236c6781e779e57561581c92a1f539wrowe cpu_save, cpu_load, env);
f2f6daffb4236c6781e779e57561581c92a1f539wrowe#endif
f2f6daffb4236c6781e779e57561581c92a1f539wrowe#endif // !VBOX
19725e678f8b916b0952a002356d2098301e9727wrowe}
032eeda9f618fa26f635c9e8dfd854c17e76262fwrowe
19725e678f8b916b0952a002356d2098301e9727wrowestatic inline void invalidate_page_bitmap(PageDesc *p)
032eeda9f618fa26f635c9e8dfd854c17e76262fwrowe{
032eeda9f618fa26f635c9e8dfd854c17e76262fwrowe if (p->code_bitmap) {
19725e678f8b916b0952a002356d2098301e9727wrowe qemu_free(p->code_bitmap);
25b0d23db56d263195cb27b77ee4c06a4bac92a3wrowe p->code_bitmap = NULL;
032eeda9f618fa26f635c9e8dfd854c17e76262fwrowe }
032eeda9f618fa26f635c9e8dfd854c17e76262fwrowe p->code_write_count = 0;
032eeda9f618fa26f635c9e8dfd854c17e76262fwrowe}
032eeda9f618fa26f635c9e8dfd854c17e76262fwrowe
032eeda9f618fa26f635c9e8dfd854c17e76262fwrowe/* set to NULL all the 'first_tb' fields in all PageDescs */
032eeda9f618fa26f635c9e8dfd854c17e76262fwrowestatic void page_flush_tb(void)
19725e678f8b916b0952a002356d2098301e9727wrowe{
f1b8465dec39c934d4bef4a2366139ffdd021851wrowe int i, j;
032eeda9f618fa26f635c9e8dfd854c17e76262fwrowe PageDesc *p;
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe#ifdef VBOX
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe int k;
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe#endif
19725e678f8b916b0952a002356d2098301e9727wrowe
823627d210d6c8bf02aec333587428584b29b6e2wrowe#ifdef VBOX
823627d210d6c8bf02aec333587428584b29b6e2wrowe k = l0_map_max_used;
823627d210d6c8bf02aec333587428584b29b6e2wrowe while (k-- > 0) {
19725e678f8b916b0952a002356d2098301e9727wrowe PageDesc **l1_map = l0_map[k];
f1b8465dec39c934d4bef4a2366139ffdd021851wrowe if (l1_map) {
f1b8465dec39c934d4bef4a2366139ffdd021851wrowe#endif
f1b8465dec39c934d4bef4a2366139ffdd021851wrowe for(i = 0; i < L1_SIZE; i++) {
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe p = l1_map[i];
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe if (p) {
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe for(j = 0; j < L2_SIZE; j++) {
19725e678f8b916b0952a002356d2098301e9727wrowe p->first_tb = NULL;
19725e678f8b916b0952a002356d2098301e9727wrowe invalidate_page_bitmap(p);
746e483939cf8224eb881df41df75ef524d18223wrowe p++;
19725e678f8b916b0952a002356d2098301e9727wrowe }
f2f6daffb4236c6781e779e57561581c92a1f539wrowe }
f2f6daffb4236c6781e779e57561581c92a1f539wrowe }
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe#ifdef VBOX
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe }
875f57a863e8f7522f78c370e25db2a552231ca8wrowe }
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe#endif
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe}
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe/* flush all the translation blocks */
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe/* XXX: tb_flush is currently not thread safe */
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowevoid tb_flush(CPUState *env1)
f99d4fa2605925f385a184ba3789be3423690533wrowe{
f99d4fa2605925f385a184ba3789be3423690533wrowe CPUState *env;
72347cd608351452f99d5f4411d3e0c089d0293awrowe#ifdef VBOX
f99d4fa2605925f385a184ba3789be3423690533wrowe STAM_PROFILE_START(&env1->StatTbFlush, a);
f99d4fa2605925f385a184ba3789be3423690533wrowe#endif
f99d4fa2605925f385a184ba3789be3423690533wrowe#if defined(DEBUG_FLUSH)
f99d4fa2605925f385a184ba3789be3423690533wrowe printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
8dda6d649a6e3be9888cd49f1d8c703d3740a06fwrowe (unsigned long)(code_gen_ptr - code_gen_buffer),
8dda6d649a6e3be9888cd49f1d8c703d3740a06fwrowe nb_tbs, nb_tbs > 0 ?
8dda6d649a6e3be9888cd49f1d8c703d3740a06fwrowe ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
72347cd608351452f99d5f4411d3e0c089d0293awrowe#endif
f99d4fa2605925f385a184ba3789be3423690533wrowe if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size)
f99d4fa2605925f385a184ba3789be3423690533wrowe cpu_abort(env1, "Internal error: code buffer overflow\n");
60f8e9cbbfc2d757c71db17a35acb8566eebc0dawrowe
d0b14e6c6aabb4ed84bc056df6caeae146973c21wrowe nb_tbs = 0;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe for(env = first_cpu; env != NULL; env = env->next_cpu) {
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe }
a901f6f8425b207639fe2d1e22b102d96f8e64ffwrowe
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
752c83c97683b1fb9879ba874593a135155a043cwrowe page_flush_tb();
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe code_gen_ptr = code_gen_buffer;
a901f6f8425b207639fe2d1e22b102d96f8e64ffwrowe /* XXX: flush processor icache at this point if cache flush is
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe expensive */
bfd8c94a05d51f9af59fc84ed65b1336acdf95a8nd tb_flush_count++;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#ifdef VBOX
59f8d8a98364ee033d23dbb8e459858946aaecb3wrowe STAM_PROFILE_STOP(&env1->StatTbFlush, a);
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe#endif
fdc76d3c3f3fea82ba0f1d8af646f8ea5e4734a2wrowe}
f99d4fa2605925f385a184ba3789be3423690533wrowe
c2e5fcbd499ae7b5093d4877ff42e6c5ec74352bwrowe#ifdef DEBUG_TB_CHECK
1e83c8de3aa48b316b28057d53995272baf1260cwrowestatic void tb_invalidate_check(target_ulong address)
1e83c8de3aa48b316b28057d53995272baf1260cwrowe{
72347cd608351452f99d5f4411d3e0c089d0293awrowe TranslationBlock *tb;
1e83c8de3aa48b316b28057d53995272baf1260cwrowe int i;
72347cd608351452f99d5f4411d3e0c089d0293awrowe address &= TARGET_PAGE_MASK;
72347cd608351452f99d5f4411d3e0c089d0293awrowe for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
72347cd608351452f99d5f4411d3e0c089d0293awrowe for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
72347cd608351452f99d5f4411d3e0c089d0293awrowe if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
1e83c8de3aa48b316b28057d53995272baf1260cwrowe address >= tb->pc + tb->size)) {
c2e5fcbd499ae7b5093d4877ff42e6c5ec74352bwrowe printf("ERROR invalidate: address=%08lx PC=%08lx size=%04x\n",
c2e5fcbd499ae7b5093d4877ff42e6c5ec74352bwrowe address, (long)tb->pc, tb->size);
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe }
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe }
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe }
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe}
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowe
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowe/* verify that all the pages have correct rights for code */
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowestatic void tb_page_check(void)
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowe{
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowe TranslationBlock *tb;
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowe int i, flags1, flags2;
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowe
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowe for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowe for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowe flags1 = page_get_flags(tb->pc);
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowe flags2 = page_get_flags(tb->pc + tb->size - 1);
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowe if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowe printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowe (long)tb->pc, tb->size, flags1, flags2);
edf585d6f44e9019b3ab45be869d7d2ad23e5daewrowe }
edf585d6f44e9019b3ab45be869d7d2ad23e5daewrowe }
edf585d6f44e9019b3ab45be869d7d2ad23e5daewrowe }
edf585d6f44e9019b3ab45be869d7d2ad23e5daewrowe}
9fb3226780b297bcc320cb19cc3ec23194fac8e1wrowe
a19c94edefc000de60a6925b4ca15637e2f785f1wrowestatic void tb_jmp_check(TranslationBlock *tb)
a19c94edefc000de60a6925b4ca15637e2f785f1wrowe{
a19c94edefc000de60a6925b4ca15637e2f785f1wrowe TranslationBlock *tb1;
a19c94edefc000de60a6925b4ca15637e2f785f1wrowe unsigned int n1;
59f8d8a98364ee033d23dbb8e459858946aaecb3wrowe
a19c94edefc000de60a6925b4ca15637e2f785f1wrowe /* suppress any remaining jumps to this TB */
6bc96ef510ce100bfdeefd80b8f05c010373ed13wrowe tb1 = tb->jmp_first;
6bc96ef510ce100bfdeefd80b8f05c010373ed13wrowe for(;;) {
6bc96ef510ce100bfdeefd80b8f05c010373ed13wrowe n1 = (long)tb1 & 3;
6bc96ef510ce100bfdeefd80b8f05c010373ed13wrowe tb1 = (TranslationBlock *)((long)tb1 & ~3);
6bc96ef510ce100bfdeefd80b8f05c010373ed13wrowe if (n1 == 2)
6bc96ef510ce100bfdeefd80b8f05c010373ed13wrowe break;
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe tb1 = tb1->jmp_next[n1];
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe }
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe /* check end of list */
0bcc003d275c6b0a9060d43be89762b218cbc2c7wrowe if (tb1 != tb) {
c4101f4a8c23dce65b76e5c41b0fca7fadeb2941wrowe printf("ERROR: jmp_list from 0x%08lx\n", (long)tb);
424303d026faabb9e9752310911d00fa737b603awrowe }
424303d026faabb9e9752310911d00fa737b603awrowe}
424303d026faabb9e9752310911d00fa737b603awrowe
c4101f4a8c23dce65b76e5c41b0fca7fadeb2941wrowe#endif
f99d4fa2605925f385a184ba3789be3423690533wrowe
1f0a9798d1c29e1e0cbdb339a0262ba287a29ed4wrowe/* invalidate one TB */
1e83c8de3aa48b316b28057d53995272baf1260cwrowestatic inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
525973b478c06cd0e8c457ade5c378dcae7485d2wrowe int next_offset)
0b54189e53778165cf497165f6b04af200fab8cawrowe{
1e83c8de3aa48b316b28057d53995272baf1260cwrowe TranslationBlock *tb1;
22390e3a41c29735e7c138ab3ea50b876b82b0e6wrowe for(;;) {
22390e3a41c29735e7c138ab3ea50b876b82b0e6wrowe tb1 = *ptb;
e3c59608a643aac0e86a0e8cf2d62f8ef655337fwrowe if (tb1 == tb) {
e3c59608a643aac0e86a0e8cf2d62f8ef655337fwrowe *ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
break;
}
ptb = (TranslationBlock **)((char *)tb1 + next_offset);
}
}
static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
{
TranslationBlock *tb1;
unsigned int n1;
for(;;) {
tb1 = *ptb;
n1 = (long)tb1 & 3;
tb1 = (TranslationBlock *)((long)tb1 & ~3);
if (tb1 == tb) {
*ptb = tb1->page_next[n1];
break;
}
ptb = &tb1->page_next[n1];
}
}
static inline void tb_jmp_remove(TranslationBlock *tb, int n)
{
TranslationBlock *tb1, **ptb;
unsigned int n1;
ptb = &tb->jmp_next[n];
tb1 = *ptb;
if (tb1) {
/* find tb(n) in circular list */
for(;;) {
tb1 = *ptb;
n1 = (long)tb1 & 3;
tb1 = (TranslationBlock *)((long)tb1 & ~3);
if (n1 == n && tb1 == tb)
break;
if (n1 == 2) {
ptb = &tb1->jmp_first;
} else {
ptb = &tb1->jmp_next[n1];
}
}
/* now we can suppress tb(n) from the list */
*ptb = tb->jmp_next[n];
tb->jmp_next[n] = NULL;
}
}
/* reset the jump entry 'n' of a TB so that it is not chained to
another TB */
static inline void tb_reset_jump(TranslationBlock *tb, int n)
{
tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
}
void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
{
CPUState *env;
PageDesc *p;
unsigned int h, n1;
target_phys_addr_t phys_pc;
TranslationBlock *tb1, *tb2;
/* remove the TB from the hash list */
phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
h = tb_phys_hash_func(phys_pc);
tb_remove(&tb_phys_hash[h], tb,
offsetof(TranslationBlock, phys_hash_next));
/* remove the TB from the page list */
if (tb->page_addr[0] != page_addr) {
p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
tb_page_remove(&p->first_tb, tb);
invalidate_page_bitmap(p);
}
if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
tb_page_remove(&p->first_tb, tb);
invalidate_page_bitmap(p);
}
tb_invalidated_flag = 1;
/* remove the TB from the hash list */
h = tb_jmp_cache_hash_func(tb->pc);
for(env = first_cpu; env != NULL; env = env->next_cpu) {
if (env->tb_jmp_cache[h] == tb)
env->tb_jmp_cache[h] = NULL;
}
/* suppress this TB from the two jump lists */
tb_jmp_remove(tb, 0);
tb_jmp_remove(tb, 1);
/* suppress any remaining jumps to this TB */
tb1 = tb->jmp_first;
for(;;) {
n1 = (long)tb1 & 3;
if (n1 == 2)
break;
tb1 = (TranslationBlock *)((long)tb1 & ~3);
tb2 = tb1->jmp_next[n1];
tb_reset_jump(tb1, n1);
tb1->jmp_next[n1] = NULL;
tb1 = tb2;
}
tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
tb_phys_invalidate_count++;
}
#ifdef VBOX
void tb_invalidate_virt(CPUState *env, uint32_t eip)
{
# if 1
tb_flush(env);
# else
uint8_t *cs_base, *pc;
unsigned int flags, h, phys_pc;
TranslationBlock *tb, **ptb;
flags = env->hflags;
flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
cs_base = env->segs[R_CS].base;
pc = cs_base + eip;
tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
flags);
if(tb)
{
# ifdef DEBUG
printf("invalidating TB (%08X) at %08X\n", tb, eip);
# endif
tb_invalidate(tb);
//Note: this will leak TBs, but the whole cache will be flushed
// when it happens too often
tb->pc = 0;
tb->cs_base = 0;
tb->flags = 0;
}
# endif
}
# ifdef VBOX_STRICT
/**
* Gets the page offset.
*/
unsigned long get_phys_page_offset(target_ulong addr)
{
PhysPageDesc *p = phys_page_find(addr >> TARGET_PAGE_BITS);
return p ? p->phys_offset : 0;
}
# endif /* VBOX_STRICT */
#endif /* VBOX */
static inline void set_bits(uint8_t *tab, int start, int len)
{
int end, mask, end1;
end = start + len;
tab += start >> 3;
mask = 0xff << (start & 7);
if ((start & ~7) == (end & ~7)) {
if (start < end) {
mask &= ~(0xff << (end & 7));
*tab |= mask;
}
} else {
*tab++ |= mask;
start = (start + 8) & ~7;
end1 = end & ~7;
while (start < end1) {
*tab++ = 0xff;
start += 8;
}
if (start < end) {
mask = ~(0xff << (end & 7));
*tab |= mask;
}
}
}
static void build_page_bitmap(PageDesc *p)
{
int n, tb_start, tb_end;
TranslationBlock *tb;
p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8);
if (!p->code_bitmap)
return;
tb = p->first_tb;
while (tb != NULL) {
n = (long)tb & 3;
tb = (TranslationBlock *)((long)tb & ~3);
/* NOTE: this is subtle as a TB may span two physical pages */
if (n == 0) {
/* NOTE: tb_end may be after the end of the page, but
it is not a problem */
tb_start = tb->pc & ~TARGET_PAGE_MASK;
tb_end = tb_start + tb->size;
if (tb_end > TARGET_PAGE_SIZE)
tb_end = TARGET_PAGE_SIZE;
} else {
tb_start = 0;
tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
}
set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
tb = tb->page_next[n];
}
}
TranslationBlock *tb_gen_code(CPUState *env,
target_ulong pc, target_ulong cs_base,
int flags, int cflags)
{
TranslationBlock *tb;
uint8_t *tc_ptr;
target_ulong phys_pc, phys_page2, virt_page2;
int code_gen_size;
phys_pc = get_phys_addr_code(env, pc);
tb = tb_alloc(pc);
if (!tb) {
/* flush must be done */
tb_flush(env);
/* cannot fail at this point */
tb = tb_alloc(pc);
/* Don't forget to invalidate previous TB info. */
tb_invalidated_flag = 1;
}
tc_ptr = code_gen_ptr;
tb->tc_ptr = tc_ptr;
tb->cs_base = cs_base;
tb->flags = flags;
tb->cflags = cflags;
cpu_gen_code(env, tb, &code_gen_size);
code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
/* check next page if needed */
virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
phys_page2 = -1;
if ((pc & TARGET_PAGE_MASK) != virt_page2) {
phys_page2 = get_phys_addr_code(env, virt_page2);
}
tb_link_phys(tb, phys_pc, phys_page2);
return tb;
}
/* invalidate all TBs which intersect with the target physical page
starting in range [start;end[. NOTE: start and end must refer to
the same physical page. 'is_cpu_write_access' should be true if called
from a real cpu write access: the virtual CPU will exit the current
TB if code is modified inside this TB. */
void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
int is_cpu_write_access)
{
int n, current_tb_modified, current_tb_not_found, current_flags;
CPUState *env = cpu_single_env;
PageDesc *p;
TranslationBlock *tb, *tb_next, *current_tb, *saved_tb;
target_ulong tb_start, tb_end;
target_ulong current_pc, current_cs_base;
p = page_find(start >> TARGET_PAGE_BITS);
if (!p)
return;
if (!p->code_bitmap &&
++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
is_cpu_write_access) {
/* build code bitmap */
build_page_bitmap(p);
}
/* we remove all the TBs in the range [start, end[ */
/* XXX: see if in some cases it could be faster to invalidate all the code */
current_tb_not_found = is_cpu_write_access;
current_tb_modified = 0;
current_tb = NULL; /* avoid warning */
current_pc = 0; /* avoid warning */
current_cs_base = 0; /* avoid warning */
current_flags = 0; /* avoid warning */
tb = p->first_tb;
while (tb != NULL) {
n = (long)tb & 3;
tb = (TranslationBlock *)((long)tb & ~3);
tb_next = tb->page_next[n];
/* NOTE: this is subtle as a TB may span two physical pages */
if (n == 0) {
/* NOTE: tb_end may be after the end of the page, but
it is not a problem */
tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
tb_end = tb_start + tb->size;
} else {
tb_start = tb->page_addr[1];
tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
}
if (!(tb_end <= start || tb_start >= end)) {
#ifdef TARGET_HAS_PRECISE_SMC
if (current_tb_not_found) {
current_tb_not_found = 0;
current_tb = NULL;
if (env->mem_io_pc) {
/* now we have a real cpu fault */
current_tb = tb_find_pc(env->mem_io_pc);
}
}
if (current_tb == tb &&
(current_tb->cflags & CF_COUNT_MASK) != 1) {
/* If we are modifying the current TB, we must stop
its execution. We could be more precise by checking
that the modification is after the current PC, but it
would require a specialized function to partially
restore the CPU state */
current_tb_modified = 1;
cpu_restore_state(current_tb, env,
env->mem_io_pc, NULL);
#if defined(TARGET_I386)
current_flags = env->hflags;
current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
current_cs_base = (target_ulong)env->segs[R_CS].base;
current_pc = current_cs_base + env->eip;
#else
#error unsupported CPU
#endif
}
#endif /* TARGET_HAS_PRECISE_SMC */
/* we need to do that to handle the case where a signal
occurs while doing tb_phys_invalidate() */
saved_tb = NULL;
if (env) {
saved_tb = env->current_tb;
env->current_tb = NULL;
}
tb_phys_invalidate(tb, -1);
if (env) {
env->current_tb = saved_tb;
if (env->interrupt_request && env->current_tb)
cpu_interrupt(env, env->interrupt_request);
}
}
tb = tb_next;
}
#if !defined(CONFIG_USER_ONLY)
/* if no code remaining, no need to continue to use slow writes */
if (!p->first_tb) {
invalidate_page_bitmap(p);
if (is_cpu_write_access) {
tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
}
}
#endif
#ifdef TARGET_HAS_PRECISE_SMC
if (current_tb_modified) {
/* we generate a block containing just the instruction
modifying the memory. It will ensure that it cannot modify
itself */
env->current_tb = NULL;
tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
cpu_resume_from_signal(env, NULL);
}
#endif
}
/* len must be <= 8 and start must be a multiple of len */
static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
{
PageDesc *p;
int offset, b;
#if 0
if (1) {
if (loglevel) {
fprintf(logfile, "modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
cpu_single_env->mem_io_vaddr, len,
cpu_single_env->eip,
cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
}
}
#endif
p = page_find(start >> TARGET_PAGE_BITS);
if (!p)
return;
if (p->code_bitmap) {
offset = start & ~TARGET_PAGE_MASK;
b = p->code_bitmap[offset >> 3] >> (offset & 7);
if (b & ((1 << len) - 1))
goto do_invalidate;
} else {
do_invalidate:
tb_invalidate_phys_page_range(start, start + len, 1);
}
}
#if !defined(CONFIG_SOFTMMU)
static void tb_invalidate_phys_page(target_phys_addr_t addr,
unsigned long pc, void *puc)
{
int n, current_flags, current_tb_modified;
target_ulong current_pc, current_cs_base;
PageDesc *p;
TranslationBlock *tb, *current_tb;
#ifdef TARGET_HAS_PRECISE_SMC
CPUState *env = cpu_single_env;
#endif
addr &= TARGET_PAGE_MASK;
p = page_find(addr >> TARGET_PAGE_BITS);
if (!p)
return;
tb = p->first_tb;
current_tb_modified = 0;
current_tb = NULL;
current_pc = 0; /* avoid warning */
current_cs_base = 0; /* avoid warning */
current_flags = 0; /* avoid warning */
#ifdef TARGET_HAS_PRECISE_SMC
if (tb && pc != 0) {
current_tb = tb_find_pc(pc);
}
#endif
while (tb != NULL) {
n = (long)tb & 3;
tb = (TranslationBlock *)((long)tb & ~3);
#ifdef TARGET_HAS_PRECISE_SMC
if (current_tb == tb &&
(current_tb->cflags & CF_COUNT_MASK) != 1) {
/* If we are modifying the current TB, we must stop
its execution. We could be more precise by checking
that the modification is after the current PC, but it
would require a specialized function to partially
restore the CPU state */
current_tb_modified = 1;
cpu_restore_state(current_tb, env, pc, puc);
#if defined(TARGET_I386)
current_flags = env->hflags;
current_flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
current_cs_base = (target_ulong)env->segs[R_CS].base;
current_pc = current_cs_base + env->eip;
#else
#error unsupported CPU
#endif
}
#endif /* TARGET_HAS_PRECISE_SMC */
tb_phys_invalidate(tb, addr);
tb = tb->page_next[n];
}
p->first_tb = NULL;
#ifdef TARGET_HAS_PRECISE_SMC
if (current_tb_modified) {
/* we generate a block containing just the instruction
modifying the memory. It will ensure that it cannot modify
itself */
env->current_tb = NULL;
tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
cpu_resume_from_signal(env, puc);
}
#endif
}
#endif
/* add the tb in the target page and protect it if necessary */
static inline void tb_alloc_page(TranslationBlock *tb,
unsigned int n, target_ulong page_addr)
{
PageDesc *p;
TranslationBlock *last_first_tb;
tb->page_addr[n] = page_addr;
p = page_find_alloc(page_addr >> TARGET_PAGE_BITS);
tb->page_next[n] = p->first_tb;
last_first_tb = p->first_tb;
p->first_tb = (TranslationBlock *)((long)tb | n);
invalidate_page_bitmap(p);
#if defined(TARGET_HAS_SMC) || 1
#if defined(CONFIG_USER_ONLY)
if (p->flags & PAGE_WRITE) {
target_ulong addr;
PageDesc *p2;
int prot;
/* force the host page as non writable (writes will have a
page fault + mprotect overhead) */
page_addr &= qemu_host_page_mask;
prot = 0;
for(addr = page_addr; addr < page_addr + qemu_host_page_size;
addr += TARGET_PAGE_SIZE) {
p2 = page_find (addr >> TARGET_PAGE_BITS);
if (!p2)
continue;
prot |= p2->flags;
p2->flags &= ~PAGE_WRITE;
page_get_flags(addr);
}
mprotect(g2h(page_addr), qemu_host_page_size,
(prot & PAGE_BITS) & ~PAGE_WRITE);
#ifdef DEBUG_TB_INVALIDATE
printf("protecting code page: 0x" TARGET_FMT_lx "\n",
page_addr);
#endif
}
#else
/* if some code is already present, then the pages are already
protected. So we handle the case where only the first TB is
allocated in a physical page */
if (!last_first_tb) {
tlb_protect_code(page_addr);
}
#endif
#endif /* TARGET_HAS_SMC */
}
/* Allocate a new translation block. Flush the translation buffer if
too many translation blocks or too much generated code. */
TranslationBlock *tb_alloc(target_ulong pc)
{
TranslationBlock *tb;
if (nb_tbs >= code_gen_max_blocks ||
#ifndef VBOX
(code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size)
#else
(code_gen_ptr - code_gen_buffer) >= (int)code_gen_buffer_max_size)
#endif
return NULL;
tb = &tbs[nb_tbs++];
tb->pc = pc;
tb->cflags = 0;
return tb;
}
void tb_free(TranslationBlock *tb)
{
/* In practice this is mostly used for single use temporary TB
Ignore the hard cases and just back up if this TB happens to
be the last one generated. */
if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
code_gen_ptr = tb->tc_ptr;
nb_tbs--;
}
}
/* add a new TB and link it to the physical page tables. phys_page2 is
(-1) to indicate that only one page contains the TB. */
void tb_link_phys(TranslationBlock *tb,
target_ulong phys_pc, target_ulong phys_page2)
{
unsigned int h;
TranslationBlock **ptb;
/* Grab the mmap lock to stop another thread invalidating this TB
before we are done. */
mmap_lock();
/* add in the physical hash table */
h = tb_phys_hash_func(phys_pc);
ptb = &tb_phys_hash[h];
tb->phys_hash_next = *ptb;
*ptb = tb;
/* add in the page list */
tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
if (phys_page2 != -1)
tb_alloc_page(tb, 1, phys_page2);
else
tb->page_addr[1] = -1;
tb->jmp_first = (TranslationBlock *)((long)tb | 2);
tb->jmp_next[0] = NULL;
tb->jmp_next[1] = NULL;
/* init original jump addresses */
if (tb->tb_next_offset[0] != 0xffff)
tb_reset_jump(tb, 0);
if (tb->tb_next_offset[1] != 0xffff)
tb_reset_jump(tb, 1);
#ifdef DEBUG_TB_CHECK
tb_page_check();
#endif
mmap_unlock();
}
/* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
tb[1].tc_ptr. Return NULL if not found */
TranslationBlock *tb_find_pc(unsigned long tc_ptr)
{
int m_min, m_max, m;
unsigned long v;
TranslationBlock *tb;
if (nb_tbs <= 0)
return NULL;
if (tc_ptr < (unsigned long)code_gen_buffer ||
tc_ptr >= (unsigned long)code_gen_ptr)
return NULL;
/* binary search (cf Knuth) */
m_min = 0;
m_max = nb_tbs - 1;
while (m_min <= m_max) {
m = (m_min + m_max) >> 1;
tb = &tbs[m];
v = (unsigned long)tb->tc_ptr;
if (v == tc_ptr)
return tb;
else if (tc_ptr < v) {
m_max = m - 1;
} else {
m_min = m + 1;
}
}
return &tbs[m_max];
}
static void tb_reset_jump_recursive(TranslationBlock *tb);
static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
{
TranslationBlock *tb1, *tb_next, **ptb;
unsigned int n1;
tb1 = tb->jmp_next[n];
if (tb1 != NULL) {
/* find head of list */
for(;;) {
n1 = (long)tb1 & 3;
tb1 = (TranslationBlock *)((long)tb1 & ~3);
if (n1 == 2)
break;
tb1 = tb1->jmp_next[n1];
}
/* we are now sure now that tb jumps to tb1 */
tb_next = tb1;
/* remove tb from the jmp_first list */
ptb = &tb_next->jmp_first;
for(;;) {
tb1 = *ptb;
n1 = (long)tb1 & 3;
tb1 = (TranslationBlock *)((long)tb1 & ~3);
if (n1 == n && tb1 == tb)
break;
ptb = &tb1->jmp_next[n1];
}
*ptb = tb->jmp_next[n];
tb->jmp_next[n] = NULL;
/* suppress the jump to next tb in generated code */
tb_reset_jump(tb, n);
/* suppress jumps in the tb on which we could have jumped */
tb_reset_jump_recursive(tb_next);
}
}
static void tb_reset_jump_recursive(TranslationBlock *tb)
{
tb_reset_jump_recursive2(tb, 0);
tb_reset_jump_recursive2(tb, 1);
}
#if defined(TARGET_HAS_ICE)
static void breakpoint_invalidate(CPUState *env, target_ulong pc)
{
target_phys_addr_t addr;
target_ulong pd;
ram_addr_t ram_addr;
PhysPageDesc *p;
addr = cpu_get_phys_page_debug(env, pc);
p = phys_page_find(addr >> TARGET_PAGE_BITS);
if (!p) {
pd = IO_MEM_UNASSIGNED;
} else {
pd = p->phys_offset;
}
ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
}
#endif
/* Add a watchpoint. */
int cpu_watchpoint_insert(CPUState *env, target_ulong addr, int type)
{
int i;
for (i = 0; i < env->nb_watchpoints; i++) {
if (addr == env->watchpoint[i].vaddr)
return 0;
}
if (env->nb_watchpoints >= MAX_WATCHPOINTS)
return -1;
i = env->nb_watchpoints++;
env->watchpoint[i].vaddr = addr;
env->watchpoint[i].type = type;
tlb_flush_page(env, addr);
/* FIXME: This flush is needed because of the hack to make memory ops
terminate the TB. It can be removed once the proper IO trap and
re-execute bits are in. */
tb_flush(env);
return i;
}
/* Remove a watchpoint. */
int cpu_watchpoint_remove(CPUState *env, target_ulong addr)
{
int i;
for (i = 0; i < env->nb_watchpoints; i++) {
if (addr == env->watchpoint[i].vaddr) {
env->nb_watchpoints--;
env->watchpoint[i] = env->watchpoint[env->nb_watchpoints];
tlb_flush_page(env, addr);
return 0;
}
}
return -1;
}
/* Remove all watchpoints. */
void cpu_watchpoint_remove_all(CPUState *env) {
int i;
for (i = 0; i < env->nb_watchpoints; i++) {
tlb_flush_page(env, env->watchpoint[i].vaddr);
}
env->nb_watchpoints = 0;
}
/* add a breakpoint. EXCP_DEBUG is returned by the CPU loop if a
breakpoint is reached */
int cpu_breakpoint_insert(CPUState *env, target_ulong pc)
{
#if defined(TARGET_HAS_ICE)
int i;
for(i = 0; i < env->nb_breakpoints; i++) {
if (env->breakpoints[i] == pc)
return 0;
}
if (env->nb_breakpoints >= MAX_BREAKPOINTS)
return -1;
env->breakpoints[env->nb_breakpoints++] = pc;
breakpoint_invalidate(env, pc);
return 0;
#else
return -1;
#endif
}
/* remove all breakpoints */
void cpu_breakpoint_remove_all(CPUState *env) {
#if defined(TARGET_HAS_ICE)
int i;
for(i = 0; i < env->nb_breakpoints; i++) {
breakpoint_invalidate(env, env->breakpoints[i]);
}
env->nb_breakpoints = 0;
#endif
}
/* remove a breakpoint */
int cpu_breakpoint_remove(CPUState *env, target_ulong pc)
{
#if defined(TARGET_HAS_ICE)
int i;
for(i = 0; i < env->nb_breakpoints; i++) {
if (env->breakpoints[i] == pc)
goto found;
}
return -1;
found:
env->nb_breakpoints--;
if (i < env->nb_breakpoints)
env->breakpoints[i] = env->breakpoints[env->nb_breakpoints];
breakpoint_invalidate(env, pc);
return 0;
#else
return -1;
#endif
}
/* enable or disable single step mode. EXCP_DEBUG is returned by the
CPU loop after each instruction */
void cpu_single_step(CPUState *env, int enabled)
{
#if defined(TARGET_HAS_ICE)
if (env->singlestep_enabled != enabled) {
env->singlestep_enabled = enabled;
/* must flush all the translated code to avoid inconsistancies */
/* XXX: only flush what is necessary */
tb_flush(env);
}
#endif
}
#ifndef VBOX
/* enable or disable low levels log */
void cpu_set_log(int log_flags)
{
loglevel = log_flags;
if (loglevel && !logfile) {
logfile = fopen(logfilename, log_append ? "a" : "w");
if (!logfile) {
perror(logfilename);
_exit(1);
}
#if !defined(CONFIG_SOFTMMU)
/* must avoid mmap() usage of glibc by setting a buffer "by hand" */
{
static char logfile_buf[4096];
setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
}
#else
setvbuf(logfile, NULL, _IOLBF, 0);
#endif
log_append = 1;
}
if (!loglevel && logfile) {
fclose(logfile);
logfile = NULL;
}
}
void cpu_set_log_filename(const char *filename)
{
logfilename = strdup(filename);
if (logfile) {
fclose(logfile);
logfile = NULL;
}
cpu_set_log(loglevel);
}
#endif /* !VBOX */
/* mask must never be zero, except for A20 change call */
void cpu_interrupt(CPUState *env, int mask)
{
#if !defined(USE_NPTL)
TranslationBlock *tb;
static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
#endif
int old_mask;
old_mask = env->interrupt_request;
#ifdef VBOX
VM_ASSERT_EMT(env->pVM);
ASMAtomicOrS32((int32_t volatile *)&env->interrupt_request, mask);
#else /* !VBOX */
/* FIXME: This is probably not threadsafe. A different thread could
be in the middle of a read-modify-write operation. */
env->interrupt_request |= mask;
#endif /* !VBOX */
#if defined(USE_NPTL)
/* FIXME: TB unchaining isn't SMP safe. For now just ignore the
problem and hope the cpu will stop of its own accord. For userspace
emulation this often isn't actually as bad as it sounds. Often
signals are used primarily to interrupt blocking syscalls. */
#else
if (use_icount) {
env->icount_decr.u16.high = 0xffff;
#ifndef CONFIG_USER_ONLY
/* CPU_INTERRUPT_EXIT isn't a real interrupt. It just means
an async event happened and we need to process it. */
if (!can_do_io(env)
&& (mask & ~(old_mask | CPU_INTERRUPT_EXIT)) != 0) {
cpu_abort(env, "Raised interrupt while not in I/O function");
}
#endif
} else {
tb = env->current_tb;
/* if the cpu is currently executing code, we must unlink it and
all the potentially executing TB */
if (tb && !testandset(&interrupt_lock)) {
env->current_tb = NULL;
tb_reset_jump_recursive(tb);
resetlock(&interrupt_lock);
}
}
#endif
}
void cpu_reset_interrupt(CPUState *env, int mask)
{
#ifdef VBOX
/*
* Note: the current implementation can be executed by another thread without problems; make sure this remains true
* for future changes!
*/
ASMAtomicAndS32((int32_t volatile *)&env->interrupt_request, ~mask);
#else /* !VBOX */
env->interrupt_request &= ~mask;
#endif /* !VBOX */
}
#ifndef VBOX
CPULogItem cpu_log_items[] = {
{ CPU_LOG_TB_OUT_ASM, "out_asm",
"show generated host assembly code for each compiled TB" },
{ CPU_LOG_TB_IN_ASM, "in_asm",
"show target assembly code for each compiled TB" },
{ CPU_LOG_TB_OP, "op",
"show micro ops for each compiled TB" },
{ CPU_LOG_TB_OP_OPT, "op_opt",
"show micro ops "
#ifdef TARGET_I386
"before eflags optimization and "
#endif
"after liveness analysis" },
{ CPU_LOG_INT, "int",
"show interrupts/exceptions in short format" },
{ CPU_LOG_EXEC, "exec",
"show trace before each executed TB (lots of logs)" },
{ CPU_LOG_TB_CPU, "cpu",
"show CPU state before block translation" },
#ifdef TARGET_I386
{ CPU_LOG_PCALL, "pcall",
"show protected mode far calls/returns/exceptions" },
#endif
#ifdef DEBUG_IOPORT
{ CPU_LOG_IOPORT, "ioport",
"show all i/o ports accesses" },
#endif
{ 0, NULL, NULL },
};
static int cmp1(const char *s1, int n, const char *s2)
{
if (strlen(s2) != n)
return 0;
return memcmp(s1, s2, n) == 0;
}
/* takes a comma separated list of log masks. Return 0 if error. */
int cpu_str_to_log_mask(const char *str)
{
const CPULogItem *item;
int mask;
const char *p, *p1;
p = str;
mask = 0;
for(;;) {
p1 = strchr(p, ',');
if (!p1)
p1 = p + strlen(p);
if(cmp1(p,p1-p,"all")) {
for(item = cpu_log_items; item->mask != 0; item++) {
mask |= item->mask;
}
} else {
for(item = cpu_log_items; item->mask != 0; item++) {
if (cmp1(p, p1 - p, item->name))
goto found;
}
return 0;
}
found:
mask |= item->mask;
if (*p1 != ',')
break;
p = p1 + 1;
}
return mask;
}
#endif /* !VBOX */
#ifndef VBOX /* VBOX: we have our own routine. */
void cpu_abort(CPUState *env, const char *fmt, ...)
{
va_list ap;
va_list ap2;
va_start(ap, fmt);
va_copy(ap2, ap);
fprintf(stderr, "qemu: fatal: ");
vfprintf(stderr, fmt, ap);
fprintf(stderr, "\n");
#ifdef TARGET_I386
cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
#else
cpu_dump_state(env, stderr, fprintf, 0);
#endif
if (logfile) {
fprintf(logfile, "qemu: fatal: ");
vfprintf(logfile, fmt, ap2);
fprintf(logfile, "\n");
#ifdef TARGET_I386
cpu_dump_state(env, logfile, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
#else
cpu_dump_state(env, logfile, fprintf, 0);
#endif
fflush(logfile);
fclose(logfile);
}
va_end(ap2);
va_end(ap);
abort();
}
#endif /* !VBOX */
#ifndef VBOX
CPUState *cpu_copy(CPUState *env)
{
CPUState *new_env = cpu_init(env->cpu_model_str);
/* preserve chaining and index */
CPUState *next_cpu = new_env->next_cpu;
int cpu_index = new_env->cpu_index;
memcpy(new_env, env, sizeof(CPUState));
new_env->next_cpu = next_cpu;
new_env->cpu_index = cpu_index;
return new_env;
}
#endif /* !VBOX */
#if !defined(CONFIG_USER_ONLY)
static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
{
unsigned int i;
/* Discard jump cache entries for any tb which might potentially
overlap the flushed page. */
i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
memset (&env->tb_jmp_cache[i], 0,
TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
i = tb_jmp_cache_hash_page(addr);
memset (&env->tb_jmp_cache[i], 0,
TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
#ifdef VBOX
/* inform raw mode about TLB page flush */
remR3FlushPage(env, addr);
#endif /* VBOX */
}
#ifdef VBOX
static CPUTLBEntry s_cputlb_empty_entry = {
.addr_read = -1,
.addr_write = -1,
.addr_code = -1,
.addend = -1,
};
#endif /* VBOX */
/* NOTE: if flush_global is true, also flush global entries (not
implemented yet) */
void tlb_flush(CPUState *env, int flush_global)
{
int i;
#if defined(DEBUG_TLB)
printf("tlb_flush:\n");
#endif
/* must reset current TB so that interrupts cannot modify the
links while we are modifying them */
env->current_tb = NULL;
for(i = 0; i < CPU_TLB_SIZE; i++) {
#ifdef VBOX
int mmu_idx;
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry;
}
#else /* !VBOX */
env->tlb_table[0][i].addr_read = -1;
env->tlb_table[0][i].addr_write = -1;
env->tlb_table[0][i].addr_code = -1;
env->tlb_table[1][i].addr_read = -1;
env->tlb_table[1][i].addr_write = -1;
env->tlb_table[1][i].addr_code = -1;
#if (NB_MMU_MODES >= 3)
env->tlb_table[2][i].addr_read = -1;
env->tlb_table[2][i].addr_write = -1;
env->tlb_table[2][i].addr_code = -1;
#if (NB_MMU_MODES == 4)
env->tlb_table[3][i].addr_read = -1;
env->tlb_table[3][i].addr_write = -1;
env->tlb_table[3][i].addr_code = -1;
#endif
#endif
#endif /* !VBOX */
}
memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
#ifdef VBOX
/* inform raw mode about TLB flush */
remR3FlushTLB(env, flush_global);
#endif
#ifdef USE_KQEMU
if (env->kqemu_enabled) {
kqemu_flush(env, flush_global);
}
#endif
tlb_flush_count++;
}
static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
{
if (addr == (tlb_entry->addr_read &
(TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
addr == (tlb_entry->addr_write &
(TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
addr == (tlb_entry->addr_code &
(TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
tlb_entry->addr_read = -1;
tlb_entry->addr_write = -1;
tlb_entry->addr_code = -1;
}
}
void tlb_flush_page(CPUState *env, target_ulong addr)
{
int i;
#if defined(DEBUG_TLB)
printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
#endif
/* must reset current TB so that interrupts cannot modify the
links while we are modifying them */
env->current_tb = NULL;
addr &= TARGET_PAGE_MASK;
i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
tlb_flush_entry(&env->tlb_table[0][i], addr);
tlb_flush_entry(&env->tlb_table[1][i], addr);
#if (NB_MMU_MODES >= 3)
tlb_flush_entry(&env->tlb_table[2][i], addr);
#if (NB_MMU_MODES == 4)
tlb_flush_entry(&env->tlb_table[3][i], addr);
#endif
#endif
tlb_flush_jmp_cache(env, addr);
#ifdef USE_KQEMU
if (env->kqemu_enabled) {
kqemu_flush_page(env, addr);
}
#endif
}
/* update the TLBs so that writes to code in the virtual page 'addr'
can be detected */
static void tlb_protect_code(ram_addr_t ram_addr)
{
cpu_physical_memory_reset_dirty(ram_addr,
ram_addr + TARGET_PAGE_SIZE,
CODE_DIRTY_FLAG);
#if defined(VBOX) && defined(REM_MONITOR_CODE_PAGES)
/** @todo Retest this? This function has changed... */
remR3ProtectCode(cpu_single_env, ram_addr);
#endif
}
/* update the TLB so that writes in physical page 'phys_addr' are no longer
tested for self modifying code */
static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
target_ulong vaddr)
{
#ifdef VBOX
if (RT_LIKELY((ram_addr >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
#endif
phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;
}
static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
unsigned long start, unsigned long length)
{
unsigned long addr;
#ifdef VBOX
if (start & 3)
return;
#endif
if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
if ((addr - start) < length) {
tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY;
}
}
}
void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
int dirty_flags)
{
CPUState *env;
unsigned long length, start1;
int i, mask, len;
uint8_t *p;
start &= TARGET_PAGE_MASK;
end = TARGET_PAGE_ALIGN(end);
length = end - start;
if (length == 0)
return;
len = length >> TARGET_PAGE_BITS;
#ifdef USE_KQEMU
/* XXX: should not depend on cpu context */
env = first_cpu;
if (env->kqemu_enabled) {
ram_addr_t addr;
addr = start;
for(i = 0; i < len; i++) {
kqemu_set_notdirty(env, addr);
addr += TARGET_PAGE_SIZE;
}
}
#endif
mask = ~dirty_flags;
p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
#ifdef VBOX
if (RT_LIKELY((start >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
#endif
for(i = 0; i < len; i++)
p[i] &= mask;
/* we modify the TLB cache so that the dirty bit will be set again
when accessing the range */
#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
start1 = start;
#elif !defined(VBOX)
start1 = start + (unsigned long)phys_ram_base;
#else
start1 = (unsigned long)remR3TlbGCPhys2Ptr(first_cpu, start, 1 /*fWritable*/); /** @todo page replacing (sharing or read only) may cause trouble, fix interface/whatever. */
#endif
for(env = first_cpu; env != NULL; env = env->next_cpu) {
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_reset_dirty_range(&env->tlb_table[0][i], start1, length);
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_reset_dirty_range(&env->tlb_table[1][i], start1, length);
#if (NB_MMU_MODES >= 3)
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length);
#if (NB_MMU_MODES == 4)
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length);
#endif
#endif
}
}
#ifndef VBOX
int cpu_physical_memory_set_dirty_tracking(int enable)
{
in_migration = enable;
return 0;
}
int cpu_physical_memory_get_dirty_tracking(void)
{
return in_migration;
}
#endif
#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
DECLINLINE(void) tlb_update_dirty(CPUTLBEntry *tlb_entry, target_phys_addr_t phys_addend)
#else
static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
#endif
{
ram_addr_t ram_addr;
if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
/* RAM case */
#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
#elif !defined(VBOX)
ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) +
tlb_entry->addend - (unsigned long)phys_ram_base;
#else
Assert(phys_addend != -1);
ram_addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + phys_addend;
#endif
if (!cpu_physical_memory_is_dirty(ram_addr)) {
tlb_entry->addr_write |= TLB_NOTDIRTY;
}
}
}
/* update the TLB according to the current state of the dirty bits */
void cpu_tlb_update_dirty(CPUState *env)
{
int i;
#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_update_dirty(&env->tlb_table[0][i], env->phys_addends[0][i]);
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_update_dirty(&env->tlb_table[1][i], env->phys_addends[1][i]);
#if (NB_MMU_MODES >= 3)
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_update_dirty(&env->tlb_table[2][i], env->phys_addends[2][i]);
#if (NB_MMU_MODES == 4)
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_update_dirty(&env->tlb_table[3][i], env->phys_addends[3][i]);
#endif
#endif
#else /* VBOX */
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_update_dirty(&env->tlb_table[0][i]);
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_update_dirty(&env->tlb_table[1][i]);
#if (NB_MMU_MODES >= 3)
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_update_dirty(&env->tlb_table[2][i]);
#if (NB_MMU_MODES == 4)
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_update_dirty(&env->tlb_table[3][i]);
#endif
#endif
#endif /* VBOX */
}
static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
{
if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY))
tlb_entry->addr_write = vaddr;
}
/* update the TLB corresponding to virtual page vaddr
so that it is no longer dirty */
static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
{
int i;
vaddr &= TARGET_PAGE_MASK;
i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
tlb_set_dirty1(&env->tlb_table[0][i], vaddr);
tlb_set_dirty1(&env->tlb_table[1][i], vaddr);
#if (NB_MMU_MODES >= 3)
tlb_set_dirty1(&env->tlb_table[2][i], vaddr);
#if (NB_MMU_MODES == 4)
tlb_set_dirty1(&env->tlb_table[3][i], vaddr);
#endif
#endif
}
/* add a new TLB entry. At most one entry for a given virtual address
is permitted. Return 0 if OK or 2 if the page could not be mapped
(can only happen in non SOFTMMU mode for I/O pages or pages
conflicting with the host address space). */
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
target_phys_addr_t paddr, int prot,
int mmu_idx, int is_softmmu)
{
PhysPageDesc *p;
unsigned long pd;
unsigned int index;
target_ulong address;
target_ulong code_address;
target_phys_addr_t addend;
int ret;
CPUTLBEntry *te;
int i;
target_phys_addr_t iotlb;
#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
int read_mods = 0, write_mods = 0, code_mods = 0;
#endif
p = phys_page_find(paddr >> TARGET_PAGE_BITS);
if (!p) {
pd = IO_MEM_UNASSIGNED;
} else {
pd = p->phys_offset;
}
#if defined(DEBUG_TLB)
printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",
vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);
#endif
ret = 0;
address = vaddr;
if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
/* IO memory case (romd handled later) */
address |= TLB_MMIO;
}
#if defined(VBOX) && defined(REM_PHYS_ADDR_IN_TLB)
addend = pd & TARGET_PAGE_MASK;
#elif !defined(VBOX)
addend = (unsigned long)phys_ram_base + (pd & TARGET_PAGE_MASK);
#else
/** @todo this is racing the phys_page_find call above since it may register
* a new chunk of memory... */
addend = (unsigned long)remR3TlbGCPhys2Ptr(env,
pd & TARGET_PAGE_MASK,
!!(prot & PAGE_WRITE));
#endif
if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
/* Normal RAM. */
iotlb = pd & TARGET_PAGE_MASK;
if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
iotlb |= IO_MEM_NOTDIRTY;
else
iotlb |= IO_MEM_ROM;
} else {
/* IO handlers are currently passed a phsical address.
It would be nice to pass an offset from the base address
of that region. This would avoid having to special case RAM,
and avoid full address decoding in every device.
We can't use the high bits of pd for this because
IO_MEM_ROMD uses these as a ram address. */
iotlb = (pd & ~TARGET_PAGE_MASK) + paddr;
}
code_address = address;
#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
if (addend & 0x3)
{
if (addend & 0x2)
{
/* catch write */
if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM)
write_mods |= TLB_MMIO;
}
else if (addend & 0x1)
{
/* catch all */
if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM)
{
read_mods |= TLB_MMIO;
write_mods |= TLB_MMIO;
code_mods |= TLB_MMIO;
}
}
if ((iotlb & ~TARGET_PAGE_MASK) == 0)
iotlb = env->pVM->rem.s.iHandlerMemType + paddr;
addend &= ~(target_ulong)0x3;
}
#endif
/* Make accesses to pages with watchpoints go via the
watchpoint trap routines. */
for (i = 0; i < env->nb_watchpoints; i++) {
if (vaddr == (env->watchpoint[i].vaddr & TARGET_PAGE_MASK)) {
iotlb = io_mem_watch + paddr;
/* TODO: The memory case can be optimized by not trapping
reads of pages with a write breakpoint. */
address |= TLB_MMIO;
}
}
index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
env->iotlb[mmu_idx][index] = iotlb - vaddr;
te = &env->tlb_table[mmu_idx][index];
te->addend = addend - vaddr;
if (prot & PAGE_READ) {
te->addr_read = address;
} else {
te->addr_read = -1;
}
if (prot & PAGE_EXEC) {
te->addr_code = code_address;
} else {
te->addr_code = -1;
}
if (prot & PAGE_WRITE) {
if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
(pd & IO_MEM_ROMD)) {
/* Write access calls the I/O callback. */
te->addr_write = address | TLB_MMIO;
} else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
!cpu_physical_memory_is_dirty(pd)) {
te->addr_write = address | TLB_NOTDIRTY;
} else {
te->addr_write = address;
}
} else {
te->addr_write = -1;
}
#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
if (prot & PAGE_READ)
te->addr_read |= read_mods;
if (prot & PAGE_EXEC)
te->addr_code |= code_mods;
if (prot & PAGE_WRITE)
te->addr_write |= write_mods;
env->phys_addends[mmu_idx][index] = (pd & TARGET_PAGE_MASK)- vaddr;
#endif
#ifdef VBOX
/* inform raw mode about TLB page change */
remR3FlushPage(env, vaddr);
#endif
return ret;
}
#else
void tlb_flush(CPUState *env, int flush_global)
{
}
void tlb_flush_page(CPUState *env, target_ulong addr)
{
}
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
target_phys_addr_t paddr, int prot,
int mmu_idx, int is_softmmu)
{
return 0;
}
#ifndef VBOX
/* dump memory mappings */
void page_dump(FILE *f)
{
unsigned long start, end;
int i, j, prot, prot1;
PageDesc *p;
fprintf(f, "%-8s %-8s %-8s %s\n",
"start", "end", "size", "prot");
start = -1;
end = -1;
prot = 0;
for(i = 0; i <= L1_SIZE; i++) {
if (i < L1_SIZE)
p = l1_map[i];
else
p = NULL;
for(j = 0;j < L2_SIZE; j++) {
if (!p)
prot1 = 0;
else
prot1 = p[j].flags;
if (prot1 != prot) {
end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS);
if (start != -1) {
fprintf(f, "%08lx-%08lx %08lx %c%c%c\n",
start, end, end - start,
prot & PAGE_READ ? 'r' : '-',
prot & PAGE_WRITE ? 'w' : '-',
prot & PAGE_EXEC ? 'x' : '-');
}
if (prot1 != 0)
start = end;
else
start = -1;
prot = prot1;
}
if (!p)
break;
}
}
}
#endif /* !VBOX */
int page_get_flags(target_ulong address)
{
PageDesc *p;
p = page_find(address >> TARGET_PAGE_BITS);
if (!p)
return 0;
return p->flags;
}
/* modify the flags of a page and invalidate the code if
necessary. The flag PAGE_WRITE_ORG is positionned automatically
depending on PAGE_WRITE */
void page_set_flags(target_ulong start, target_ulong end, int flags)
{
PageDesc *p;
target_ulong addr;
/* mmap_lock should already be held. */
start = start & TARGET_PAGE_MASK;
end = TARGET_PAGE_ALIGN(end);
if (flags & PAGE_WRITE)
flags |= PAGE_WRITE_ORG;
#ifdef VBOX
AssertMsgFailed(("We shouldn't be here, and if we should, we must have an env to do the proper locking!\n"));
#endif
for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
p = page_find_alloc(addr >> TARGET_PAGE_BITS);
/* We may be called for host regions that are outside guest
address space. */
if (!p)
return;
/* if the write protection is set, then we invalidate the code
inside */
if (!(p->flags & PAGE_WRITE) &&
(flags & PAGE_WRITE) &&
p->first_tb) {
tb_invalidate_phys_page(addr, 0, NULL);
}
p->flags = flags;
}
}
int page_check_range(target_ulong start, target_ulong len, int flags)
{
PageDesc *p;
target_ulong end;
target_ulong addr;
end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
start = start & TARGET_PAGE_MASK;
if( end < start )
/* we've wrapped around */
return -1;
for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
p = page_find(addr >> TARGET_PAGE_BITS);
if( !p )
return -1;
if( !(p->flags & PAGE_VALID) )
return -1;
if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
return -1;
if (flags & PAGE_WRITE) {
if (!(p->flags & PAGE_WRITE_ORG))
return -1;
/* unprotect the page if it was put read-only because it
contains translated code */
if (!(p->flags & PAGE_WRITE)) {
if (!page_unprotect(addr, 0, NULL))
return -1;
}
return 0;
}
}
return 0;
}
/* called from signal handler: invalidate the code and unprotect the
page. Return TRUE if the fault was succesfully handled. */
int page_unprotect(target_ulong address, unsigned long pc, void *puc)
{
unsigned int page_index, prot, pindex;
PageDesc *p, *p1;
target_ulong host_start, host_end, addr;
/* Technically this isn't safe inside a signal handler. However we
know this only ever happens in a synchronous SEGV handler, so in
practice it seems to be ok. */
mmap_lock();
host_start = address & qemu_host_page_mask;
page_index = host_start >> TARGET_PAGE_BITS;
p1 = page_find(page_index);
if (!p1) {
mmap_unlock();
return 0;
}
host_end = host_start + qemu_host_page_size;
p = p1;
prot = 0;
for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) {
prot |= p->flags;
p++;
}
/* if the page was really writable, then we change its
protection back to writable */
if (prot & PAGE_WRITE_ORG) {
pindex = (address - host_start) >> TARGET_PAGE_BITS;
if (!(p1[pindex].flags & PAGE_WRITE)) {
mprotect((void *)g2h(host_start), qemu_host_page_size,
(prot & PAGE_BITS) | PAGE_WRITE);
p1[pindex].flags |= PAGE_WRITE;
/* and since the content will be modified, we must invalidate
the corresponding translated code. */
tb_invalidate_phys_page(address, pc, puc);
#ifdef DEBUG_TB_CHECK
tb_invalidate_check(address);
#endif
mmap_unlock();
return 1;
}
}
mmap_unlock();
return 0;
}
static inline void tlb_set_dirty(CPUState *env,
unsigned long addr, target_ulong vaddr)
{
}
#endif /* defined(CONFIG_USER_ONLY) */
#if !defined(CONFIG_USER_ONLY)
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
ram_addr_t memory);
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
ram_addr_t orig_memory);
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
need_subpage) \
do { \
if (addr > start_addr) \
start_addr2 = 0; \
else { \
start_addr2 = start_addr & ~TARGET_PAGE_MASK; \
if (start_addr2 > 0) \
need_subpage = 1; \
} \
\
if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \
end_addr2 = TARGET_PAGE_SIZE - 1; \
else { \
end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
if (end_addr2 < TARGET_PAGE_SIZE - 1) \
need_subpage = 1; \
} \
} while (0)
/* register physical memory. 'size' must be a multiple of the target
page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
io memory page */
void cpu_register_physical_memory(target_phys_addr_t start_addr,
ram_addr_t size,
ram_addr_t phys_offset)
{
target_phys_addr_t addr, end_addr;
PhysPageDesc *p;
CPUState *env;
ram_addr_t orig_size = size;
void *subpage;
#ifdef USE_KQEMU
/* XXX: should not depend on cpu context */
env = first_cpu;
if (env->kqemu_enabled) {
kqemu_set_phys_mem(start_addr, size, phys_offset);
}
#endif
size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
end_addr = start_addr + (target_phys_addr_t)size;
for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
p = phys_page_find(addr >> TARGET_PAGE_BITS);
if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
ram_addr_t orig_memory = p->phys_offset;
target_phys_addr_t start_addr2, end_addr2;
int need_subpage = 0;
CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
need_subpage);
if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
if (!(orig_memory & IO_MEM_SUBPAGE)) {
subpage = subpage_init((addr & TARGET_PAGE_MASK),
&p->phys_offset, orig_memory);
} else {
subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
>> IO_MEM_SHIFT];
}
subpage_register(subpage, start_addr2, end_addr2, phys_offset);
} else {
p->phys_offset = phys_offset;
if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
(phys_offset & IO_MEM_ROMD))
phys_offset += TARGET_PAGE_SIZE;
}
} else {
p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
p->phys_offset = phys_offset;
if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
(phys_offset & IO_MEM_ROMD))
phys_offset += TARGET_PAGE_SIZE;
else {
target_phys_addr_t start_addr2, end_addr2;
int need_subpage = 0;
CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
end_addr2, need_subpage);
if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
subpage = subpage_init((addr & TARGET_PAGE_MASK),
&p->phys_offset, IO_MEM_UNASSIGNED);
subpage_register(subpage, start_addr2, end_addr2,
phys_offset);
}
}
}
}
/* since each CPU stores ram addresses in its TLB cache, we must
reset the modified entries */
/* XXX: slow ! */
for(env = first_cpu; env != NULL; env = env->next_cpu) {
tlb_flush(env, 1);
}
}
/* XXX: temporary until new memory mapping API */
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
{
PhysPageDesc *p;
p = phys_page_find(addr >> TARGET_PAGE_BITS);
if (!p)
return IO_MEM_UNASSIGNED;
return p->phys_offset;
}
#ifndef VBOX
/* XXX: better than nothing */
ram_addr_t qemu_ram_alloc(ram_addr_t size)
{
ram_addr_t addr;
if ((phys_ram_alloc_offset + size) > phys_ram_size) {
fprintf(stderr, "Not enough memory (requested_size = %" PRIu64 ", max memory = %" PRIu64 ")\n",
(uint64_t)size, (uint64_t)phys_ram_size);
abort();
}
addr = phys_ram_alloc_offset;
phys_ram_alloc_offset = TARGET_PAGE_ALIGN(phys_ram_alloc_offset + size);
return addr;
}
void qemu_ram_free(ram_addr_t addr)
{
}
#endif /* !VBOX */
static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
#endif
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
do_unassigned_access(addr, 0, 0, 0, 1);
#endif
return 0;
}
static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
#endif
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
do_unassigned_access(addr, 0, 0, 0, 2);
#endif
return 0;
}
static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
#endif
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
do_unassigned_access(addr, 0, 0, 0, 4);
#endif
return 0;
}
static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
#endif
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
do_unassigned_access(addr, 1, 0, 0, 1);
#endif
}
static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
#endif
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
do_unassigned_access(addr, 1, 0, 0, 2);
#endif
}
static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
#endif
#if defined(TARGET_SPARC) || defined(TARGET_CRIS)
do_unassigned_access(addr, 1, 0, 0, 4);
#endif
}
static CPUReadMemoryFunc *unassigned_mem_read[3] = {
unassigned_mem_readb,
unassigned_mem_readw,
unassigned_mem_readl,
};
static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
unassigned_mem_writeb,
unassigned_mem_writew,
unassigned_mem_writel,
};
static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
uint32_t val)
{
int dirty_flags;
#ifdef VBOX
if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
dirty_flags = 0xff;
else
#endif /* VBOX */
dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
if (!(dirty_flags & CODE_DIRTY_FLAG)) {
#if !defined(CONFIG_USER_ONLY)
tb_invalidate_phys_page_fast(ram_addr, 1);
# ifdef VBOX
if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
dirty_flags = 0xff;
else
# endif /* VBOX */
dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
#endif
}
#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
remR3PhysWriteU8(ram_addr, val);
#else
stb_p(phys_ram_base + ram_addr, val);
#endif
#ifdef USE_KQEMU
if (cpu_single_env->kqemu_enabled &&
(dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
kqemu_modify_page(cpu_single_env, ram_addr);
#endif
dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
#ifdef VBOX
if (RT_LIKELY((ram_addr >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
#endif /* !VBOX */
phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
/* we remove the notdirty callback only if the code has been
flushed */
if (dirty_flags == 0xff)
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
}
static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
uint32_t val)
{
int dirty_flags;
#ifdef VBOX
if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
dirty_flags = 0xff;
else
#endif /* VBOX */
dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
if (!(dirty_flags & CODE_DIRTY_FLAG)) {
#if !defined(CONFIG_USER_ONLY)
tb_invalidate_phys_page_fast(ram_addr, 2);
# ifdef VBOX
if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
dirty_flags = 0xff;
else
# endif /* VBOX */
dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
#endif
}
#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
remR3PhysWriteU16(ram_addr, val);
#else
stw_p(phys_ram_base + ram_addr, val);
#endif
#ifdef USE_KQEMU
if (cpu_single_env->kqemu_enabled &&
(dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
kqemu_modify_page(cpu_single_env, ram_addr);
#endif
dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
#ifdef VBOX
if (RT_LIKELY((ram_addr >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
#endif
phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
/* we remove the notdirty callback only if the code has been
flushed */
if (dirty_flags == 0xff)
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
}
static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
uint32_t val)
{
int dirty_flags;
#ifdef VBOX
if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
dirty_flags = 0xff;
else
#endif /* VBOX */
dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
if (!(dirty_flags & CODE_DIRTY_FLAG)) {
#if !defined(CONFIG_USER_ONLY)
tb_invalidate_phys_page_fast(ram_addr, 4);
# ifdef VBOX
if (RT_UNLIKELY((ram_addr >> TARGET_PAGE_BITS) >= phys_ram_dirty_size))
dirty_flags = 0xff;
else
# endif /* VBOX */
dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
#endif
}
#if defined(VBOX) && !defined(REM_PHYS_ADDR_IN_TLB)
remR3PhysWriteU32(ram_addr, val);
#else
stl_p(phys_ram_base + ram_addr, val);
#endif
#ifdef USE_KQEMU
if (cpu_single_env->kqemu_enabled &&
(dirty_flags & KQEMU_MODIFY_PAGE_MASK) != KQEMU_MODIFY_PAGE_MASK)
kqemu_modify_page(cpu_single_env, ram_addr);
#endif
dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
#ifdef VBOX
if (RT_LIKELY((ram_addr >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
#endif
phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
/* we remove the notdirty callback only if the code has been
flushed */
if (dirty_flags == 0xff)
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
}
static CPUReadMemoryFunc *error_mem_read[3] = {
NULL, /* never used */
NULL, /* never used */
NULL, /* never used */
};
static CPUWriteMemoryFunc *notdirty_mem_write[3] = {
notdirty_mem_writeb,
notdirty_mem_writew,
notdirty_mem_writel,
};
/* Generate a debug exception if a watchpoint has been hit. */
static void check_watchpoint(int offset, int flags)
{
CPUState *env = cpu_single_env;
target_ulong vaddr;
int i;
vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
for (i = 0; i < env->nb_watchpoints; i++) {
if (vaddr == env->watchpoint[i].vaddr
&& (env->watchpoint[i].type & flags)) {
env->watchpoint_hit = i + 1;
cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
break;
}
}
}
/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
so these check for a hit then pass through to the normal out-of-line
phys routines. */
static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_READ);
return ldub_phys(addr);
}
static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_READ);
return lduw_phys(addr);
}
static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_READ);
return ldl_phys(addr);
}
static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_WRITE);
stb_phys(addr, val);
}
static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_WRITE);
stw_phys(addr, val);
}
static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, PAGE_WRITE);
stl_phys(addr, val);
}
static CPUReadMemoryFunc *watch_mem_read[3] = {
watch_mem_readb,
watch_mem_readw,
watch_mem_readl,
};
static CPUWriteMemoryFunc *watch_mem_write[3] = {
watch_mem_writeb,
watch_mem_writew,
watch_mem_writel,
};
static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
unsigned int len)
{
uint32_t ret;
unsigned int idx;
idx = SUBPAGE_IDX(addr - mmio->base);
#if defined(DEBUG_SUBPAGE)
printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
mmio, len, addr, idx);
#endif
ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len], addr);
return ret;
}
static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
uint32_t value, unsigned int len)
{
unsigned int idx;
idx = SUBPAGE_IDX(addr - mmio->base);
#if defined(DEBUG_SUBPAGE)
printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
mmio, len, addr, idx, value);
#endif
(**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len], addr, value);
}
static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return subpage_readlen(opaque, addr, 0);
}
static void subpage_writeb (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
#endif
subpage_writelen(opaque, addr, value, 0);
}
static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return subpage_readlen(opaque, addr, 1);
}
static void subpage_writew (void *opaque, target_phys_addr_t addr,
uint32_t value)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
#endif
subpage_writelen(opaque, addr, value, 1);
}
static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return subpage_readlen(opaque, addr, 2);
}
static void subpage_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
#endif
subpage_writelen(opaque, addr, value, 2);
}
static CPUReadMemoryFunc *subpage_read[] = {
&subpage_readb,
&subpage_readw,
&subpage_readl,
};
static CPUWriteMemoryFunc *subpage_write[] = {
&subpage_writeb,
&subpage_writew,
&subpage_writel,
};
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
ram_addr_t memory)
{
int idx, eidx;
unsigned int i;
if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
return -1;
idx = SUBPAGE_IDX(start);
eidx = SUBPAGE_IDX(end);
#if defined(DEBUG_SUBPAGE)
printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %d\n", __func__,
mmio, start, end, idx, eidx, memory);
#endif
memory >>= IO_MEM_SHIFT;
for (; idx <= eidx; idx++) {
for (i = 0; i < 4; i++) {
if (io_mem_read[memory][i]) {
mmio->mem_read[idx][i] = &io_mem_read[memory][i];
mmio->opaque[idx][0][i] = io_mem_opaque[memory];
}
if (io_mem_write[memory][i]) {
mmio->mem_write[idx][i] = &io_mem_write[memory][i];
mmio->opaque[idx][1][i] = io_mem_opaque[memory];
}
}
}
return 0;
}
static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
ram_addr_t orig_memory)
{
subpage_t *mmio;
int subpage_memory;
mmio = qemu_mallocz(sizeof(subpage_t));
if (mmio != NULL) {
mmio->base = base;
subpage_memory = cpu_register_io_memory(0, subpage_read, subpage_write, mmio);
#if defined(DEBUG_SUBPAGE)
printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
mmio, base, TARGET_PAGE_SIZE, subpage_memory);
#endif
*phys = subpage_memory | IO_MEM_SUBPAGE;
subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory);
}
return mmio;
}
static void io_mem_init(void)
{
cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, error_mem_read, unassigned_mem_write, NULL);
cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, error_mem_read, notdirty_mem_write, NULL);
io_mem_nb = 5;
io_mem_watch = cpu_register_io_memory(0, watch_mem_read,
watch_mem_write, NULL);
#ifndef VBOX /* VBOX: we do this later when the RAM is allocated. */
/* alloc dirty bits array */
phys_ram_dirty = qemu_vmalloc(phys_ram_size >> TARGET_PAGE_BITS);
memset(phys_ram_dirty, 0xff, phys_ram_size >> TARGET_PAGE_BITS);
#endif /* !VBOX */
}
/* mem_read and mem_write are arrays of functions containing the
function to access byte (index 0), word (index 1) and dword (index
2). Functions can be omitted with a NULL function pointer. The
registered functions may be modified dynamically later.
If io_index is non zero, the corresponding io zone is
modified. If it is zero, a new io zone is allocated. The return
value can be used with cpu_register_physical_memory(). (-1) is
returned if error. */
int cpu_register_io_memory(int io_index,
CPUReadMemoryFunc **mem_read,
CPUWriteMemoryFunc **mem_write,
void *opaque)
{
int i, subwidth = 0;
if (io_index <= 0) {
if (io_mem_nb >= IO_MEM_NB_ENTRIES)
return -1;
io_index = io_mem_nb++;
} else {
if (io_index >= IO_MEM_NB_ENTRIES)
return -1;
}
for(i = 0;i < 3; i++) {
if (!mem_read[i] || !mem_write[i])
subwidth = IO_MEM_SUBWIDTH;
io_mem_read[io_index][i] = mem_read[i];
io_mem_write[io_index][i] = mem_write[i];
}
io_mem_opaque[io_index] = opaque;
return (io_index << IO_MEM_SHIFT) | subwidth;
}
CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index)
{
return io_mem_write[io_index >> IO_MEM_SHIFT];
}
CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index)
{
return io_mem_read[io_index >> IO_MEM_SHIFT];
}
#endif /* !defined(CONFIG_USER_ONLY) */
/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
int len, int is_write)
{
int l, flags;
target_ulong page;
void * p;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
l = (page + TARGET_PAGE_SIZE) - addr;
if (l > len)
l = len;
flags = page_get_flags(page);
if (!(flags & PAGE_VALID))
return;
if (is_write) {
if (!(flags & PAGE_WRITE))
return;
/* XXX: this code should not depend on lock_user */
if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
/* FIXME - should this return an error rather than just fail? */
return;
memcpy(p, buf, l);
unlock_user(p, addr, l);
} else {
if (!(flags & PAGE_READ))
return;
/* XXX: this code should not depend on lock_user */
if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
/* FIXME - should this return an error rather than just fail? */
return;
memcpy(buf, p, l);
unlock_user(p, addr, 0);
}
len -= l;
buf += l;
addr += l;
}
}
#else
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
int len, int is_write)
{
int l, io_index;
uint8_t *ptr;
uint32_t val;
target_phys_addr_t page;
unsigned long pd;
PhysPageDesc *p;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
l = (page + TARGET_PAGE_SIZE) - addr;
if (l > len)
l = len;
p = phys_page_find(page >> TARGET_PAGE_BITS);
if (!p) {
pd = IO_MEM_UNASSIGNED;
} else {
pd = p->phys_offset;
}
if (is_write) {
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
/* XXX: could force cpu_single_env to NULL to avoid
potential bugs */
if (l >= 4 && ((addr & 3) == 0)) {
/* 32 bit write access */
#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
val = ldl_p(buf);
#else
val = *(const uint32_t *)buf;
#endif
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
l = 4;
} else if (l >= 2 && ((addr & 1) == 0)) {
/* 16 bit write access */
#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
val = lduw_p(buf);
#else
val = *(const uint16_t *)buf;
#endif
io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
l = 2;
} else {
/* 8 bit write access */
#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
val = ldub_p(buf);
#else
val = *(const uint8_t *)buf;
#endif
io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val);
l = 1;
}
} else {
unsigned long addr1;
addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
/* RAM case */
#ifdef VBOX
remR3PhysWrite(addr1, buf, l); NOREF(ptr);
#else
ptr = phys_ram_base + addr1;
memcpy(ptr, buf, l);
#endif
if (!cpu_physical_memory_is_dirty(addr1)) {
/* invalidate code */
tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
/* set dirty bit */
#ifdef VBOX
if (RT_LIKELY((addr1 >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
#endif
phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
(0xff & ~CODE_DIRTY_FLAG);
}
}
} else {
if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
!(pd & IO_MEM_ROMD)) {
/* I/O case */
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (l >= 4 && ((addr & 3) == 0)) {
/* 32 bit read access */
val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
stl_p(buf, val);
#else
*(uint32_t *)buf = val;
#endif
l = 4;
} else if (l >= 2 && ((addr & 1) == 0)) {
/* 16 bit read access */
val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
stw_p(buf, val);
#else
*(uint16_t *)buf = val;
#endif
l = 2;
} else {
/* 8 bit read access */
val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr);
#if !defined(VBOX) || !defined(REM_PHYS_ADDR_IN_TLB)
stb_p(buf, val);
#else
*(uint8_t *)buf = val;
#endif
l = 1;
}
} else {
/* RAM case */
#ifdef VBOX
remR3PhysRead((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), buf, l); NOREF(ptr);
#else
ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
(addr & ~TARGET_PAGE_MASK);
memcpy(buf, ptr, l);
#endif
}
}
len -= l;
buf += l;
addr += l;
}
}
#ifndef VBOX
/* used for ROM loading : can write in RAM and ROM */
void cpu_physical_memory_write_rom(target_phys_addr_t addr,
const uint8_t *buf, int len)
{
int l;
uint8_t *ptr;
target_phys_addr_t page;
unsigned long pd;
PhysPageDesc *p;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
l = (page + TARGET_PAGE_SIZE) - addr;
if (l > len)
l = len;
p = phys_page_find(page >> TARGET_PAGE_BITS);
if (!p) {
pd = IO_MEM_UNASSIGNED;
} else {
pd = p->phys_offset;
}
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
(pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
!(pd & IO_MEM_ROMD)) {
/* do nothing */
} else {
unsigned long addr1;
addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
/* ROM/RAM case */
ptr = phys_ram_base + addr1;
memcpy(ptr, buf, l);
}
len -= l;
buf += l;
addr += l;
}
}
#endif /* !VBOX */
/* warning: addr must be aligned */
uint32_t ldl_phys(target_phys_addr_t addr)
{
int io_index;
uint8_t *ptr;
uint32_t val;
unsigned long pd;
PhysPageDesc *p;
p = phys_page_find(addr >> TARGET_PAGE_BITS);
if (!p) {
pd = IO_MEM_UNASSIGNED;
} else {
pd = p->phys_offset;
}
if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
!(pd & IO_MEM_ROMD)) {
/* I/O case */
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
} else {
/* RAM case */
#ifndef VBOX
ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
(addr & ~TARGET_PAGE_MASK);
val = ldl_p(ptr);
#else
val = remR3PhysReadU32((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK)); NOREF(ptr);
#endif
}
return val;
}
/* warning: addr must be aligned */
uint64_t ldq_phys(target_phys_addr_t addr)
{
int io_index;
uint8_t *ptr;
uint64_t val;
unsigned long pd;
PhysPageDesc *p;
p = phys_page_find(addr >> TARGET_PAGE_BITS);
if (!p) {
pd = IO_MEM_UNASSIGNED;
} else {
pd = p->phys_offset;
}
if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
!(pd & IO_MEM_ROMD)) {
/* I/O case */
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
#ifdef TARGET_WORDS_BIGENDIAN
val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
#else
val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
#endif
} else {
/* RAM case */
#ifndef VBOX
ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
(addr & ~TARGET_PAGE_MASK);
val = ldq_p(ptr);
#else
val = remR3PhysReadU64((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK)); NOREF(ptr);
#endif
}
return val;
}
/* XXX: optimize */
uint32_t ldub_phys(target_phys_addr_t addr)
{
uint8_t val;
cpu_physical_memory_read(addr, &val, 1);
return val;
}
/* XXX: optimize */
uint32_t lduw_phys(target_phys_addr_t addr)
{
uint16_t val;
cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
return tswap16(val);
}
/* warning: addr must be aligned. The ram page is not masked as dirty
and the code inside is not invalidated. It is useful if the dirty
bits are used to track modified PTEs */
void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
{
int io_index;
uint8_t *ptr;
unsigned long pd;
PhysPageDesc *p;
p = phys_page_find(addr >> TARGET_PAGE_BITS);
if (!p) {
pd = IO_MEM_UNASSIGNED;
} else {
pd = p->phys_offset;
}
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
} else {
#ifndef VBOX
unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
ptr = phys_ram_base + addr1;
stl_p(ptr, val);
#else
remR3PhysWriteU32((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), val); NOREF(ptr);
#endif
#ifndef VBOX
if (unlikely(in_migration)) {
if (!cpu_physical_memory_is_dirty(addr1)) {
/* invalidate code */
tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
/* set dirty bit */
phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
(0xff & ~CODE_DIRTY_FLAG);
}
}
#endif /* !VBOX */
}
}
void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
{
int io_index;
uint8_t *ptr;
unsigned long pd;
PhysPageDesc *p;
p = phys_page_find(addr >> TARGET_PAGE_BITS);
if (!p) {
pd = IO_MEM_UNASSIGNED;
} else {
pd = p->phys_offset;
}
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
#ifdef TARGET_WORDS_BIGENDIAN
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
#else
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
#endif
} else {
#ifndef VBOX
ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
(addr & ~TARGET_PAGE_MASK);
stq_p(ptr, val);
#else
remR3PhysWriteU64((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), val); NOREF(ptr);
#endif
}
}
/* warning: addr must be aligned */
void stl_phys(target_phys_addr_t addr, uint32_t val)
{
int io_index;
uint8_t *ptr;
unsigned long pd;
PhysPageDesc *p;
p = phys_page_find(addr >> TARGET_PAGE_BITS);
if (!p) {
pd = IO_MEM_UNASSIGNED;
} else {
pd = p->phys_offset;
}
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
} else {
unsigned long addr1;
addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
/* RAM case */
#ifndef VBOX
ptr = phys_ram_base + addr1;
stl_p(ptr, val);
#else
remR3PhysWriteU32((pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK), val); NOREF(ptr);
#endif
if (!cpu_physical_memory_is_dirty(addr1)) {
/* invalidate code */
tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
/* set dirty bit */
#ifdef VBOX
if (RT_LIKELY((addr1 >> TARGET_PAGE_BITS) < phys_ram_dirty_size))
#endif
phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
(0xff & ~CODE_DIRTY_FLAG);
}
}
}
/* XXX: optimize */
void stb_phys(target_phys_addr_t addr, uint32_t val)
{
uint8_t v = val;
cpu_physical_memory_write(addr, &v, 1);
}
/* XXX: optimize */
void stw_phys(target_phys_addr_t addr, uint32_t val)
{
uint16_t v = tswap16(val);
cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
}
/* XXX: optimize */
void stq_phys(target_phys_addr_t addr, uint64_t val)
{
val = tswap64(val);
cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
}
#endif
/* virtual memory access for debug */
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l;
target_phys_addr_t phys_addr;
target_ulong page;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
phys_addr = cpu_get_phys_page_debug(env, page);
/* if no physical page mapped, return an error */
if (phys_addr == -1)
return -1;
l = (page + TARGET_PAGE_SIZE) - addr;
if (l > len)
l = len;
cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK),
buf, l, is_write);
len -= l;
buf += l;
addr += l;
}
return 0;
}
/* in deterministic execution mode, instructions doing device I/Os
must be at the end of the TB */
void cpu_io_recompile(CPUState *env, void *retaddr)
{
TranslationBlock *tb;
uint32_t n, cflags;
target_ulong pc, cs_base;
uint64_t flags;
tb = tb_find_pc((unsigned long)retaddr);
if (!tb) {
cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
retaddr);
}
n = env->icount_decr.u16.low + tb->icount;
cpu_restore_state(tb, env, (unsigned long)retaddr, NULL);
/* Calculate how many instructions had been executed before the fault
occurred. */
n = n - env->icount_decr.u16.low;
/* Generate a new TB ending on the I/O insn. */
n++;
/* On MIPS and SH, delay slot instructions can only be restarted if
they were already the first instruction in the TB. If this is not
the first instruction in a TB then re-execute the preceding
branch. */
#if defined(TARGET_MIPS)
if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
env->active_tc.PC -= 4;
env->icount_decr.u16.low++;
env->hflags &= ~MIPS_HFLAG_BMASK;
}
#elif defined(TARGET_SH4)
if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
&& n > 1) {
env->pc -= 2;
env->icount_decr.u16.low++;
env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
}
#endif
/* This should never happen. */
if (n > CF_COUNT_MASK)
cpu_abort(env, "TB too big during recompile");
cflags = n | CF_LAST_IO;
pc = tb->pc;
cs_base = tb->cs_base;
flags = tb->flags;
tb_phys_invalidate(tb, -1);
/* FIXME: In theory this could raise an exception. In practice
we have already translated the block once so it's probably ok. */
tb_gen_code(env, pc, cs_base, flags, cflags);
/* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
the first in the TB) then we end up generating a whole new TB and
repeating the fault, which is horribly inefficient.
Better would be to execute just this insn uncached, or generate a
second new TB. */
cpu_resume_from_signal(env, NULL);
}
#ifndef VBOX
void dump_exec_info(FILE *f,
int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
{
int i, target_code_size, max_target_code_size;
int direct_jmp_count, direct_jmp2_count, cross_page;
TranslationBlock *tb;
target_code_size = 0;
max_target_code_size = 0;
cross_page = 0;
direct_jmp_count = 0;
direct_jmp2_count = 0;
for(i = 0; i < nb_tbs; i++) {
tb = &tbs[i];
target_code_size += tb->size;
if (tb->size > max_target_code_size)
max_target_code_size = tb->size;
if (tb->page_addr[1] != -1)
cross_page++;
if (tb->tb_next_offset[0] != 0xffff) {
direct_jmp_count++;
if (tb->tb_next_offset[1] != 0xffff) {
direct_jmp2_count++;
}
}
}
/* XXX: avoid using doubles ? */
cpu_fprintf(f, "Translation buffer state:\n");
cpu_fprintf(f, "gen code size %ld/%ld\n",
code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size);
cpu_fprintf(f, "TB count %d/%d\n",
nb_tbs, code_gen_max_blocks);
cpu_fprintf(f, "TB avg target size %d max=%d bytes\n",
nb_tbs ? target_code_size / nb_tbs : 0,
max_target_code_size);
cpu_fprintf(f, "TB avg host size %d bytes (expansion ratio: %0.1f)\n",
nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
cross_page,
nb_tbs ? (cross_page * 100) / nb_tbs : 0);
cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
direct_jmp_count,
nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
direct_jmp2_count,
nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
cpu_fprintf(f, "\nStatistics:\n");
cpu_fprintf(f, "TB flush count %d\n", tb_flush_count);
cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count);
tcg_dump_info(f, cpu_fprintf);
}
#endif /* !VBOX */
#if !defined(CONFIG_USER_ONLY)
#define MMUSUFFIX _cmmu
#define GETPC() NULL
#define env cpu_single_env
#define SOFTMMU_CODE_ACCESS
#define SHIFT 0
#include "softmmu_template.h"
#define SHIFT 1
#include "softmmu_template.h"
#define SHIFT 2
#include "softmmu_template.h"
#define SHIFT 3
#include "softmmu_template.h"
#undef env
#endif