cpu-defs.h revision 4af48bf7c72ef1e201c64bd475377b5af9d8e8a1
/*
* common defines for all CPUs
*
* Copyright (c) 2003 Fabrice Bellard
*
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
*/
/*
* Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
* other than GPL or LGPL is available it will apply instead, Oracle elects to use only
* the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
* a choice of LGPL license versions is made available with the language indicating
* that LGPLv2 or any later version may be used, or where a choice of which version
* of the LGPL is applied is otherwise unspecified.
*/
#ifndef CPU_DEFS_H
#define CPU_DEFS_H
#ifndef NEED_CPU_H
#endif
#include "config.h"
#include <setjmp.h>
#include <inttypes.h>
#include "osdep.h"
#include "sys-queue.h"
#ifndef TARGET_LONG_BITS
#endif
#ifndef TARGET_PHYS_ADDR_BITS
#if TARGET_LONG_BITS >= HOST_LONG_BITS
#else
#define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
#endif
#endif
/* target_ulong is the type of a virtual address */
#if TARGET_LONG_SIZE == 4
typedef int32_t target_long;
typedef uint32_t target_ulong;
#define TARGET_FMT_lx "%08x"
#define TARGET_FMT_ld "%d"
#define TARGET_FMT_lu "%u"
typedef int64_t target_long;
typedef uint64_t target_ulong;
#else
#endif
/* target_phys_addr_t is the type of a physical address (its size can
be different from 'target_ulong'). We have sizeof(target_phys_addr)
= max(sizeof(unsigned long),
sizeof(size_of_target_physical_address)) because we must pass a
host pointer to memory operations in some cases */
#if TARGET_PHYS_ADDR_BITS == 32
typedef uint32_t target_phys_addr_t;
#define TARGET_FMT_plx "%08x"
typedef uint64_t target_phys_addr_t;
#else
#endif
#ifdef VBOX
#endif /* VBOX */
#define TB_JMP_CACHE_BITS 12
/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
addresses on the same page. The top bits are the same. This allows
TLB invalidation to quickly clear a subset of the hash table. */
#define CPU_TLB_BITS 8
#define CPU_TLB_ENTRY_BITS 4
#else
#define CPU_TLB_ENTRY_BITS 5
#endif
typedef struct CPUTLBEntry {
/* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
go directly to ram.
bit 3 : indicates that the entry is invalid
bit 2..0 : zero
*/
/* Addend to virtual address to get physical address. IO accesses
use the corresponding iotlb value. */
#if TARGET_PHYS_ADDR_BITS == 64
/* on i386 Linux make sure it is aligned */
#else
#endif
/* padding to get a power of two size */
(sizeof(target_ulong) * 3 +
sizeof(target_phys_addr_t))];
} CPUTLBEntry;
#ifdef WORDS_BIGENDIAN
typedef struct icount_decr_u16 {
#else
typedef struct icount_decr_u16 {
#endif
struct kvm_run;
struct KVMState;
typedef struct CPUBreakpoint {
int flags; /* BP_* */
typedef struct CPUWatchpoint {
int flags; /* BP_* */
#define CPU_TEMP_BUF_NLONGS 128
#define CPU_COMMON \
/* soft mmu support */ \
/* in order to avoid passing too many arguments to the MMIO \
helpers, we store some rarely used information in the CPU \
context) */ \
unsigned long mem_io_pc; /* host pc at which the memory was \
accessed */ \
memory was accessed */ \
/* The meaning of the MMU modes is defined in the target code. */ \
/** addends for HVA -> GPA translations */ \
/* buffer for temporaries in the code generator */ \
long temp_buf[CPU_TEMP_BUF_NLONGS]; \
\
/* Number of cycles left, with interrupt flag in high bit. \
This allows a single read-compare-cbranch-write sequence to test \
for both decrementer underflow and exceptions. */ \
union { \
} icount_decr; \
\
/* from this point: preserved by CPU reset */ \
/* ice debug support */ \
int singlestep_enabled; \
\
\
struct GDBRegisterState *gdb_regs; \
\
/* Core interrupt code */ \
int exception_index; \
\
void *next_cpu; /* next CPU sharing TB cache */ \
int cpu_index; /* CPU index (informative) */ \
int running; /* Nonzero if cpu is currently running(usermode). */ \
/* user data */ \
void *opaque; \
\
const char *cpu_model_str; \
int kvm_fd;
#endif