cpu-defs.h revision 178d85b8274f9ac82fb553c80760bbbb4044401c
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * common defines for all CPUs
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * Copyright (c) 2003 Fabrice Bellard
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * This library is free software; you can redistribute it and/or
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * modify it under the terms of the GNU Lesser General Public
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * License as published by the Free Software Foundation; either
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * version 2 of the License, or (at your option) any later version.
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync * This library is distributed in the hope that it will be useful,
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * but WITHOUT ANY WARRANTY; without even the implied warranty of
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * Lesser General Public License for more details.
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * You should have received a copy of the GNU Lesser General Public
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * License along with this library; if not, write to the Free Software
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * a choice of LGPL license versions is made available with the language indicating
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * that LGPLv2 or any later version may be used, or where a choice of which version
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * of the LGPL is applied is otherwise unspecified.
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#error TARGET_LONG_BITS must be defined before including this header
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/* target_ulong is the type of a virtual address */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/* target_phys_addr_t is the type of a physical address (its size can
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync be different from 'target_ulong'). We have sizeof(target_phys_addr)
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync = max(sizeof(unsigned long),
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync sizeof(size_of_target_physical_address)) because we must pass a
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync host pointer to memory operations in some cases */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define EXCP_INTERRUPT 0x10000 /* async interruption */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define EXCP_HLT 0x10001 /* hlt instruction reached */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#if defined(VBOX)
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define EXCP_EXECUTE_RAW 0x11024 /* execute raw mode. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define EXCP_EXECUTE_HWACC 0x11025 /* execute hardware accelerated raw mode. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define EXCP_SINGLE_INSTR 0x11026 /* executed single instruction. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define EXCP_RC 0x11027 /* a EM rc was raised (VMR3Reset/Suspend/PowerOff). */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#endif /* VBOX */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync addresses on the same page. The top bits are the same. This allows
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync TLB invalidation to quickly clear a subset of the hash table. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync#if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsynctypedef struct CPUTLBEntry {
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync go directly to ram.
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync bit 3 : indicates that the entry is invalid
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync bit 2..0 : zero
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /* Addend to virtual address to get physical address. IO accesses
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync use the correcponding iotlb value. */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /* on i386 Linux make sure it is aligned */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync target_phys_addr_t addend __attribute__((aligned(8)));
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /* padding to get a power of two size */
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) +
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsynctypedef struct icount_decr_u16 {
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsynctypedef struct icount_decr_u16 {
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync struct TranslationBlock *current_tb; /* currently executing TB */ \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /* soft mmu support */ \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /* in order to avoid passing too many arguments to the MMIO \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync helpers, we store some rarely used information in the CPU \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync context) */ \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync unsigned long mem_io_pc; /* host pc at which the memory was \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync accessed */ \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync target_ulong mem_io_vaddr; /* target virtual addr at which the \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync memory was accessed */ \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /* The meaning of the MMU modes is defined in the target code. */ \
192a1d418422c3b5905dd2577527c07a8ed8b61evboxsync CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /** addends for HVA -> GPA translations */ \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync VBOX_ONLY(target_phys_addr_t phys_addends[NB_MMU_MODES][CPU_TLB_SIZE]); \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /* buffer for temporaries in the code generator */ \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync int64_t icount_extra; /* Instructions until next timer event. */ \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /* Number of cycles left, with interrupt flag in high bit. \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync This allows a single read-compare-cbranch-write sequence to test \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync for both decrementer underflow and exceptions. */ \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /* from this point: preserved by CPU reset */ \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /* ice debug support */ \
192a1d418422c3b5905dd2577527c07a8ed8b61evboxsync /* Core interrupt code */ \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync int running; /* Nonzero if cpu is currently running(usermode). */ \
809e0c4b84167932d92a1df4edcbab2edf0ddf25vboxsync /* user data */ \