4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsync/* CPU interfaces that are target indpendent. */
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsync#if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__)
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsync/* address in the RAM (different from a physical address) */
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsync/* memory API */
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsynctypedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsynctypedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncvoid cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncstatic inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsync cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsyncram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name,
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsyncram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size);
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsync/* This should only be used for ram local to a device. */
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsync/* This should not be used by devices. */
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsync#endif /* !VBOX */
81db31727ed27322c3f5e3bc40e71fe7fc54bf91vboxsyncint cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncvoid cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncstatic inline void cpu_physical_memory_read(target_phys_addr_t addr,
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncstatic inline void cpu_physical_memory_write(target_phys_addr_t addr,
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsync cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncvoid *cpu_physical_memory_map(target_phys_addr_t addr,
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncvoid cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncvoid *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsynctypedef struct CPUPhysMemoryClient CPUPhysMemoryClient;
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsync void (*set_memory)(struct CPUPhysMemoryClient *client,
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsync int (*sync_dirty_bitmap)(struct CPUPhysMemoryClient *client,
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsync int (*migration_log)(struct CPUPhysMemoryClient *client,
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsyncvoid cpu_register_phys_memory_client(CPUPhysMemoryClient *);
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsyncvoid cpu_unregister_phys_memory_client(CPUPhysMemoryClient *);
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsync/* Coalesced MMIO regions are areas where write operations can be reordered.
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsync * This usually implies that write operations are side-effect free. This allows
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsync * batching which can make a major impact on performance when using
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsync * virtualization.
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsyncvoid qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
cec22f4b94382f5ebee9d2f6b6df672689681e07vboxsyncvoid qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncvoid stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncvoid stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncvoid stb_phys(target_phys_addr_t addr, uint32_t val);
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncvoid stw_phys(target_phys_addr_t addr, uint32_t val);
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncvoid stl_phys(target_phys_addr_t addr, uint32_t val);
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncvoid stq_phys(target_phys_addr_t addr, uint64_t val);
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsyncvoid cpu_physical_memory_write_rom(target_phys_addr_t addr,
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsync#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsync#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsync/* Acts like a ROM when read and like a device when written. */
4c37c32b924cb13b821f9d2e01f42cabbd3d9cf9vboxsync#endif /* !CPU_COMMON_H */