VBoxCpuReport.cpp revision 4f9276b4c85a4617d08094484cc1d983791bbb16
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/* $Id$ */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** @file
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * VBoxCpuReport - Produces the basis for a CPU DB entry.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/*
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Copyright (C) 2013 Oracle Corporation
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * available from http://www.virtualbox.org. This file is free software;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * you can redistribute it and/or modify it under the terms of the GNU
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * General Public License (GPL) as published by the Free Software
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/*******************************************************************************
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync* Header Files *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync*******************************************************************************/
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/asm.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/asm-amd64-x86.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/buildconfig.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/ctype.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/file.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/getopt.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/initterm.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/message.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/mem.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/path.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/string.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/stream.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/symlink.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/thread.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <iprt/time.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <VBox/err.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <VBox/vmm/cpum.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#include <VBox/sup.h>
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/*******************************************************************************
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync* Structures and Typedefs *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync*******************************************************************************/
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** Write only register. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#define VBCPUREPMSR_F_WRITE_ONLY RT_BIT(0)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsynctypedef struct VBCPUREPMSR
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /** The first MSR register number. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uint32_t uMsr;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /** Flags (MSRREPORT_F_XXX). */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uint32_t fFlags;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /** The value we read, unless write-only. */
dbec828311ed2a5cf6fbc68fe4391d516ba4f92fvboxsync uint64_t uValue;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync} VBCPUREPMSR;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
5eb36887f6970e0033f63fa135f3bb8fbfd6059bvboxsync/*******************************************************************************
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync* Global Variables *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync*******************************************************************************/
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** The CPU vendor. Used by the MSR code. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic CPUMCPUVENDOR g_enmVendor = CPUMCPUVENDOR_INVALID;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** The CPU microarchitecture. Used by the MSR code. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic CPUMMICROARCH g_enmMicroarch = kCpumMicroarch_Invalid;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** Set if g_enmMicroarch indicates an Intel NetBurst CPU. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool g_fIntelNetBurst = false;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** The report stream. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic PRTSTREAM g_pReportOut;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** The debug stream. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic PRTSTREAM g_pDebugOut;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic void vbCpuRepDebug(const char *pszMsg, ...)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (g_pDebugOut)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync va_list va;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync va_start(va, pszMsg);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTStrmPrintfV(g_pDebugOut, pszMsg, va);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync va_end(va);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTStrmFlush(g_pDebugOut);
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync RTThreadSleep(1);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic void vbCpuRepPrintf(const char *pszMsg, ...)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync va_list va;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Output to report file, if requested. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (g_pReportOut)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync va_start(va, pszMsg);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTStrmPrintfV(g_pReportOut, pszMsg, va);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync va_end(va);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTStrmFlush(g_pReportOut);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Always print a copy of the report to standard out. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync va_start(va, pszMsg);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTStrmPrintfV(g_pStdOut, pszMsg, va);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync va_end(va);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTStrmFlush(g_pStdOut);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic int vbCpuRepMsrsAddOne(VBCPUREPMSR **ppaMsrs, uint32_t *pcMsrs,
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uint32_t uMsr, uint64_t uValue, uint32_t fFlags)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /*
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Grow the array?
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uint32_t cMsrs = *pcMsrs;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if ((cMsrs % 64) == 0)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync void *pvNew = RTMemRealloc(*ppaMsrs, (cMsrs + 64) * sizeof(**ppaMsrs));
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (!pvNew)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTMemFree(*ppaMsrs);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *ppaMsrs = NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *pcMsrs = 0;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return VERR_NO_MEMORY;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *ppaMsrs = (VBCPUREPMSR *)pvNew;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /*
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Add it.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync VBCPUREPMSR *pEntry = *ppaMsrs + cMsrs;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync pEntry->uMsr = uMsr;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync pEntry->fFlags = fFlags;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync pEntry->uValue = uValue;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *pcMsrs = cMsrs + 1;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return VINF_SUCCESS;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/**
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Returns the max physical address width as a number of bits.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @returns Bit count.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic uint8_t vbCpuRepGetPhysAddrWidth(void)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uint8_t cMaxWidth;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uint32_t cMaxExt = ASMCpuId_EAX(0x80000000);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (!ASMHasCpuId())
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync cMaxWidth = 32;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync else if (ASMIsValidExtRange(cMaxExt)&& cMaxExt >= 0x80000008)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync cMaxWidth = ASMCpuId_EAX(0x80000008) & 0xff;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync else if ( ASMIsValidStdRange(ASMCpuId_EAX(0))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PSE36))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync cMaxWidth = 36;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync else
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync cMaxWidth = 32;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return cMaxWidth;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool vbCpuRepSupportsPae(void)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return ASMHasCpuId()
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && ASMIsValidStdRange(ASMCpuId_EAX(0))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool vbCpuRepSupportsLongMode(void)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return ASMHasCpuId()
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && ASMIsValidExtRange(ASMCpuId_EAX(0x80000000))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool vbCpuRepSupportsNX(void)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return ASMHasCpuId()
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && ASMIsValidExtRange(ASMCpuId_EAX(0x80000000))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool vbCpuRepSupportsX2Apic(void)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return ASMHasCpuId()
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && ASMIsValidStdRange(ASMCpuId_EAX(0))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && (ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_X2APIC);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool msrProberWrite(uint32_t uMsr, uint64_t uValue)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync bool fGp;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync int rc = SUPR3MsrProberWrite(uMsr, NIL_RTCPUID, uValue, &fGp);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync AssertRC(rc);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RT_SUCCESS(rc) && !fGp;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool msrProberRead(uint32_t uMsr, uint64_t *puValue)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *puValue = 0;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync bool fGp;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync int rc = SUPR3MsrProberRead(uMsr, NIL_RTCPUID, puValue, &fGp);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync AssertRC(rc);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RT_SUCCESS(rc) && !fGp;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** Tries to modify the register by writing the original value to it. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool msrProberModifyNoChange(uint32_t uMsr)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync SUPMSRPROBERMODIFYRESULT Result;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, UINT64_MAX, 0, &Result);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RT_SUCCESS(rc)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !Result.fBeforeGp
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !Result.fModifyGp
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !Result.fAfterGp
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !Result.fRestoreGp;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** Tries to modify the register by writing zero to it. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool msrProberModifyZero(uint32_t uMsr)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync SUPMSRPROBERMODIFYRESULT Result;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, 0, 0, &Result);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RT_SUCCESS(rc)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !Result.fBeforeGp
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !Result.fModifyGp
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !Result.fAfterGp
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !Result.fRestoreGp;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/**
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Tries to modify each bit in the MSR and see if we can make it change.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @returns VBox status code.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param uMsr The MSR.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param pfIgnMask The ignore mask to update.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param pfGpMask The GP mask to update.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param fSkipMask Mask of bits to skip.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic int msrProberModifyBitChanges(uint32_t uMsr, uint64_t *pfIgnMask, uint64_t *pfGpMask, uint64_t fSkipMask)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync for (unsigned iBit = 0; iBit < 64; iBit++)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uint64_t fBitMask = RT_BIT_64(iBit);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (fBitMask & fSkipMask)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync continue;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Set it. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync SUPMSRPROBERMODIFYRESULT ResultSet;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, fBitMask, &ResultSet);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (RT_FAILURE(rc))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RTMsgErrorRc(rc, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, fBitMask, rc);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Clear it. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync SUPMSRPROBERMODIFYRESULT ResultClear;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, 0, &ResultClear);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (RT_FAILURE(rc))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RTMsgErrorRc(rc, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, 0, rc);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (ResultSet.fModifyGp || ResultClear.fModifyGp)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *pfGpMask |= fBitMask;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync else if ( ( ((ResultSet.uBefore ^ ResultSet.uAfter) & fBitMask) == 0
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !ResultSet.fBeforeGp
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !ResultSet.fAfterGp)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && ( ((ResultClear.uBefore ^ ResultClear.uAfter) & fBitMask) == 0
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !ResultClear.fBeforeGp
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !ResultClear.fAfterGp) )
78df65edff21c11c537f38e736707ea434ab5623vboxsync *pfIgnMask |= fBitMask;
78df65edff21c11c537f38e736707ea434ab5623vboxsync }
78df65edff21c11c537f38e736707ea434ab5623vboxsync
78df65edff21c11c537f38e736707ea434ab5623vboxsync return VINF_SUCCESS;
78df65edff21c11c537f38e736707ea434ab5623vboxsync}
78df65edff21c11c537f38e736707ea434ab5623vboxsync
78df65edff21c11c537f38e736707ea434ab5623vboxsync
78df65edff21c11c537f38e736707ea434ab5623vboxsync/**
78df65edff21c11c537f38e736707ea434ab5623vboxsync * Tries to modify one bit.
78df65edff21c11c537f38e736707ea434ab5623vboxsync *
78df65edff21c11c537f38e736707ea434ab5623vboxsync * @retval -2 on API error.
78df65edff21c11c537f38e736707ea434ab5623vboxsync * @retval -1 on \#GP.
78df65edff21c11c537f38e736707ea434ab5623vboxsync * @retval 0 if ignored.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @retval 1 if it changed.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param uMsr The MSR.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param iBit The bit to try modify.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic int msrProberModifyBit(uint32_t uMsr, unsigned iBit)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uint64_t fBitMask = RT_BIT_64(iBit);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Set it. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync SUPMSRPROBERMODIFYRESULT ResultSet;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, fBitMask, &ResultSet);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (RT_FAILURE(rc))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RTMsgErrorRc(-2, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, fBitMask, rc);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Clear it. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync SUPMSRPROBERMODIFYRESULT ResultClear;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, 0, &ResultClear);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (RT_FAILURE(rc))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RTMsgErrorRc(-2, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, 0, rc);
78df65edff21c11c537f38e736707ea434ab5623vboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (ResultSet.fModifyGp || ResultClear.fModifyGp)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return -1;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
78df65edff21c11c537f38e736707ea434ab5623vboxsync if ( ( ((ResultSet.uBefore ^ ResultSet.uAfter) & fBitMask) != 0
78df65edff21c11c537f38e736707ea434ab5623vboxsync && !ResultSet.fBeforeGp
78df65edff21c11c537f38e736707ea434ab5623vboxsync && !ResultSet.fAfterGp)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync || ( ((ResultClear.uBefore ^ ResultClear.uAfter) & fBitMask) != 0
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !ResultClear.fBeforeGp
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !ResultClear.fAfterGp) )
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return 1;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return 0;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/**
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Tries to do a simple AND+OR change and see if we \#GP or not.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @retval @c true if successfully modified.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @retval @c false if \#GP or other error.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param uMsr The MSR.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param fAndMask The AND mask.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param fOrMask The OR mask.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool msrProberModifySimpleGp(uint32_t uMsr, uint64_t fAndMask, uint64_t fOrMask)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync SUPMSRPROBERMODIFYRESULT Result;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, fAndMask, fOrMask, &Result);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (RT_FAILURE(rc))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTMsgError("SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, fAndMask, fOrMask, rc);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return false;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return !Result.fBeforeGp
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !Result.fModifyGp
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !Result.fAfterGp
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && !Result.fRestoreGp;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/**
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Combination of the basic tests.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @returns VBox status code.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param uMsr The MSR.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param fSkipMask Mask of bits to skip.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param pfReadOnly Where to return read-only status.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param pfIgnMask Where to return the write ignore mask. Need not
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * be initialized.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param pfGpMask Where to return the write GP mask. Need not
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * be initialized.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic int msrProberModifyBasicTests(uint32_t uMsr, uint64_t fSkipMask, bool *pfReadOnly, uint64_t *pfIgnMask, uint64_t *pfGpMask)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (msrProberModifyNoChange(uMsr))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *pfReadOnly = false;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *pfIgnMask = 0;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *pfGpMask = 0;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return msrProberModifyBitChanges(uMsr, pfIgnMask, pfGpMask, fSkipMask);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *pfReadOnly = true;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *pfIgnMask = 0;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *pfGpMask = UINT64_MAX;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return VINF_SUCCESS;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/**
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Determines for the MSR AND mask.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Older CPUs doesn't necessiarly implement all bits of the MSR register number.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * So, we have to approximate how many are used so we don't get an overly large
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * and confusing set of MSRs when probing.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @returns The mask.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic uint32_t determineMsrAndMask(void)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#define VBCPUREP_MASK_TEST_MSRS 7
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync static uint32_t const s_aMsrs[VBCPUREP_MASK_TEST_MSRS] =
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Try a bunch of mostly read only registers: */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync MSR_P5_MC_TYPE, MSR_IA32_PLATFORM_ID, MSR_IA32_MTRR_CAP, MSR_IA32_MCG_CAP, MSR_IA32_CR_PAT,
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Then some which aren't supposed to be present on any CPU: */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync 0x00000015, 0x00000019,
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync };
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Get the base values. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uint64_t auBaseValues[VBCPUREP_MASK_TEST_MSRS];
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync for (unsigned i = 0; i < RT_ELEMENTS(s_aMsrs); i++)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (!msrProberRead(s_aMsrs[i], &auBaseValues[i]))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync auBaseValues[i] = UINT64_MAX;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //vbCpuRepDebug("Base: %#x -> %#llx\n", s_aMsrs[i], auBaseValues[i]);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Do the probing. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync unsigned iBit;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync for (iBit = 31; iBit > 8; iBit--)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uint64_t fMsrOrMask = RT_BIT_64(iBit);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync for (unsigned iTest = 0; iTest <= 64 && fMsrOrMask < UINT32_MAX; iTest++)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync for (unsigned i = 0; i < RT_ELEMENTS(s_aMsrs); i++)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uint64_t uValue;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (!msrProberRead(s_aMsrs[i] | fMsrOrMask, &uValue))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uValue = UINT64_MAX;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (uValue != auBaseValues[i])
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uint32_t fMsrMask = iBit >= 31 ? UINT32_MAX : RT_BIT_32(iBit + 1) - 1;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync vbCpuRepDebug("MSR AND mask: quit on iBit=%u uMsr=%#x (%#x) %llx != %llx => fMsrMask=%#x\n",
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync iBit, s_aMsrs[i] | (uint32_t)fMsrOrMask, s_aMsrs[i], uValue, auBaseValues[i], fMsrMask);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return fMsrMask;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Advance. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (iBit <= 6)
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync fMsrOrMask += RT_BIT_64(iBit);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync else if (iBit <= 11)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync fMsrOrMask += RT_BIT_64(iBit) * 33;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync else if (iBit <= 16)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync fMsrOrMask += RT_BIT_64(iBit) * 1025;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync else if (iBit <= 22)
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync fMsrOrMask += RT_BIT_64(iBit) * 65537;
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync else
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync fMsrOrMask += RT_BIT_64(iBit) * 262145;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
090c459b9e90ca46e2ce2b8c81533ade3b23f3e9vboxsync uint32_t fMsrMask = RT_BIT_32(iBit + 1) - 1;
090c459b9e90ca46e2ce2b8c81533ade3b23f3e9vboxsync vbCpuRepDebug("MSR AND mask: less that %u bits that matters?!? => fMsrMask=%#x\n", iBit + 1, fMsrMask);
090c459b9e90ca46e2ce2b8c81533ade3b23f3e9vboxsync return fMsrMask;
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync}
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsyncstatic int findMsrs(VBCPUREPMSR **ppaMsrs, uint32_t *pcMsrs, uint32_t fMsrMask)
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync{
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync /*
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync * Gather them.
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync */
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync static struct { uint32_t uFirst, cMsrs; } const s_aRanges[] =
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync {
090c459b9e90ca46e2ce2b8c81533ade3b23f3e9vboxsync { 0x00000000, 0x00042000 },
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync { 0x10000000, 0x00001000 },
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync { 0x20000000, 0x00001000 },
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync { 0x40000000, 0x00012000 },
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync { 0x80000000, 0x00012000 },
090c459b9e90ca46e2ce2b8c81533ade3b23f3e9vboxsync { 0xc0000000, 0x00022000 }, /* Had some trouble here on solaris with the tstVMM setup. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync };
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *pcMsrs = 0;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *ppaMsrs = NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync for (unsigned i = 0; i < RT_ELEMENTS(s_aRanges); i++)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uint32_t uMsr = s_aRanges[i].uFirst;
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync if ((uMsr & fMsrMask) != uMsr)
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync continue;
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync uint32_t cLeft = s_aRanges[i].cMsrs;
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync while (cLeft-- > 0 && (uMsr & fMsrMask) == uMsr)
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync {
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync if ((uMsr & 0xfff) == 0)
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync {
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync vbCpuRepDebug("testing %#x...\n", uMsr);
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync RTThreadSleep(22);
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync }
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync#if 0
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync else if (uMsr >= 0xc0011000 && uMsr <= 0xc0011100)
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync {
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync vbCpuRepDebug("testing %#x...\n", uMsr);
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync RTThreadSleep(250);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#endif
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Skip 0xc0011012..13 as it seems to be bad for our health (Phenom II X6 1100T). */
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync if ((uMsr >= 0xc0011012 && uMsr <= 0xc0011013) && g_enmVendor == CPUMCPUVENDOR_AMD)
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync vbCpuRepDebug("Skipping %#x\n", uMsr);
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync else
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync {
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync /* Read probing normally does it. */
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync uint64_t uValue = 0;
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync bool fGp = true;
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync int rc = SUPR3MsrProberRead(uMsr, NIL_RTCPUID, &uValue, &fGp);
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync if (RT_FAILURE(rc))
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync {
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync RTMemFree(*ppaMsrs);
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync *ppaMsrs = NULL;
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync return RTMsgErrorRc(rc, "SUPR3MsrProberRead failed on %#x: %Rrc\n", uMsr, rc);
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync }
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync
a86135e41c89c7b599607649347a4240809c784bvboxsync uint32_t fFlags;
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync if (!fGp)
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync fFlags = 0;
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync else
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync {
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync /* Is it a write only register? */
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync#if 0
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync if (uMsr >= 0xc0011000 && uMsr <= 0xc0011100)
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync {
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync vbCpuRepDebug("test writing %#x...\n", uMsr);
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync RTThreadSleep(250);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync#endif
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync fGp = true;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync rc = SUPR3MsrProberWrite(uMsr, NIL_RTCPUID, 0, &fGp);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (RT_FAILURE(rc))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTMemFree(*ppaMsrs);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *ppaMsrs = NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RTMsgErrorRc(rc, "SUPR3MsrProberWrite failed on %#x: %Rrc\n", uMsr, rc);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uValue = 0;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync fFlags = VBCPUREPMSR_F_WRITE_ONLY;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /*
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Tweaks. On Intel CPUs we've got trouble detecting
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * IA32_BIOS_UPDT_TRIG (0x00000079), so we have to add it manually here.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if ( uMsr == 0x00000079
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && fGp
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && g_enmMicroarch >= kCpumMicroarch_Intel_P6_Core_Atom_First
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && g_enmMicroarch <= kCpumMicroarch_Intel_End)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync fGp = false;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (!fGp)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Add it. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync rc = vbCpuRepMsrsAddOne(ppaMsrs, pcMsrs, uMsr, uValue, fFlags);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (RT_FAILURE(rc))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RTMsgErrorRc(rc, "Out of memory (uMsr=%#x).\n", uMsr);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync vbCpuRepDebug("%#010x: uValue=%#llx fFlags=%#x\n", uMsr, uValue, fFlags);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uMsr++;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return VINF_SUCCESS;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/**
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Get the name of the specified MSR, if we know it and can handle it.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Do _NOT_ add any new names here without ALSO at the SAME TIME making sure it
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * is handled correctly by the PROBING CODE and REPORTED correctly!!
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @returns Pointer to name if handled, NULL if not yet explored.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param uMsr The MSR in question.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic const char *getMsrNameHandled(uint32_t uMsr)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /** @todo figure out where NCU_EVENT_CORE_MASK might be... */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync switch (uMsr)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000000: return "IA32_P5_MC_ADDR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000001: return "IA32_P5_MC_TYPE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000006:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (g_enmMicroarch >= kCpumMicroarch_Intel_First && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_First)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return NULL; /* TR4 / cache tag on Pentium, but that's for later. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "IA32_MONITOR_FILTER_LINE_SIZE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x0000000e: return "P?_TR12"; /* K6-III docs */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000010: return "IA32_TIME_STAMP_COUNTER";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000017: return "IA32_PLATFORM_ID";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000018: return "P6_UNK_0000_0018"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000001b: return "IA32_APIC_BASE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000021: return "C2_UNK_0000_0021"; /* Core2_Penryn */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000002a: return "EBL_CR_POWERON";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000002e: return "I7_UNK_0000_002e"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000002f: return "P6_UNK_0000_002f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000032: return "P6_UNK_0000_0032"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000033: return "TEST_CTL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000034: return "P6_UNK_0000_0034"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000035: return "P6_UNK_0000_0035"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000036: return "I7_UNK_0000_0036"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000039: return "C2_UNK_0000_0039"; /* Core2_Penryn */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000003a: return "IA32_FEATURE_CONTROL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000003b: return "P6_UNK_0000_003b"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000003e: return "I7_UNK_0000_003e"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000003f: return "P6_UNK_0000_003f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000040: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_0_FROM_IP" : "MSR_LASTBRANCH_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000041: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_1_FROM_IP" : "MSR_LASTBRANCH_1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000042: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_2_FROM_IP" : "MSR_LASTBRANCH_2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000043: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_3_FROM_IP" : "MSR_LASTBRANCH_3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000044: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_4_FROM_IP" : "MSR_LASTBRANCH_4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000045: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_5_FROM_IP" : "MSR_LASTBRANCH_5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000046: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_6_FROM_IP" : "MSR_LASTBRANCH_6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000047: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_7_FROM_IP" : "MSR_LASTBRANCH_7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000048: return "MSR_LASTBRANCH_8"; /*??*/
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000049: return "MSR_LASTBRANCH_9"; /*??*/
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000004a: return "P6_UNK_0000_004a"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000004b: return "P6_UNK_0000_004b"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000004c: return "P6_UNK_0000_004c"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000004d: return "P6_UNK_0000_004d"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000004e: return "P6_UNK_0000_004e"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000004f: return "P6_UNK_0000_004f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000050: return "P6_UNK_0000_0050"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000051: return "P6_UNK_0000_0051"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000052: return "P6_UNK_0000_0052"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000053: return "P6_UNK_0000_0053"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000054: return "P6_UNK_0000_0054"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000060: return "MSR_LASTBRANCH_0_TO_IP"; /* Core2_Penryn */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000061: return "MSR_LASTBRANCH_1_TO_IP"; /* Core2_Penryn */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000062: return "MSR_LASTBRANCH_2_TO_IP"; /* Core2_Penryn */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000063: return "MSR_LASTBRANCH_3_TO_IP"; /* Core2_Penryn */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000064: return "MSR_LASTBRANCH_4_TO_IP"; /* Atom? */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000065: return "MSR_LASTBRANCH_5_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000066: return "MSR_LASTBRANCH_6_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000067: return "MSR_LASTBRANCH_7_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000006c: return "P6_UNK_0000_006c"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000006d: return "P6_UNK_0000_006d"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000006e: return "P6_UNK_0000_006e"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000006f: return "P6_UNK_0000_006f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000079: return "IA32_BIOS_UPDT_TRIG";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000088: return "BBL_CR_D0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000089: return "BBL_CR_D1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000008a: return "BBL_CR_D2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000008b: return "BBL_CR_D3|BIOS_SIGN";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000008c: return "P6_UNK_0000_008c"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000008d: return "P6_UNK_0000_008d"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000008e: return "P6_UNK_0000_008e"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000008f: return "P6_UNK_0000_008f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000090: return "P6_UNK_0000_0090"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000009b: return "IA32_SMM_MONITOR_CTL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000a8: return "C2_EMTTM_CR_TABLES_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000a9: return "C2_EMTTM_CR_TABLES_1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000aa: return "C2_EMTTM_CR_TABLES_2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ab: return "C2_EMTTM_CR_TABLES_3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ac: return "C2_EMTTM_CR_TABLES_4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ad: return "C2_EMTTM_CR_TABLES_5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ae: return "P6_UNK_0000_00ae"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c1: return "IA32_PMC0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c2: return "IA32_PMC1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c3: return "IA32_PMC2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c4: return "IA32_PMC3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* PMC4+ first seen on SandyBridge. The earlier cut off is just to be
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync on the safe side as we must avoid P6_M_Dothan and possibly others. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c5: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC4" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c6: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC5" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c7: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC6" : "P6_UNK_0000_00c7"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC7" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000cd: return "P6_UNK_0000_00cd"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ce: return "P6_UNK_0000_00ce"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000cf: return "C2_UNK_0000_00cf"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e0: return "C2_UNK_0000_00e0"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e1: return "C2_UNK_0000_00e1"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e2: return "MSR_PKG_CST_CONFIG_CONTROL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e3: return "C2_SMM_CST_MISC_INFO"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e4: return "MSR_PMG_IO_CAPTURE_BASE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e5: return "C2_UNK_0000_00e5"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e7: return "IA32_MPERF";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e8: return "IA32_APERF";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ee: return "C1_EXT_CONFIG"; /* Core2_Penryn. msrtool lists it for Core1 as well. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000fe: return "IA32_MTRRCAP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000102: return "I7_IB_UNK_0000_0102"; /* IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000103: return "I7_IB_UNK_0000_0103"; /* IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000104: return "I7_IB_UNK_0000_0104"; /* IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000116: return "BBL_CR_ADDR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000118: return "BBL_CR_DECC";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000119: return "BBL_CR_CTL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000011a: return "BBL_CR_TRIG";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000011b: return "P6_UNK_0000_011b"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000011c: return "C2_UNK_0000_011c"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000011e: return "BBL_CR_CTL3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000130: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync ? "CPUID1_FEATURE_MASK" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000131: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync ? "CPUID80000001_FEATURE_MASK" : "P6_UNK_0000_0131" /* P6_M_Dothan. */;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000132: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync ? "CPUID1_FEATURE_MASK" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000133: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync ? "CPUIDD_01_FEATURE_MASK" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000134: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync ? "CPUID80000001_FEATURE_MASK" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000013c: return "I7_SB_AES_NI_CTL"; /* SandyBridge. Bit 0 is lock bit, bit 1 disables AES-NI. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000140: return "I7_IB_UNK_0000_0140"; /* IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000142: return "I7_IB_UNK_0000_0142"; /* IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000014e: return "P6_UNK_0000_014e"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000014f: return "P6_UNK_0000_014f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000150: return "P6_UNK_0000_0150"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000151: return "P6_UNK_0000_0151"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000154: return "P6_UNK_0000_0154"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000015b: return "P6_UNK_0000_015b"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000015e: return "C2_UNK_0000_015e"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000015f: return "C1_DTS_CAL_CTRL"; /* Core2_Penryn. msrtool only docs this for core1! */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000174: return "IA32_SYSENTER_CS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000175: return "IA32_SYSENTER_ESP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000176: return "IA32_SYSENTER_EIP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000179: return "IA32_MCG_CAP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000017a: return "IA32_MCG_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000017b: return "IA32_MCG_CTL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000017f: return "I7_SB_ERROR_CONTROL"; /* SandyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000180: return g_fIntelNetBurst ? "MSR_MCG_RAX" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000181: return g_fIntelNetBurst ? "MSR_MCG_RBX" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000182: return g_fIntelNetBurst ? "MSR_MCG_RCX" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000183: return g_fIntelNetBurst ? "MSR_MCG_RDX" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000184: return g_fIntelNetBurst ? "MSR_MCG_RSI" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000185: return g_fIntelNetBurst ? "MSR_MCG_RDI" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000186: return g_fIntelNetBurst ? "MSR_MCG_RBP" : "IA32_PERFEVTSEL0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000187: return g_fIntelNetBurst ? "MSR_MCG_RSP" : "IA32_PERFEVTSEL1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000188: return g_fIntelNetBurst ? "MSR_MCG_RFLAGS" : "IA32_PERFEVTSEL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000189: return g_fIntelNetBurst ? "MSR_MCG_RIP" : "IA32_PERFEVTSEL3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000018a: return g_fIntelNetBurst ? "MSR_MCG_MISC" : "IA32_PERFEVTSEL4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000018b: return g_fIntelNetBurst ? "MSR_MCG_RESERVED1" : "IA32_PERFEVTSEL5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000018c: return g_fIntelNetBurst ? "MSR_MCG_RESERVED2" : "IA32_PERFEVTSEL6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000018d: return g_fIntelNetBurst ? "MSR_MCG_RESERVED3" : "IA32_PERFEVTSEL7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000018e: return g_fIntelNetBurst ? "MSR_MCG_RESERVED4" : "IA32_PERFEVTSEL8";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000018f: return g_fIntelNetBurst ? "MSR_MCG_RESERVED5" : "IA32_PERFEVTSEL9";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000190: return g_fIntelNetBurst ? "MSR_MCG_R8" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000191: return g_fIntelNetBurst ? "MSR_MCG_R9" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000192: return g_fIntelNetBurst ? "MSR_MCG_R10" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000193: return g_fIntelNetBurst ? "MSR_MCG_R11" : "C2_UNK_0000_0193";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000194: return g_fIntelNetBurst ? "MSR_MCG_R12" : "CLOCK_FLEX_MAX";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000195: return g_fIntelNetBurst ? "MSR_MCG_R13" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000196: return g_fIntelNetBurst ? "MSR_MCG_R14" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000197: return g_fIntelNetBurst ? "MSR_MCG_R15" : NULL;
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x00000198: return "IA32_PERF_STATUS";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x00000199: return "IA32_PERF_CTL";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x0000019a: return "IA32_CLOCK_MODULATION";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x0000019b: return "IA32_THERM_INTERRUPT";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x0000019c: return "IA32_THERM_STATUS";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x0000019d: return "IA32_THERM2_CTL";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x0000019e: return "P6_UNK_0000_019e"; /* P6_M_Dothan. */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x0000019f: return "P6_UNK_0000_019f"; /* P6_M_Dothan. */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001a0: return "IA32_MISC_ENABLE";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001a1: return "P6_UNK_0000_01a1"; /* P6_M_Dothan. */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001a2: return "I7_MSR_TEMPERATURE_TARGET"; /* SandyBridge, IvyBridge. */
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0x000001a4: return "I7_UNK_0000_01a4"; /* SandyBridge, IvyBridge. */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001a6: return "I7_MSR_OFFCORE_RSP_0";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001a7: return "I7_MSR_OFFCORE_RSP_1";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001a8: return "I7_UNK_0000_01a8"; /* SandyBridge, IvyBridge. */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001aa: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "MSR_MISC_PWR_MGMT" : "P6_PIC_SENS_CFG" /* Pentium M. */;
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001ad: return "I7_MSR_TURBO_RATIO_LIMIT"; /* SandyBridge+, Silvermount+ */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001ae: return "P6_UNK_0000_01ae"; /* P6_M_Dothan. */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001af: return "P6_UNK_0000_01af"; /* P6_M_Dothan. */
dbec828311ed2a5cf6fbc68fe4391d516ba4f92fvboxsync case 0x000001b0: return "IA32_ENERGY_PERF_BIAS";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001b1: return "IA32_PACKAGE_THERM_STATUS";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001b2: return "IA32_PACKAGE_THERM_INTERRUPT";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001bf: return "C2_UNK_0000_01bf"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001c6: return "I7_UNK_0000_01c6"; /* SandyBridge*/
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Nehalem ? "MSR_LBR_SELECT" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001c9: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_End
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync ? "MSR_LASTBRANCH_TOS" : NULL /* Pentium M Dothan seems to have something else here. */;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001d3: return "P6_UNK_0000_01d3"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001d9: return "IA32_DEBUGCTL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001db: return "P6_LAST_BRANCH_FROM_IP"; /* Not exclusive to P6, also AMD. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001dc: return "P6_LAST_BRANCH_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001dd: return "P6_LAST_INT_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001de: return "P6_LAST_INT_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001e0: return "MSR_ROB_CR_BKUPTMPDR6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001e1: return "I7_SB_UNK_0000_01e1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001ef: return "I7_SB_UNK_0000_01ef";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001f0: return "I7_VLW_CAPABILITY"; /* SandyBridge. Bit 1 is A20M and was implemented incorrectly (AAJ49). */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001f2: return "IA32_SMRR_PHYSBASE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001f3: return "IA32_SMRR_PHYSMASK";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001f8: return "IA32_PLATFORM_DCA_CAP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001f9: return "IA32_CPU_DCA_CAP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001fa: return "IA32_DCA_0_CAP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001fc: return "I7_MSR_POWER_CTL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000200: return "IA32_MTRR_PHYS_BASE0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000202: return "IA32_MTRR_PHYS_BASE1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000204: return "IA32_MTRR_PHYS_BASE2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000206: return "IA32_MTRR_PHYS_BASE3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000208: return "IA32_MTRR_PHYS_BASE4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000020a: return "IA32_MTRR_PHYS_BASE5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000020c: return "IA32_MTRR_PHYS_BASE6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000020e: return "IA32_MTRR_PHYS_BASE7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000210: return "IA32_MTRR_PHYS_BASE8";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000212: return "IA32_MTRR_PHYS_BASE9";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000214: return "IA32_MTRR_PHYS_BASE10";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000216: return "IA32_MTRR_PHYS_BASE11";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000218: return "IA32_MTRR_PHYS_BASE12";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000021a: return "IA32_MTRR_PHYS_BASE13";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000021c: return "IA32_MTRR_PHYS_BASE14";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000021e: return "IA32_MTRR_PHYS_BASE15";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000201: return "IA32_MTRR_PHYS_MASK0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000203: return "IA32_MTRR_PHYS_MASK1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000205: return "IA32_MTRR_PHYS_MASK2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000207: return "IA32_MTRR_PHYS_MASK3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000209: return "IA32_MTRR_PHYS_MASK4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000020b: return "IA32_MTRR_PHYS_MASK5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000020d: return "IA32_MTRR_PHYS_MASK6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000020f: return "IA32_MTRR_PHYS_MASK7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000211: return "IA32_MTRR_PHYS_MASK8";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000213: return "IA32_MTRR_PHYS_MASK9";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000215: return "IA32_MTRR_PHYS_MASK10";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000217: return "IA32_MTRR_PHYS_MASK11";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000219: return "IA32_MTRR_PHYS_MASK12";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000021b: return "IA32_MTRR_PHYS_MASK13";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000021d: return "IA32_MTRR_PHYS_MASK14";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000021f: return "IA32_MTRR_PHYS_MASK15";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000250: return "IA32_MTRR_FIX64K_00000";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000258: return "IA32_MTRR_FIX16K_80000";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000259: return "IA32_MTRR_FIX16K_A0000";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000268: return "IA32_MTRR_FIX4K_C0000";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000269: return "IA32_MTRR_FIX4K_C8000";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000026a: return "IA32_MTRR_FIX4K_D0000";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000026b: return "IA32_MTRR_FIX4K_D8000";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000026c: return "IA32_MTRR_FIX4K_E0000";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000026d: return "IA32_MTRR_FIX4K_E8000";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000026e: return "IA32_MTRR_FIX4K_F0000";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000026f: return "IA32_MTRR_FIX4K_F8000";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000277: return "IA32_PAT";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000280: return "IA32_MC0_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000281: return "IA32_MC1_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000282: return "IA32_MC2_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000283: return "IA32_MC3_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000284: return "IA32_MC4_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000285: return "IA32_MC5_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000286: return "IA32_MC6_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000287: return "IA32_MC7_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000288: return "IA32_MC8_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000289: return "IA32_MC9_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000028a: return "IA32_MC10_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000028b: return "IA32_MC11_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000028c: return "IA32_MC12_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000028d: return "IA32_MC13_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000028e: return "IA32_MC14_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000028f: return "IA32_MC15_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000290: return "IA32_MC16_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000291: return "IA32_MC17_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000292: return "IA32_MC18_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000293: return "IA32_MC19_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000294: return "IA32_MC20_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000295: return "IA32_MC21_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x00000296: return "IA32_MC22_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x00000297: return "IA32_MC23_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x00000298: return "IA32_MC24_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x00000299: return "IA32_MC25_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x0000029a: return "IA32_MC26_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x0000029b: return "IA32_MC27_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x0000029c: return "IA32_MC28_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x0000029d: return "IA32_MC29_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x0000029e: return "IA32_MC30_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x0000029f: return "IA32_MC31_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000002e0: return "I7_SB_NO_EVICT_MODE"; /* (Bits 1 & 0 are said to have something to do with no-evict cache mode used during early boot.) */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000002e6: return "I7_IB_UNK_0000_02e6"; /* IvyBridge */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000002e7: return "I7_IB_UNK_0000_02e7"; /* IvyBridge */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000002ff: return "IA32_MTRR_DEF_TYPE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000300: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_BPU_COUNTER0" : "I7_SB_UNK_0000_0300" /* SandyBridge */;
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0x00000305: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_MS_COUNTER1" : "I7_SB_UNK_0000_0305" /* SandyBridge, IvyBridge */;
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0x00000309: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_FLAME_COUNTER1" : "IA32_FIXED_CTR0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000030a: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_FLAME_COUNTER2" : "IA32_FIXED_CTR1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000030b: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_FLAME_COUNTER3" : "IA32_FIXED_CTR2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000345: return "IA32_PERF_CAPABILITIES";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000038d: return "IA32_FIXED_CTR_CTRL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000038e: return "IA32_PERF_GLOBAL_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000038f: return "IA32_PERF_GLOBAL_CTRL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000390: return "IA32_PERF_GLOBAL_OVF_CTRL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000391: return "I7_UNC_PERF_GLOBAL_CTRL"; /* S,H,X */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000392: return "I7_UNC_PERF_GLOBAL_STATUS"; /* S,H,X */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000393: return "I7_UNC_PERF_GLOBAL_OVF_CTRL"; /* X. ASSUMING this is the same on sandybridge and later. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000394: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PERF_FIXED_CTR" /* X */ : "I7_UNC_PERF_FIXED_CTR_CTRL"; /* >= S,H */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000395: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PERF_FIXED_CTR_CTRL" /* X*/ : "I7_UNC_PERF_FIXED_CTR"; /* >= S,H */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_ADDR_OPCODE_MATCH" /* X */ : "I7_UNC_CBO_CONFIG"; /* >= S,H */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000397: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_IvyBridge ? NULL : "I7_IB_UNK_0000_0397";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000039c: return "I7_SB_MSR_PEBS_NUM_ALT";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003b0: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC0" /* X */ : "I7_UNC_ARB_PERF_CTR0"; /* >= S,H */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003b1: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC1" /* X */ : "I7_UNC_ARB_PERF_CTR1"; /* >= S,H */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003b2: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC2" /* X */ : "I7_UNC_ARB_PERF_EVT_SEL0"; /* >= S,H */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003b3: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC3" /* X */ : "I7_UNC_ARB_PERF_EVT_SEL1"; /* >= S,H */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003b4: return "I7_UNC_PMC4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003b5: return "I7_UNC_PMC5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003b6: return "I7_UNC_PMC6";
090c459b9e90ca46e2ce2b8c81533ade3b23f3e9vboxsync case 0x000003b7: return "I7_UNC_PMC7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003c0: return "I7_UNC_PERF_EVT_SEL0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003c1: return "I7_UNC_PERF_EVT_SEL1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003c2: return "I7_UNC_PERF_EVT_SEL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003c3: return "I7_UNC_PERF_EVT_SEL3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003c4: return "I7_UNC_PERF_EVT_SEL4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003c5: return "I7_UNC_PERF_EVT_SEL5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003c6: return "I7_UNC_PERF_EVT_SEL6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003c7: return "I7_UNC_PERF_EVT_SEL7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003f1: return "IA32_PEBS_ENABLE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003f6: return "I7_MSR_PEBS_LD_LAT";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003f8: return "I7_MSR_PKG_C3_RESIDENCY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003f9: return "I7_MSR_PKG_C6_RESIDENCY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fa: return "I7_MSR_PKG_C7_RESIDENCY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fc: return "I7_MSR_CORE_C3_RESIDENCY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fd: return "I7_MSR_CORE_C6_RESIDENCY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fe: return "I7_MSR_CORE_C7_RESIDENCY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000478: return g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "CPUID1_FEATURE_MASK" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000480: return "IA32_VMX_BASIC";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000481: return "IA32_VMX_PINBASED_CTLS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000482: return "IA32_VMX_PROCBASED_CTLS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000483: return "IA32_VMX_EXIT_CTLS";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0x00000484: return "IA32_VMX_ENTRY_CTLS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000485: return "IA32_VMX_MISC";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000486: return "IA32_VMX_CR0_FIXED0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000487: return "IA32_VMX_CR0_FIXED1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000488: return "IA32_VMX_CR4_FIXED0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000489: return "IA32_VMX_CR4_FIXED1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000048a: return "IA32_VMX_VMCS_ENUM";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000048b: return "IA32_VMX_PROCBASED_CTLS2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000048c: return "IA32_VMX_EPT_VPID_CAP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000048d: return "IA32_VMX_TRUE_PINBASED_CTLS";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0x0000048e: return "IA32_VMX_TRUE_PROCBASED_CTLS";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0x0000048f: return "IA32_VMX_TRUE_EXIT_CTLS";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0x00000490: return "IA32_VMX_TRUE_ENTRY_CTLS";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000004c1: return "IA32_A_PMC0";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000004c2: return "IA32_A_PMC1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004c3: return "IA32_A_PMC2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004c4: return "IA32_A_PMC3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004c5: return "IA32_A_PMC4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004c6: return "IA32_A_PMC5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004c7: return "IA32_A_PMC6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004c8: return "IA32_A_PMC7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004f8: return "C2_UNK_0000_04f8"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004f9: return "C2_UNK_0000_04f9"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004fa: return "C2_UNK_0000_04fa"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004fb: return "C2_UNK_0000_04fb"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004fc: return "C2_UNK_0000_04fc"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004fd: return "C2_UNK_0000_04fd"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004fe: return "C2_UNK_0000_04fe"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004ff: return "C2_UNK_0000_04ff"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000502: return "I7_SB_UNK_0000_0502";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000590: return "C2_UNK_0000_0590"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000591: return "C2_UNK_0000_0591"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000005a0: return "C2_PECI_CTL"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000005a1: return "C2_UNK_0000_05a1"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000600: return "IA32_DS_AREA";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000601: return "I7_SB_MSR_VR_CURRENT_CONFIG"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000602: return "I7_IB_UNK_0000_0602";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000603: return "I7_SB_MSR_VR_MISC_CONFIG"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000604: return "I7_IB_UNK_0000_0602";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000606: return "I7_SB_MSR_RAPL_POWER_UNIT"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000060a: return "I7_SB_MSR_PKGC3_IRTL"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000060b: return "I7_SB_MSR_PKGC6_IRTL"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000060c: return "I7_SB_MSR_PKGC7_IRTL"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000060d: return "I7_SB_MSR_PKG_C2_RESIDENCY"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000610: return "I7_SB_MSR_PKG_POWER_LIMIT";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000611: return "I7_SB_MSR_PKG_ENERGY_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000613: return "I7_SB_MSR_PKG_PERF_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000614: return "I7_SB_MSR_PKG_POWER_INFO";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000618: return "I7_SB_MSR_DRAM_POWER_LIMIT";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000619: return "I7_SB_MSR_DRAM_ENERGY_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000061b: return "I7_SB_MSR_DRAM_PERF_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000061c: return "I7_SB_MSR_DRAM_POWER_INFO";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000638: return "I7_SB_MSR_PP0_POWER_LIMIT";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000639: return "I7_SB_MSR_PP0_ENERGY_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000063a: return "I7_SB_MSR_PP0_POLICY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000063b: return "I7_SB_MSR_PP0_PERF_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000640: return "I7_HW_MSR_PP0_POWER_LIMIT";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000641: return "I7_HW_MSR_PP0_ENERGY_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000642: return "I7_HW_MSR_PP0_POLICY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000648: return "I7_IB_MSR_CONFIG_TDP_NOMINAL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000649: return "I7_IB_MSR_CONFIG_TDP_LEVEL1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000064a: return "I7_IB_MSR_CONFIG_TDP_LEVEL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000064b: return "I7_IB_MSR_CONFIG_TDP_CONTROL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000064c: return "I7_IB_MSR_TURBO_ACTIVATION_RATIO";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000680: return "MSR_LASTBRANCH_0_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000681: return "MSR_LASTBRANCH_1_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000682: return "MSR_LASTBRANCH_2_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000683: return "MSR_LASTBRANCH_3_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000684: return "MSR_LASTBRANCH_4_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000685: return "MSR_LASTBRANCH_5_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000686: return "MSR_LASTBRANCH_6_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000687: return "MSR_LASTBRANCH_7_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000688: return "MSR_LASTBRANCH_8_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000689: return "MSR_LASTBRANCH_9_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000068a: return "MSR_LASTBRANCH_10_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000068b: return "MSR_LASTBRANCH_11_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000068c: return "MSR_LASTBRANCH_12_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000068d: return "MSR_LASTBRANCH_13_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000068e: return "MSR_LASTBRANCH_14_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000068f: return "MSR_LASTBRANCH_15_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006c0: return "MSR_LASTBRANCH_0_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006c1: return "MSR_LASTBRANCH_1_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006c2: return "MSR_LASTBRANCH_2_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006c3: return "MSR_LASTBRANCH_3_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006c4: return "MSR_LASTBRANCH_4_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006c5: return "MSR_LASTBRANCH_5_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006c6: return "MSR_LASTBRANCH_6_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006c7: return "MSR_LASTBRANCH_7_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006c8: return "MSR_LASTBRANCH_8_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006c9: return "MSR_LASTBRANCH_9_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006ca: return "MSR_LASTBRANCH_10_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006cb: return "MSR_LASTBRANCH_11_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006cc: return "MSR_LASTBRANCH_12_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006cd: return "MSR_LASTBRANCH_13_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006ce: return "MSR_LASTBRANCH_14_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006cf: return "MSR_LASTBRANCH_15_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006e0: return "IA32_TSC_DEADLINE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c80: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "IA32_DEBUG_INTERFACE" : NULL; /* Mentioned in an intel dataskit called 4th-gen-core-family-desktop-vol-1-datasheet.pdf. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c81: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c81" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c82: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c82" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c83: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c83" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* 0x1000..0x1004 seems to have been used by IBM 386 and 486 clones too. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00001000: return "P6_DEBUG_REGISTER_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00001001: return "P6_DEBUG_REGISTER_1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00001002: return "P6_DEBUG_REGISTER_2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00001003: return "P6_DEBUG_REGISTER_3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00001004: return "P6_DEBUG_REGISTER_4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00001005: return "P6_DEBUG_REGISTER_5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00001006: return "P6_DEBUG_REGISTER_6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00001007: return "P6_DEBUG_REGISTER_7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000103f: return "P6_UNK_0000_103f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000010cd: return "P6_UNK_0000_10cd"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00002000: return "P6_CR0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00002002: return "P6_CR2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00002003: return "P6_CR3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00002004: return "P6_CR4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000203f: return "P6_UNK_0000_203f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000020cd: return "P6_UNK_0000_20cd"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000303f: return "P6_UNK_0000_303f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000030cd: return "P6_UNK_0000_30cd"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000080: return "AMD64_EFER";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000081: return "AMD64_STAR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000082: return "AMD64_STAR64";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000083: return "AMD64_STARCOMPAT";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000084: return "AMD64_SYSCALL_FLAG_MASK";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000100: return "AMD64_FS_BASE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000101: return "AMD64_GS_BASE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000102: return "AMD64_KERNEL_GS_BASE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000103: return "AMD64_TSC_AUX";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000104: return "AMD_15H_TSC_RATE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000105: return "AMD_15H_LWP_CFG"; /* Only Family 15h? */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000106: return "AMD_15H_LWP_CBADDR"; /* Only Family 15h? */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000408: return "AMD_10H_MC4_MISC1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000409: return "AMD_10H_MC4_MISC2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc000040a: return "AMD_10H_MC4_MISC3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc000040b: return "AMD_10H_MC4_MISC4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc000040c: return "AMD_10H_MC4_MISC5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc000040d: return "AMD_10H_MC4_MISC6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc000040e: return "AMD_10H_MC4_MISC7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc000040f: return "AMD_10H_MC4_MISC8";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010000: return "AMD_K8_PERF_CTL_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010001: return "AMD_K8_PERF_CTL_1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010002: return "AMD_K8_PERF_CTL_2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010003: return "AMD_K8_PERF_CTL_3";
090c459b9e90ca46e2ce2b8c81533ade3b23f3e9vboxsync case 0xc0010004: return "AMD_K8_PERF_CTR_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010005: return "AMD_K8_PERF_CTR_1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010006: return "AMD_K8_PERF_CTR_2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010007: return "AMD_K8_PERF_CTR_3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010010: return "AMD_K8_SYS_CFG";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010015: return "AMD_K8_HW_CFG";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010016: return "AMD_K8_IORR_BASE_0";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010017: return "AMD_K8_IORR_MASK_0";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010018: return "AMD_K8_IORR_BASE_1";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010019: return "AMD_K8_IORR_MASK_1";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc001001a: return "AMD_K8_TOP_MEM";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc001001d: return "AMD_K8_TOP_MEM2";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc001001e: return "AMD_K8_MANID";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc001001f: return "AMD_K8_NB_CFG1";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010021: return "AMD_10H_UNK_c001_0021";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010022: return "AMD_K8_MC_XCPT_REDIR";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010028: return "AMD_K8_UNK_c001_0028";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010029: return "AMD_K8_UNK_c001_0029";
11c2b573e2625474a51ae55ee1f3f82936f125davboxsync case 0xc001002a: return "AMD_K8_UNK_c001_002a";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc001002b: return "AMD_K8_UNK_c001_002b";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc001002c: return "AMD_K8_UNK_c001_002c";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc001002d: return "AMD_K8_UNK_c001_002d";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010030: return "AMD_K8_CPU_NAME_0";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010031: return "AMD_K8_CPU_NAME_1";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010032: return "AMD_K8_CPU_NAME_2";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010033: return "AMD_K8_CPU_NAME_3";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010034: return "AMD_K8_CPU_NAME_4";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010035: return "AMD_K8_CPU_NAME_5";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc001003e: return "AMD_K8_HTC";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc001003f: return "AMD_K8_STC";
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010043: return "AMD_K8_THERMTRIP_STATUS"; /* BDKG says it was removed in K8 revision C.*/
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010044: return "AMD_K8_MC_CTL_MASK_0";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010045: return "AMD_K8_MC_CTL_MASK_1";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010046: return "AMD_K8_MC_CTL_MASK_2";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010047: return "AMD_K8_MC_CTL_MASK_3";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010048: return "AMD_K8_MC_CTL_MASK_4";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010049: return "AMD_K8_MC_CTL_MASK_5";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc001004a: return "AMD_K8_MC_CTL_MASK_6";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync //case 0xc001004b: return "AMD_K8_MC_CTL_MASK_7";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010050: return "AMD_K8_SMI_ON_IO_TRAP_0";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010051: return "AMD_K8_SMI_ON_IO_TRAP_1";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010052: return "AMD_K8_SMI_ON_IO_TRAP_2";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010053: return "AMD_K8_SMI_ON_IO_TRAP_3";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010054: return "AMD_K8_SMI_ON_IO_TRAP_CTL_STS";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010055: return "AMD_K8_INT_PENDING_MSG";
04b02ffb8824a60fd37777bc1f7d2f35104a274cvboxsync case 0xc0010056: return "AMD_K8_SMI_TRIGGER_IO_CYCLE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010057: return "AMD_10H_UNK_c001_0057";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010058: return "AMD_10H_MMIO_CFG_BASE_ADDR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010059: return "AMD_10H_TRAP_CTL?"; /* Undocumented, only one google hit. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001005a: return "AMD_10H_UNK_c001_005a";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001005b: return "AMD_10H_UNK_c001_005b";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001005c: return "AMD_10H_UNK_c001_005c";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001005d: return "AMD_10H_UNK_c001_005d";
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010060: return "AMD_K8_BIST_RESULT"; /* BDKG says it as introduced with revision F. */
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010061: return "AMD_10H_P_ST_CUR_LIM";
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010062: return "AMD_10H_P_ST_CTL";
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010063: return "AMD_10H_P_ST_STS";
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010064: return "AMD_10H_P_ST_0";
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010065: return "AMD_10H_P_ST_1";
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010066: return "AMD_10H_P_ST_2";
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010067: return "AMD_10H_P_ST_3";
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010068: return "AMD_10H_P_ST_4";
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010069: return "AMD_10H_P_ST_5";
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc001006a: return "AMD_10H_P_ST_6";
04b02ffb8824a60fd37777bc1f7d2f35104a274cvboxsync case 0xc001006b: return "AMD_10H_P_ST_7";
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010070: return "AMD_10H_COFVID_CTL";
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010071: return "AMD_10H_COFVID_STS";
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010073: return "AMD_10H_C_ST_IO_BASE_ADDR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010074: return "AMD_10H_CPU_WD_TMR_CFG";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync // case 0xc0010075: return "AMD_15H_APML_TDP_LIM";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync // case 0xc0010077: return "AMD_15H_CPU_PWR_IN_TDP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync // case 0xc0010078: return "AMD_15H_PWR_AVG_PERIOD";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync // case 0xc0010079: return "AMD_15H_DRAM_CTR_CMD_THR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync // case 0xc0010080: return "AMD_16H_FSFM_ACT_CNT_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync // case 0xc0010081: return "AMD_16H_FSFM_REF_CNT_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010111: return "AMD_K8_SMM_BASE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010112: return "AMD_K8_SMM_ADDR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010113: return "AMD_K8_SMM_MASK";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010114: return "AMD_K8_VM_CR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010115: return "AMD_K8_IGNNE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010116: return "AMD_K8_SMM_CTL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010117: return "AMD_K8_VM_HSAVE_PA";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010118: return "AMD_10H_VM_LOCK_KEY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010119: return "AMD_10H_SSM_LOCK_KEY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001011a: return "AMD_10H_LOCAL_SMI_STS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010140: return "AMD_10H_OSVW_ID_LEN";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010141: return "AMD_10H_OSVW_STS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010200: return "AMD_K8_PERF_CTL_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010202: return "AMD_K8_PERF_CTL_1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010204: return "AMD_K8_PERF_CTL_2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010206: return "AMD_K8_PERF_CTL_3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010208: return "AMD_K8_PERF_CTL_4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001020a: return "AMD_K8_PERF_CTL_5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001020c: return "AMD_K8_PERF_CTL_6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001020e: return "AMD_K8_PERF_CTL_7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010201: return "AMD_K8_PERF_CTR_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010203: return "AMD_K8_PERF_CTR_1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010205: return "AMD_K8_PERF_CTR_2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010207: return "AMD_K8_PERF_CTR_3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010209: return "AMD_K8_PERF_CTR_4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001020b: return "AMD_K8_PERF_CTR_5";
78df65edff21c11c537f38e736707ea434ab5623vboxsync //case 0xc001020d: return "AMD_K8_PERF_CTR_6";
78df65edff21c11c537f38e736707ea434ab5623vboxsync //case 0xc001020f: return "AMD_K8_PERF_CTR_7";
78df65edff21c11c537f38e736707ea434ab5623vboxsync case 0xc0010230: return "AMD_16H_L2I_PERF_CTL_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010232: return "AMD_16H_L2I_PERF_CTL_1";
78df65edff21c11c537f38e736707ea434ab5623vboxsync case 0xc0010234: return "AMD_16H_L2I_PERF_CTL_2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010236: return "AMD_16H_L2I_PERF_CTL_3";
78df65edff21c11c537f38e736707ea434ab5623vboxsync //case 0xc0010238: return "AMD_16H_L2I_PERF_CTL_4";
78df65edff21c11c537f38e736707ea434ab5623vboxsync //case 0xc001023a: return "AMD_16H_L2I_PERF_CTL_5";
78df65edff21c11c537f38e736707ea434ab5623vboxsync //case 0xc001030c: return "AMD_16H_L2I_PERF_CTL_6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001023e: return "AMD_16H_L2I_PERF_CTL_7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010231: return "AMD_16H_L2I_PERF_CTR_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010233: return "AMD_16H_L2I_PERF_CTR_1";
78df65edff21c11c537f38e736707ea434ab5623vboxsync case 0xc0010235: return "AMD_16H_L2I_PERF_CTR_2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010237: return "AMD_16H_L2I_PERF_CTR_3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc0010239: return "AMD_16H_L2I_PERF_CTR_4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001023b: return "AMD_16H_L2I_PERF_CTR_5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001023d: return "AMD_16H_L2I_PERF_CTR_6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001023f: return "AMD_16H_L2I_PERF_CTR_7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010240: return "AMD_15H_NB_PERF_CTL_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010242: return "AMD_15H_NB_PERF_CTL_1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010244: return "AMD_15H_NB_PERF_CTL_2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010246: return "AMD_15H_NB_PERF_CTL_3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc0010248: return "AMD_15H_NB_PERF_CTL_4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001024a: return "AMD_15H_NB_PERF_CTL_5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001024c: return "AMD_15H_NB_PERF_CTL_6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001024e: return "AMD_15H_NB_PERF_CTL_7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010241: return "AMD_15H_NB_PERF_CTR_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010243: return "AMD_15H_NB_PERF_CTR_1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010245: return "AMD_15H_NB_PERF_CTR_2";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0010247: return "AMD_15H_NB_PERF_CTR_3";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync //case 0xc0010249: return "AMD_15H_NB_PERF_CTR_4";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync //case 0xc001024b: return "AMD_15H_NB_PERF_CTR_5";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync //case 0xc001024d: return "AMD_15H_NB_PERF_CTR_6";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync //case 0xc001024f: return "AMD_15H_NB_PERF_CTR_7";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011000: return "AMD_K7_MCODE_CTL";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011001: return "AMD_K7_APIC_CLUSTER_ID"; /* Mentioned in BKDG (r3.00) for fam16h when describing EBL_CR_POWERON. */
0fc8a97f9a19a44f1ad4670454edf26d80c42281vboxsync case 0xc0011002: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD07" : NULL;
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011003: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD06" : NULL;
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011004: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD01" : NULL;
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011005: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_EXT01" : NULL;
78df65edff21c11c537f38e736707ea434ab5623vboxsync case 0xc0011006: return "AMD_K7_DEBUG_STS?";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011007: return "AMD_K7_BH_TRACE_BASE?";
78df65edff21c11c537f38e736707ea434ab5623vboxsync case 0xc0011008: return "AMD_K7_BH_TRACE_PTR?";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011009: return "AMD_K7_BH_TRACE_LIM?";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc001100a: return "AMD_K7_HDT_CFG?";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc001100b: return "AMD_K7_FAST_FLUSH_COUNT?";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc001100c: return "AMD_K7_NODE_ID";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001100d: return "AMD_K8_LOGICAL_CPUS_NUM?";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001100e: return "AMD_K8_WRMSR_BP?";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001100f: return "AMD_K8_WRMSR_BP_MASK?";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011010: return "AMD_K8_BH_TRACE_CTL?";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011011: return "AMD_K8_BH_TRACE_USRD?";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011012: return "AMD_K7_UNK_c001_1012";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011013: return "AMD_K7_UNK_c001_1013";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011014: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_RIP?" : "AMD_K7_MOBIL_DEBUG?";
2506c2bcd77fcc75b5640fa0f6a55fb5ab48ff80vboxsync case 0xc0011015: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_RIP_MASK?" : NULL;
2506c2bcd77fcc75b5640fa0f6a55fb5ab48ff80vboxsync case 0xc0011016: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_COND_HDT_VAL?" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011017: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_COND_HDT_VAL_MASK?" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011018: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_CTL?" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011019: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR1_ADDR_MASK" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001101a: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR2_ADDR_MASK" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001101b: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR3_ADDR_MASK" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001101d: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_NB_BIST?" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001101e: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_THERMTRIP_2?" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001101f: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_NB_CFG?" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011020: return "AMD_K7_LS_CFG";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011021: return "AMD_K7_IC_CFG";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011022: return "AMD_K7_DC_CFG";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011023: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG" : "AMD_K7_BU_CFG";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011024: return "AMD_K7_DEBUG_CTL_2?";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011025: return "AMD_K7_DR0_DATA_MATCH?";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011026: return "AMD_K7_DR0_DATA_MATCH?";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011027: return "AMD_K7_DR0_ADDR_MASK";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011028: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AMD_15H_FP_CFG"
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) ? "AMD_10H_UNK_c001_1028"
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011029: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AMD_15H_DC_CFG"
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) ? "AMD_10H_UNK_c001_1029"
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001102a: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG2"
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) || g_enmMicroarch > kCpumMicroarch_AMD_15h_End
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync ? "AMD_10H_BU_CFG2" /* 10h & 16h */ : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001102b: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG3" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001102c: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_EX_CFG" : NULL;
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc001102d: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_LS_CFG2" : NULL;
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011030: return "AMD_10H_IBS_FETCH_CTL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011031: return "AMD_10H_IBS_FETCH_LIN_ADDR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011032: return "AMD_10H_IBS_FETCH_PHYS_ADDR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011033: return "AMD_10H_IBS_OP_EXEC_CTL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011034: return "AMD_10H_IBS_OP_RIP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011035: return "AMD_10H_IBS_OP_DATA";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011036: return "AMD_10H_IBS_OP_DATA2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011037: return "AMD_10H_IBS_OP_DATA3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011038: return "AMD_10H_IBS_DC_LIN_ADDR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011039: return "AMD_10H_IBS_DC_PHYS_ADDR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001103a: return "AMD_10H_IBS_CTL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001103b: return "AMD_14H_IBS_BR_TARGET";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011040: return "AMD_15H_UNK_c001_1040";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011041: return "AMD_15H_UNK_c001_1041";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011042: return "AMD_15H_UNK_c001_1042";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011043: return "AMD_15H_UNK_c001_1043";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011044: return "AMD_15H_UNK_c001_1044";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011045: return "AMD_15H_UNK_c001_1045";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011046: return "AMD_15H_UNK_c001_1046";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011047: return "AMD_15H_UNK_c001_1047";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011048: return "AMD_15H_UNK_c001_1048";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011049: return "AMD_15H_UNK_c001_1049";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001104a: return "AMD_15H_UNK_c001_104a";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001104b: return "AMD_15H_UNK_c001_104b";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001104c: return "AMD_15H_UNK_c001_104c";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001104d: return "AMD_15H_UNK_c001_104d";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001104e: return "AMD_15H_UNK_c001_104e";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001104f: return "AMD_15H_UNK_c001_104f";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011050: return "AMD_15H_UNK_c001_1050";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011051: return "AMD_15H_UNK_c001_1051";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011052: return "AMD_15H_UNK_c001_1052";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011053: return "AMD_15H_UNK_c001_1053";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011054: return "AMD_15H_UNK_c001_1054";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011055: return "AMD_15H_UNK_c001_1055";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011056: return "AMD_15H_UNK_c001_1056";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011057: return "AMD_15H_UNK_c001_1057";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011058: return "AMD_15H_UNK_c001_1058";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011059: return "AMD_15H_UNK_c001_1059";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001105a: return "AMD_15H_UNK_c001_105a";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001105b: return "AMD_15H_UNK_c001_105b";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001105c: return "AMD_15H_UNK_c001_105c";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001105d: return "AMD_15H_UNK_c001_105d";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001105e: return "AMD_15H_UNK_c001_105e";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001105f: return "AMD_15H_UNK_c001_105f";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011060: return "AMD_15H_UNK_c001_1060";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011061: return "AMD_15H_UNK_c001_1061";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011062: return "AMD_15H_UNK_c001_1062";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011063: return "AMD_15H_UNK_c001_1063";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011064: return "AMD_15H_UNK_c001_1064";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011065: return "AMD_15H_UNK_c001_1065";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011066: return "AMD_15H_UNK_c001_1066";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011067: return "AMD_15H_UNK_c001_1067";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011068: return "AMD_15H_UNK_c001_1068";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011069: return "AMD_15H_UNK_c001_1069";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001106a: return "AMD_15H_UNK_c001_106a";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001106b: return "AMD_15H_UNK_c001_106b";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001106c: return "AMD_15H_UNK_c001_106c";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001106d: return "AMD_15H_UNK_c001_106d";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001106e: return "AMD_15H_UNK_c001_106e";
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0xc001106f: return "AMD_15H_UNK_c001_106f";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011070: return "AMD_15H_UNK_c001_1070"; /* coreboot defines this, but with a numerical name. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011071: return "AMD_15H_UNK_c001_1071";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011072: return "AMD_15H_UNK_c001_1072";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011073: return "AMD_15H_UNK_c001_1073";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011080: return "AMD_15H_UNK_c001_1080";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /*
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Bunch of unknown sandy bridge registers. They might seem like the
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * nehalem based xeon stuff, but the layout doesn't match. I bet it's the
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync * same kind of registes though (i.e. uncore (UNC)).
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Kudos to Intel for keeping these a secret! Many thanks guys!!
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_SandyBridge)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync switch (uMsr)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0x00000a00: return "I7_SB_UNK_0000_0a00"; case 0x00000a01: return "I7_SB_UNK_0000_0a01";
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0x00000a02: return "I7_SB_UNK_0000_0a02";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000c00: return "I7_SB_UNK_0000_0c00"; case 0x00000c01: return "I7_SB_UNK_0000_0c01";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000c06: return "I7_SB_UNK_0000_0c06"; case 0x00000c08: return "I7_SB_UNK_0000_0c08";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000c09: return "I7_SB_UNK_0000_0c09"; case 0x00000c10: return "I7_SB_UNK_0000_0c10";
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0x00000c11: return "I7_SB_UNK_0000_0c11"; case 0x00000c14: return "I7_SB_UNK_0000_0c14";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c15: return "I7_SB_UNK_0000_0c15"; case 0x00000c16: return "I7_SB_UNK_0000_0c16";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c17: return "I7_SB_UNK_0000_0c17"; case 0x00000c24: return "I7_SB_UNK_0000_0c24";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c30: return "I7_SB_UNK_0000_0c30"; case 0x00000c31: return "I7_SB_UNK_0000_0c31";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c32: return "I7_SB_UNK_0000_0c32"; case 0x00000c33: return "I7_SB_UNK_0000_0c33";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0x00000c34: return "I7_SB_UNK_0000_0c34"; case 0x00000c35: return "I7_SB_UNK_0000_0c35";
78df65edff21c11c537f38e736707ea434ab5623vboxsync case 0x00000c36: return "I7_SB_UNK_0000_0c36"; case 0x00000c37: return "I7_SB_UNK_0000_0c37";
02e851310fa6b70ff20500172a9758a50731a451vboxsync case 0x00000c38: return "I7_SB_UNK_0000_0c38"; case 0x00000c39: return "I7_SB_UNK_0000_0c39";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d04: return "I7_SB_UNK_0000_0d04";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d10: return "I7_SB_UNK_0000_0d10"; case 0x00000d11: return "I7_SB_UNK_0000_0d11";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d12: return "I7_SB_UNK_0000_0d12"; case 0x00000d13: return "I7_SB_UNK_0000_0d13";
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0x00000d14: return "I7_SB_UNK_0000_0d14"; case 0x00000d15: return "I7_SB_UNK_0000_0d15";
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0x00000d16: return "I7_SB_UNK_0000_0d16"; case 0x00000d17: return "I7_SB_UNK_0000_0d17";
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0x00000d18: return "I7_SB_UNK_0000_0d18"; case 0x00000d19: return "I7_SB_UNK_0000_0d19";
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0x00000d24: return "I7_SB_UNK_0000_0d24";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d30: return "I7_SB_UNK_0000_0d30"; case 0x00000d31: return "I7_SB_UNK_0000_0d31";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d32: return "I7_SB_UNK_0000_0d32"; case 0x00000d33: return "I7_SB_UNK_0000_0d33";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d34: return "I7_SB_UNK_0000_0d34"; case 0x00000d35: return "I7_SB_UNK_0000_0d35";
a144bb4a097a1818739e00ba31bea88ce63f5345vboxsync case 0x00000d36: return "I7_SB_UNK_0000_0d36"; case 0x00000d37: return "I7_SB_UNK_0000_0d37";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0x00000d38: return "I7_SB_UNK_0000_0d38"; case 0x00000d39: return "I7_SB_UNK_0000_0d39";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0x00000d44: return "I7_SB_UNK_0000_0d44";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d50: return "I7_SB_UNK_0000_0d50"; case 0x00000d51: return "I7_SB_UNK_0000_0d51";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d52: return "I7_SB_UNK_0000_0d52"; case 0x00000d53: return "I7_SB_UNK_0000_0d53";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d54: return "I7_SB_UNK_0000_0d54"; case 0x00000d55: return "I7_SB_UNK_0000_0d55";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d56: return "I7_SB_UNK_0000_0d56"; case 0x00000d57: return "I7_SB_UNK_0000_0d57";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d58: return "I7_SB_UNK_0000_0d58"; case 0x00000d59: return "I7_SB_UNK_0000_0d59";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d64: return "I7_SB_UNK_0000_0d64";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d70: return "I7_SB_UNK_0000_0d70"; case 0x00000d71: return "I7_SB_UNK_0000_0d71";
78df65edff21c11c537f38e736707ea434ab5623vboxsync case 0x00000d72: return "I7_SB_UNK_0000_0d72"; case 0x00000d73: return "I7_SB_UNK_0000_0d73";
78df65edff21c11c537f38e736707ea434ab5623vboxsync case 0x00000d74: return "I7_SB_UNK_0000_0d74"; case 0x00000d75: return "I7_SB_UNK_0000_0d75";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d76: return "I7_SB_UNK_0000_0d76"; case 0x00000d77: return "I7_SB_UNK_0000_0d77";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d78: return "I7_SB_UNK_0000_0d78"; case 0x00000d79: return "I7_SB_UNK_0000_0d79";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d84: return "I7_SB_UNK_0000_0d84";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d90: return "I7_SB_UNK_0000_0d90"; case 0x00000d91: return "I7_SB_UNK_0000_0d91";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d92: return "I7_SB_UNK_0000_0d92"; case 0x00000d93: return "I7_SB_UNK_0000_0d93";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d94: return "I7_SB_UNK_0000_0d94"; case 0x00000d95: return "I7_SB_UNK_0000_0d95";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d96: return "I7_SB_UNK_0000_0d96"; case 0x00000d97: return "I7_SB_UNK_0000_0d97";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d98: return "I7_SB_UNK_0000_0d98"; case 0x00000d99: return "I7_SB_UNK_0000_0d99";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000da4: return "I7_SB_UNK_0000_0da4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000db0: return "I7_SB_UNK_0000_0db0"; case 0x00000db1: return "I7_SB_UNK_0000_0db1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000db2: return "I7_SB_UNK_0000_0db2"; case 0x00000db3: return "I7_SB_UNK_0000_0db3";
090c459b9e90ca46e2ce2b8c81533ade3b23f3e9vboxsync case 0x00000db4: return "I7_SB_UNK_0000_0db4"; case 0x00000db5: return "I7_SB_UNK_0000_0db5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000db6: return "I7_SB_UNK_0000_0db6"; case 0x00000db7: return "I7_SB_UNK_0000_0db7";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000db8: return "I7_SB_UNK_0000_0db8"; case 0x00000db9: return "I7_SB_UNK_0000_0db9";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync }
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync /*
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync * Ditto for ivy bridge (observed on the i5-3570). There are some haswell
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * and sandybridge related docs on registers in this ares, but either
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * things are different for ivy or they're very incomplete. Again, kudos
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * to intel!
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_IvyBridge)
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync switch (uMsr)
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000700: return "I7_IB_UNK_0000_0700"; case 0x00000701: return "I7_IB_UNK_0000_0701";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000702: return "I7_IB_UNK_0000_0702"; case 0x00000703: return "I7_IB_UNK_0000_0703";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000704: return "I7_IB_UNK_0000_0704"; case 0x00000705: return "I7_IB_UNK_0000_0705";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000706: return "I7_IB_UNK_0000_0706"; case 0x00000707: return "I7_IB_UNK_0000_0707";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000708: return "I7_IB_UNK_0000_0708"; case 0x00000709: return "I7_IB_UNK_0000_0709";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x00000710: return "I7_IB_UNK_0000_0710"; case 0x00000711: return "I7_IB_UNK_0000_0711";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000712: return "I7_IB_UNK_0000_0712"; case 0x00000713: return "I7_IB_UNK_0000_0713";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000714: return "I7_IB_UNK_0000_0714"; case 0x00000715: return "I7_IB_UNK_0000_0715";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x00000716: return "I7_IB_UNK_0000_0716"; case 0x00000717: return "I7_IB_UNK_0000_0717";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000718: return "I7_IB_UNK_0000_0718"; case 0x00000719: return "I7_IB_UNK_0000_0719";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x00000720: return "I7_IB_UNK_0000_0720"; case 0x00000721: return "I7_IB_UNK_0000_0721";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000722: return "I7_IB_UNK_0000_0722"; case 0x00000723: return "I7_IB_UNK_0000_0723";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000724: return "I7_IB_UNK_0000_0724"; case 0x00000725: return "I7_IB_UNK_0000_0725";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0x00000726: return "I7_IB_UNK_0000_0726"; case 0x00000727: return "I7_IB_UNK_0000_0727";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x00000728: return "I7_IB_UNK_0000_0728"; case 0x00000729: return "I7_IB_UNK_0000_0729";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000730: return "I7_IB_UNK_0000_0730"; case 0x00000731: return "I7_IB_UNK_0000_0731";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x00000732: return "I7_IB_UNK_0000_0732"; case 0x00000733: return "I7_IB_UNK_0000_0733";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0x00000734: return "I7_IB_UNK_0000_0734"; case 0x00000735: return "I7_IB_UNK_0000_0735";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000736: return "I7_IB_UNK_0000_0736"; case 0x00000737: return "I7_IB_UNK_0000_0737";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000738: return "I7_IB_UNK_0000_0738"; case 0x00000739: return "I7_IB_UNK_0000_0739";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000740: return "I7_IB_UNK_0000_0740"; case 0x00000741: return "I7_IB_UNK_0000_0741";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x00000742: return "I7_IB_UNK_0000_0742"; case 0x00000743: return "I7_IB_UNK_0000_0743";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000744: return "I7_IB_UNK_0000_0744"; case 0x00000745: return "I7_IB_UNK_0000_0745";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0x00000746: return "I7_IB_UNK_0000_0746"; case 0x00000747: return "I7_IB_UNK_0000_0747";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000748: return "I7_IB_UNK_0000_0748"; case 0x00000749: return "I7_IB_UNK_0000_0749";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync }
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync return NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/**
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Gets the name of an MSR.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync * This may return a static buffer, so the content should only be considered
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync * valid until the next time this function is called!.
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync *
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync * @returns MSR name.
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync * @param uMsr The MSR in question.
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync */
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsyncstatic const char *getMsrName(uint32_t uMsr)
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync const char *pszReadOnly = getMsrNameHandled(uMsr);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (pszReadOnly)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return pszReadOnly;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /*
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * This MSR needs looking into, return a TODO_XXXX_XXXX name.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync static char s_szBuf[32];
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTStrPrintf(s_szBuf, sizeof(s_szBuf), "TODO_%04x_%04x", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return s_szBuf;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/**
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Gets the name of an MSR range.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * This may return a static buffer, so the content should only be considered
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * valid until the next time this function is called!.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @returns MSR name.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param uMsr The first MSR in the range.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic const char *getMsrRangeName(uint32_t uMsr)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync switch (uMsr)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000040:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_n_FROM_IP" : "MSR_LASTBRANCH_n";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000060:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "MSR_LASTBRANCH_n_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync break;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003f8:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003f9:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fa:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "I7_MSR_PKG_Cn_RESIDENCY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fc:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fd:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fe:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "I7_MSR_CORE_Cn_RESIDENCY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000400:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "IA32_MCi_CTL_STATUS_ADDR_MISC";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000680:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "MSR_LASTBRANCH_n_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006c0:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "MSR_LASTBRANCH_n_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000800: case 0x00000801: case 0x00000802: case 0x00000803:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000804: case 0x00000805: case 0x00000806: case 0x00000807:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000808: case 0x00000809: case 0x0000080a: case 0x0000080b:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000080c: case 0x0000080d: case 0x0000080e: case 0x0000080f:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "IA32_X2APIC_n";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync static char s_szBuf[96];
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync const char *pszReadOnly = getMsrNameHandled(uMsr);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (pszReadOnly)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /*
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Replace the last char with 'n'.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTStrCopy(s_szBuf, sizeof(s_szBuf), pszReadOnly);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync size_t off = strlen(s_szBuf);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (off > 0)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync off--;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (off + 1 < sizeof(s_szBuf))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync s_szBuf[off] = 'n';
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync s_szBuf[off + 1] = '\0';
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync else
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /*
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * This MSR needs looking into, return a TODO_XXXX_XXXX_n name.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTStrPrintf(s_szBuf, sizeof(s_szBuf), "TODO_%04x_%04x_n", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync }
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return s_szBuf;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync}
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/**
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Returns the function name for MSRs that have one or two.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @returns Function name if applicable, NULL if not.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param uMsr The MSR in question.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param pfTakesValue Whether this MSR function takes a value or not.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Optional.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic const char *getMsrFnName(uint32_t uMsr, bool *pfTakesValue)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync{
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync bool fTmp;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (!pfTakesValue)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync pfTakesValue = &fTmp;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *pfTakesValue = false;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync switch (uMsr)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync {
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000000: return "Ia32P5McAddr";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000001: return "Ia32P5McType";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000006:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (g_enmMicroarch >= kCpumMicroarch_Intel_First && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_First)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return NULL; /* TR4 / cache tag on Pentium, but that's for later. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "Ia32MonitorFilterLineSize";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000010: return "Ia32TimestampCounter";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000001b: return "Ia32ApicBase";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000002a: *pfTakesValue = true; return "IntelEblCrPowerOn";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x00000033: return "IntelTestCtl";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000003a: return "Ia32FeatureControl";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000040:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000041:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000042:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000043:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000044:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000045:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000046:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000047:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "IntelLastBranchFromToN";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000009b: return "Ia32SmmMonitorCtl";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000a8:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000a9:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000aa:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ab:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ac:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ad:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync *pfTakesValue = true;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "IntelCore2EmttmCrTablesN";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c1:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c2:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c3:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c4:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "Ia32PmcN";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c5:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c6:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c7:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c8:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "Ia32PmcN";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e2: return "IntelPkgCStConfigControl";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e3: return "IntelCore2SmmCStMiscInfo";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e4: return "IntelPmgIoCaptureBase";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e7: return "Ia32MPerf";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e8: return "Ia32APerf";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ee: return "IntelCore1ExtConfig";
case 0x000000fe: *pfTakesValue = true; return "Ia32MtrrCap";
case 0x00000119: *pfTakesValue = true; return "IntelBblCrCtl";
case 0x0000011e: *pfTakesValue = true; return "IntelBblCrCtl3";
case 0x00000130: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
|| g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
? "IntelCpuId1FeatureMaskEcdx" : NULL;
case 0x00000131: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
|| g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
? "IntelCpuId80000001FeatureMaskEcdx" : NULL;
case 0x00000132: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
? "IntelCpuId1FeatureMaskEax" : NULL;
case 0x00000133: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
? "IntelCpuId1FeatureMaskEcdx" : NULL;
case 0x00000134: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
? "IntelCpuId80000001FeatureMaskEcdx" : NULL;
case 0x0000013c: return "IntelI7SandyAesNiCtl";
case 0x0000015f: return "IntelCore1DtsCalControl";
case 0x00000174: return "Ia32SysEnterCs";
case 0x00000175: return "Ia32SysEnterEsp";
case 0x00000176: return "Ia32SysEnterEip";
case 0x00000179: *pfTakesValue = true; return "Ia32McgCap";
case 0x0000017a: return "Ia32McgStatus";
case 0x0000017b: return "Ia32McgCtl";
case 0x0000017f: return "IntelI7SandyErrorControl"; /* SandyBridge. */
case 0x00000186: return "Ia32PerfEvtSelN";
case 0x00000187: return "Ia32PerfEvtSelN";
case 0x00000193: return /*CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? NULL :*/ NULL /* Core2_Penryn. */;
case 0x00000198: *pfTakesValue = true; return "Ia32PerfStatus";
case 0x00000199: *pfTakesValue = true; return "Ia32PerfCtl";
case 0x0000019a: *pfTakesValue = true; return "Ia32ClockModulation";
case 0x0000019b: *pfTakesValue = true; return "Ia32ThermInterrupt";
case 0x0000019c: *pfTakesValue = true; return "Ia32ThermStatus";
case 0x0000019d: *pfTakesValue = true; return "Ia32Therm2Ctl";
case 0x000001a0: *pfTakesValue = true; return "Ia32MiscEnable";
case 0x000001a2: *pfTakesValue = true; return "IntelI7TemperatureTarget";
case 0x000001a6: return "IntelI7MsrOffCoreResponseN";
case 0x000001a7: return "IntelI7MsrOffCoreResponseN";
case 0x000001aa: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "IntelI7MiscPwrMgmt" : NULL /*"P6PicSensCfg"*/;
case 0x000001ad: *pfTakesValue = true; return "IntelI7TurboRatioLimit"; /* SandyBridge+, Silvermount+ */
case 0x000001c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Nehalem ? "IntelI7LbrSelect" : NULL;
case 0x000001c9: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
&& g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_End
? "IntelLastBranchTos" : NULL /* Pentium M Dothan seems to have something else here. */;
case 0x000001d9: return "Ia32DebugCtl";
case 0x000001db: return "P6LastBranchFromIp";
case 0x000001dc: return "P6LastBranchToIp";
case 0x000001dd: return "P6LastIntFromIp";
case 0x000001de: return "P6LastIntToIp";
case 0x000001f0: return "IntelI7VirtualLegacyWireCap"; /* SandyBridge. */
case 0x000001f2: return "Ia32SmrrPhysBase";
case 0x000001f3: return "Ia32SmrrPhysMask";
case 0x000001f8: return "Ia32PlatformDcaCap";
case 0x000001f9: return "Ia32CpuDcaCap";
case 0x000001fa: return "Ia32Dca0Cap";
case 0x000001fc: return "IntelI7PowerCtl";
case 0x00000200: case 0x00000202: case 0x00000204: case 0x00000206:
case 0x00000208: case 0x0000020a: case 0x0000020c: case 0x0000020e:
case 0x00000210: case 0x00000212: case 0x00000214: case 0x00000216:
case 0x00000218: case 0x0000021a: case 0x0000021c: case 0x0000021e:
return "Ia32MtrrPhysBaseN";
case 0x00000201: case 0x00000203: case 0x00000205: case 0x00000207:
case 0x00000209: case 0x0000020b: case 0x0000020d: case 0x0000020f:
case 0x00000211: case 0x00000213: case 0x00000215: case 0x00000217:
case 0x00000219: case 0x0000021b: case 0x0000021d: case 0x0000021f:
return "Ia32MtrrPhysMaskN";
case 0x00000250:
case 0x00000258: case 0x00000259:
case 0x00000268: case 0x00000269: case 0x0000026a: case 0x0000026b:
case 0x0000026c: case 0x0000026d: case 0x0000026e: case 0x0000026f:
return "Ia32MtrrFixed";
case 0x00000277: *pfTakesValue = true; return "Ia32Pat";
case 0x00000280: case 0x00000281: case 0x00000282: case 0x00000283:
case 0x00000284: case 0x00000285: case 0x00000286: case 0x00000287:
case 0x00000288: case 0x00000289: case 0x0000028a: case 0x0000028b:
case 0x0000028c: case 0x0000028d: case 0x0000028e: case 0x0000028f:
case 0x00000290: case 0x00000291: case 0x00000292: case 0x00000293:
case 0x00000294: case 0x00000295: //case 0x00000296: case 0x00000297:
//case 0x00000298: case 0x00000299: case 0x0000029a: case 0x0000029b:
//case 0x0000029c: case 0x0000029d: case 0x0000029e: case 0x0000029f:
return "Ia32McNCtl2";
case 0x000002ff: return "Ia32MtrrDefType";
//case 0x00000305: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? TODO : NULL;
case 0x00000309: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
case 0x0000030a: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
case 0x0000030b: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
case 0x00000345: *pfTakesValue = true; return "Ia32PerfCapabilities";
case 0x0000038d: return "Ia32FixedCtrCtrl";
case 0x0000038e: *pfTakesValue = true; return "Ia32PerfGlobalStatus";
case 0x0000038f: return "Ia32PerfGlobalCtrl";
case 0x00000390: return "Ia32PerfGlobalOvfCtrl";
case 0x00000391: return "IntelI7UncPerfGlobalCtrl"; /* S,H,X */
case 0x00000392: return "IntelI7UncPerfGlobalStatus"; /* S,H,X */
case 0x00000393: return "IntelI7UncPerfGlobalOvfCtrl"; /* X. ASSUMING this is the same on sandybridge and later. */
case 0x00000394: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPerfFixedCtr" /* X */ : "IntelI7UncPerfFixedCtrCtrl"; /* >= S,H */
case 0x00000395: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPerfFixedCtrCtrl" /* X*/ : "IntelI7UncPerfFixedCtr"; /* >= S,H */
case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncAddrOpcodeMatch" /* X */ : "IntelI7UncCBoxConfig"; /* >= S,H */
case 0x0000039c: return "IntelI7SandyPebsNumAlt";
case 0x000003b0: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfCtrN"; /* >= S,H */
case 0x000003b1: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfCtrN"; /* >= S,H */
case 0x000003b2: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfEvtSelN"; /* >= S,H */
case 0x000003b3: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfEvtSelN"; /* >= S,H */
case 0x000003b4: case 0x000003b5: case 0x000003b6: case 0x000003b7:
return "IntelI7UncPmcN";
case 0x000003c0: case 0x000003c1: case 0x000003c2: case 0x000003c3:
case 0x000003c4: case 0x000003c5: case 0x000003c6: case 0x000003c7:
return "IntelI7UncPerfEvtSelN";
case 0x000003f1: return "Ia32PebsEnable";
case 0x000003f6: return "IntelI7PebsLdLat";
case 0x000003f8: return "IntelI7PkgCnResidencyN";
case 0x000003f9: return "IntelI7PkgCnResidencyN";
case 0x000003fa: return "IntelI7PkgCnResidencyN";
case 0x000003fc: return "IntelI7CoreCnResidencyN";
case 0x000003fd: return "IntelI7CoreCnResidencyN";
case 0x000003fe: return "IntelI7CoreCnResidencyN";
case 0x00000478: return g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "IntelCpuId1FeatureMaskEcdx" : NULL;
case 0x00000480: *pfTakesValue = true; return "Ia32VmxBase";
case 0x00000481: *pfTakesValue = true; return "Ia32VmxPinbasedCtls";
case 0x00000482: *pfTakesValue = true; return "Ia32VmxProcbasedCtls";
case 0x00000483: *pfTakesValue = true; return "Ia32VmxExitCtls";
case 0x00000484: *pfTakesValue = true; return "Ia32VmxEntryCtls";
case 0x00000485: *pfTakesValue = true; return "Ia32VmxMisc";
case 0x00000486: *pfTakesValue = true; return "Ia32VmxCr0Fixed0";
case 0x00000487: *pfTakesValue = true; return "Ia32VmxCr0Fixed1";
case 0x00000488: *pfTakesValue = true; return "Ia32VmxCr4Fixed0";
case 0x00000489: *pfTakesValue = true; return "Ia32VmxCr4Fixed1";
case 0x0000048a: *pfTakesValue = true; return "Ia32VmxVmcsEnum";
case 0x0000048b: *pfTakesValue = true; return "Ia32VmxProcBasedCtls2";
case 0x0000048c: *pfTakesValue = true; return "Ia32VmxEptVpidCap";
case 0x0000048d: *pfTakesValue = true; return "Ia32VmxTruePinbasedCtls";
case 0x0000048e: *pfTakesValue = true; return "Ia32VmxTrueProcbasedCtls";
case 0x0000048f: *pfTakesValue = true; return "Ia32VmxTrueExitCtls";
case 0x00000490: *pfTakesValue = true; return "Ia32VmxTrueEntryCtls";
case 0x000004c1:
case 0x000004c2:
case 0x000004c3:
case 0x000004c4:
case 0x000004c5:
case 0x000004c6:
case 0x000004c7:
case 0x000004c8:
return "Ia32PmcN";
case 0x000005a0: return "IntelCore2PeciControl"; /* Core2_Penryn. */
case 0x00000600: return "Ia32DsArea";
case 0x00000601: return "IntelI7SandyVrCurrentConfig";
case 0x00000603: return "IntelI7SandyVrMiscConfig";
case 0x00000606: return "IntelI7SandyRaplPowerUnit";
case 0x0000060a: return "IntelI7SandyPkgCnIrtlN";
case 0x0000060b: return "IntelI7SandyPkgCnIrtlN";
case 0x0000060c: return "IntelI7SandyPkgCnIrtlN";
case 0x0000060d: return "IntelI7SandyPkgC2Residency";
case 0x00000610: return "IntelI7RaplPkgPowerLimit";
case 0x00000611: return "IntelI7RaplPkgEnergyStatus";
case 0x00000613: return "IntelI7RaplPkgPerfStatus";
case 0x00000614: return "IntelI7RaplPkgPowerInfo";
case 0x00000618: return "IntelI7RaplDramPowerLimit";
case 0x00000619: return "IntelI7RaplDramEnergyStatus";
case 0x0000061b: return "IntelI7RaplDramPerfStatus";
case 0x0000061c: return "IntelI7RaplDramPowerInfo";
case 0x00000638: return "IntelI7RaplPp0PowerLimit";
case 0x00000639: return "IntelI7RaplPp0EnergyStatus";
case 0x0000063a: return "IntelI7RaplPp0Policy";
case 0x0000063b: return "IntelI7RaplPp0PerfStatus";
case 0x00000640: return "IntelI7RaplPp1PowerLimit";
case 0x00000641: return "IntelI7RaplPp1EnergyStatus";
case 0x00000642: return "IntelI7RaplPp1Policy";
case 0x00000648: return "IntelI7IvyConfigTdpNominal";
case 0x00000649: return "IntelI7IvyConfigTdpLevel1";
case 0x0000064a: return "IntelI7IvyConfigTdpLevel2";
case 0x0000064b: return "IntelI7IvyConfigTdpControl";
case 0x0000064c: return "IntelI7IvyTurboActivationRatio";
case 0x00000680: case 0x00000681: case 0x00000682: case 0x00000683:
case 0x00000684: case 0x00000685: case 0x00000686: case 0x00000687:
case 0x00000688: case 0x00000689: case 0x0000068a: case 0x0000068b:
case 0x0000068c: case 0x0000068d: case 0x0000068e: case 0x0000068f:
//case 0x00000690: case 0x00000691: case 0x00000692: case 0x00000693:
//case 0x00000694: case 0x00000695: case 0x00000696: case 0x00000697:
//case 0x00000698: case 0x00000699: case 0x0000069a: case 0x0000069b:
//case 0x0000069c: case 0x0000069d: case 0x0000069e: case 0x0000069f:
return "IntelLastBranchFromN";
case 0x000006c0: case 0x000006c1: case 0x000006c2: case 0x000006c3:
case 0x000006c4: case 0x000006c5: case 0x000006c6: case 0x000006c7:
case 0x000006c8: case 0x000006c9: case 0x000006ca: case 0x000006cb:
case 0x000006cc: case 0x000006cd: case 0x000006ce: case 0x000006cf:
//case 0x000006d0: case 0x000006d1: case 0x000006d2: case 0x000006d3:
//case 0x000006d4: case 0x000006d5: case 0x000006d6: case 0x000006d7:
//case 0x000006d8: case 0x000006d9: case 0x000006da: case 0x000006db:
//case 0x000006dc: case 0x000006dd: case 0x000006de: case 0x000006df:
return "IntelLastBranchToN";
case 0x000006e0: return "Ia32TscDeadline"; /** @todo detect this correctly! */
case 0x00000c80: return g_enmMicroarch > kCpumMicroarch_Intel_Core7_Nehalem ? "Ia32DebugInterface" : NULL;
case 0xc0000080: return "Amd64Efer";
case 0xc0000081: return "Amd64SyscallTarget";
case 0xc0000082: return "Amd64LongSyscallTarget";
case 0xc0000083: return "Amd64CompSyscallTarget";
case 0xc0000084: return "Amd64SyscallFlagMask";
case 0xc0000100: return "Amd64FsBase";
case 0xc0000101: return "Amd64GsBase";
case 0xc0000102: return "Amd64KernelGsBase";
case 0xc0000103: return "Amd64TscAux";
case 0xc0000104: return "AmdFam15hTscRate";
case 0xc0000105: return "AmdFam15hLwpCfg";
case 0xc0000106: return "AmdFam15hLwpCbAddr";
case 0xc0000408: return "AmdFam10hMc4MiscN";
case 0xc0000409: return "AmdFam10hMc4MiscN";
case 0xc000040a: return "AmdFam10hMc4MiscN";
case 0xc000040b: return "AmdFam10hMc4MiscN";
case 0xc000040c: return "AmdFam10hMc4MiscN";
case 0xc000040d: return "AmdFam10hMc4MiscN";
case 0xc000040e: return "AmdFam10hMc4MiscN";
case 0xc000040f: return "AmdFam10hMc4MiscN";
case 0xc0010000: return "AmdK8PerfCtlN";
case 0xc0010001: return "AmdK8PerfCtlN";
case 0xc0010002: return "AmdK8PerfCtlN";
case 0xc0010003: return "AmdK8PerfCtlN";
case 0xc0010004: return "AmdK8PerfCtrN";
case 0xc0010005: return "AmdK8PerfCtrN";
case 0xc0010006: return "AmdK8PerfCtrN";
case 0xc0010007: return "AmdK8PerfCtrN";
case 0xc0010010: *pfTakesValue = true; return "AmdK8SysCfg";
case 0xc0010015: return "AmdK8HwCr";
case 0xc0010016: case 0xc0010018: return "AmdK8IorrBaseN";
case 0xc0010017: case 0xc0010019: return "AmdK8IorrMaskN";
case 0xc001001a: case 0xc001001d: return "AmdK8TopOfMemN";
case 0xc001001f: return "AmdK8NbCfg1";
case 0xc0010022: return "AmdK8McXcptRedir";
case 0xc0010030: case 0xc0010031: case 0xc0010032:
case 0xc0010033: case 0xc0010034: case 0xc0010035:
return "AmdK8CpuNameN";
case 0xc001003e: *pfTakesValue = true; return "AmdK8HwThermalCtrl";
case 0xc001003f: return "AmdK8SwThermalCtrl";
case 0xc0010044: case 0xc0010045: case 0xc0010046: case 0xc0010047:
case 0xc0010048: case 0xc0010049: case 0xc001004a: //case 0xc001004b:
return "AmdK8McCtlMaskN";
case 0xc0010050: case 0xc0010051: case 0xc0010052: case 0xc0010053:
return "AmdK8SmiOnIoTrapN";
case 0xc0010054: return "AmdK8SmiOnIoTrapCtlSts";
case 0xc0010055: return "AmdK8IntPendingMessage";
case 0xc0010056: return "AmdK8SmiTriggerIoCycle";
case 0xc0010058: return "AmdFam10hMmioCfgBaseAddr";
case 0xc0010059: return "AmdFam10hTrapCtlMaybe";
case 0xc0010061: *pfTakesValue = true; return "AmdFam10hPStateCurLimit";
case 0xc0010062: *pfTakesValue = true; return "AmdFam10hPStateControl";
case 0xc0010063: *pfTakesValue = true; return "AmdFam10hPStateStatus";
case 0xc0010064: case 0xc0010065: case 0xc0010066: case 0xc0010067:
case 0xc0010068: case 0xc0010069: case 0xc001006a: case 0xc001006b:
*pfTakesValue = true; return "AmdFam10hPStateN";
case 0xc0010070: *pfTakesValue = true; return "AmdFam10hCofVidControl";
case 0xc0010071: *pfTakesValue = true; return "AmdFam10hCofVidStatus";
case 0xc0010073: return "AmdFam10hCStateIoBaseAddr";
case 0xc0010074: return "AmdFam10hCpuWatchdogTimer";
// case 0xc0010075: return "AmdFam15hApmlTdpLimit";
// case 0xc0010077: return "AmdFam15hCpuPowerInTdp";
// case 0xc0010078: return "AmdFam15hPowerAveragingPeriod";
// case 0xc0010079: return "AmdFam15hDramCtrlCmdThrottle";
// case 0xc0010080: return "AmdFam16hFreqSensFeedbackMonActCnt0";
// case 0xc0010081: return "AmdFam16hFreqSensFeedbackMonRefCnt0";
case 0xc0010111: return "AmdK8SmmBase"; /** @todo probably misdetected ign/gp due to locking */
case 0xc0010112: return "AmdK8SmmAddr"; /** @todo probably misdetected ign/gp due to locking */
case 0xc0010113: return "AmdK8SmmMask"; /** @todo probably misdetected ign/gp due to locking */
case 0xc0010114: return "AmdK8VmCr"; /** @todo probably misdetected due to locking */
case 0xc0010115: return "AmdK8IgnNe";
case 0xc0010116: return "AmdK8SmmCtl";
case 0xc0010117: return "AmdK8VmHSavePa"; /** @todo probably misdetected due to locking */
case 0xc0010118: return "AmdFam10hVmLockKey";
case 0xc0010119: return "AmdFam10hSmmLockKey"; /* Not documented by BKDG, found in netbsd patch. */
case 0xc001011a: return "AmdFam10hLocalSmiStatus";
case 0xc0010140: *pfTakesValue = true; return "AmdFam10hOsVisWrkIdLength";
case 0xc0010141: *pfTakesValue = true; return "AmdFam10hOsVisWrkStatus";
case 0xc0010200: case 0xc0010202: case 0xc0010204: case 0xc0010206:
case 0xc0010208: case 0xc001020a: //case 0xc001020c: case 0xc001020e:
return "AmdK8PerfCtlN";
case 0xc0010201: case 0xc0010203: case 0xc0010205: case 0xc0010207:
case 0xc0010209: case 0xc001020b: //case 0xc001020d: case 0xc001020f:
return "AmdK8PerfCtrN";
case 0xc0010230: case 0xc0010232: case 0xc0010234: case 0xc0010236:
//case 0xc0010238: case 0xc001023a: case 0xc001030c: case 0xc001023e:
return "AmdFam16hL2IPerfCtlN";
case 0xc0010231: case 0xc0010233: case 0xc0010235: case 0xc0010237:
//case 0xc0010239: case 0xc001023b: case 0xc001023d: case 0xc001023f:
return "AmdFam16hL2IPerfCtrN";
case 0xc0010240: case 0xc0010242: case 0xc0010244: case 0xc0010246:
//case 0xc0010248: case 0xc001024a: case 0xc001024c: case 0xc001024e:
return "AmdFam15hNorthbridgePerfCtlN";
case 0xc0010241: case 0xc0010243: case 0xc0010245: case 0xc0010247:
//case 0xc0010249: case 0xc001024b: case 0xc001024d: case 0xc001024f:
return "AmdFam15hNorthbridgePerfCtrN";
case 0xc0011000: *pfTakesValue = true; return "AmdK7MicrocodeCtl";
case 0xc0011001: *pfTakesValue = true; return "AmdK7ClusterIdMaybe";
case 0xc0011002: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd07hEbax" : NULL;
case 0xc0011003: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd06hEcx" : NULL;
case 0xc0011004: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd01hEdcx" : NULL;
case 0xc0011005: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlExt01hEdcx" : NULL;
case 0xc0011006: return "AmdK7DebugStatusMaybe";
case 0xc0011007: return "AmdK7BHTraceBaseMaybe";
case 0xc0011008: return "AmdK7BHTracePtrMaybe";
case 0xc0011009: return "AmdK7BHTraceLimitMaybe";
case 0xc001100a: return "AmdK7HardwareDebugToolCfgMaybe";
case 0xc001100b: return "AmdK7FastFlushCountMaybe";
case 0xc001100c: return "AmdK7NodeId"; /** @todo dunno if this was there is K7 already. Kinda doubt it. */
case 0xc0011019: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
case 0xc001101a: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
case 0xc001101b: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
case 0xc0011020: return "AmdK7LoadStoreCfg";
case 0xc0011021: return "AmdK7InstrCacheCfg";
case 0xc0011022: return "AmdK7DataCacheCfg";
case 0xc0011023: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg" : "AmdK7BusUnitCfg";
case 0xc0011024: return "AmdK7DebugCtl2Maybe";
case 0xc0011025: return "AmdK7Dr0DataMatchMaybe";
case 0xc0011026: return "AmdK7Dr0DataMaskMaybe";
case 0xc0011027: return "AmdK7DrXAddrMaskN";
case 0xc0011028: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AmdFam15hFpuCfg" : NULL;
case 0xc0011029: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AmdFam15hDecoderCfg" : NULL;
case 0xc001102a: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg2"
: CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) || g_enmMicroarch > kCpumMicroarch_AMD_15h_End
? "AmdFam10hBusUnitCfg2" /* 10h & 16h */ : NULL;
case 0xc001102b: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg3" : NULL;
case 0xc001102c: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hExecUnitCfg" : NULL;
case 0xc001102d: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hLoadStoreCfg2" : NULL;
case 0xc0011030: return "AmdFam10hIbsFetchCtl";
case 0xc0011031: return "AmdFam10hIbsFetchLinAddr";
case 0xc0011032: return "AmdFam10hIbsFetchPhysAddr";
case 0xc0011033: return "AmdFam10hIbsOpExecCtl";
case 0xc0011034: return "AmdFam10hIbsOpRip";
case 0xc0011035: return "AmdFam10hIbsOpData";
case 0xc0011036: return "AmdFam10hIbsOpData2";
case 0xc0011037: return "AmdFam10hIbsOpData3";
case 0xc0011038: return "AmdFam10hIbsDcLinAddr";
case 0xc0011039: return "AmdFam10hIbsDcPhysAddr";
case 0xc001103a: return "AmdFam10hIbsCtl";
case 0xc001103b: return "AmdFam14hIbsBrTarget";
}
return NULL;
}
/**
* Names CPUMCPU variables that MSRs corresponds to.
*
* @returns The variable name @a uMsr corresponds to, NULL if no variable.
* @param uMsr The MSR in question.
*/
static const char *getMsrCpumCpuVarName(uint32_t uMsr)
{
switch (uMsr)
{
case 0x00000250: return "GuestMsrs.msr.MtrrFix64K_00000";
case 0x00000258: return "GuestMsrs.msr.MtrrFix16K_80000";
case 0x00000259: return "GuestMsrs.msr.MtrrFix16K_A0000";
case 0x00000268: return "GuestMsrs.msr.MtrrFix4K_C0000";
case 0x00000269: return "GuestMsrs.msr.MtrrFix4K_C8000";
case 0x0000026a: return "GuestMsrs.msr.MtrrFix4K_D0000";
case 0x0000026b: return "GuestMsrs.msr.MtrrFix4K_D8000";
case 0x0000026c: return "GuestMsrs.msr.MtrrFix4K_E0000";
case 0x0000026d: return "GuestMsrs.msr.MtrrFix4K_E8000";
case 0x0000026e: return "GuestMsrs.msr.MtrrFix4K_F0000";
case 0x0000026f: return "GuestMsrs.msr.MtrrFix4K_F8000";
case 0x00000277: return "Guest.msrPAT";
case 0x000002ff: return "GuestMsrs.msr.MtrrDefType";
}
return NULL;
}
/**
* Checks whether the MSR should read as zero for some reason.
*
* @returns true if the register should read as zero, false if not.
* @param uMsr The MSR.
*/
static bool doesMsrReadAsZero(uint32_t uMsr)
{
switch (uMsr)
{
case 0x00000088: return true; // "BBL_CR_D0" - RAZ until understood/needed.
case 0x00000089: return true; // "BBL_CR_D1" - RAZ until understood/needed.
case 0x0000008a: return true; // "BBL_CR_D2" - RAZ until understood/needed.
/* Non-zero, but unknown register. */
case 0x0000004a:
case 0x0000004b:
case 0x0000004c:
case 0x0000004d:
case 0x0000004e:
case 0x0000004f:
case 0x00000050:
case 0x00000051:
case 0x00000052:
case 0x00000053:
case 0x00000054:
case 0x0000008c:
case 0x0000008d:
case 0x0000008e:
case 0x0000008f:
case 0x00000090:
case 0xc0011011:
return true;
}
return false;
}
/**
* Gets the skip mask for the given MSR.
*
* @returns Skip mask (0 means skipping nothing).
* @param uMsr The MSR.
*/
static uint64_t getGenericSkipMask(uint32_t uMsr)
{
switch (uMsr)
{
case 0x0000013c: return 3; /* AES-NI lock bit ++. */
case 0x000001f2: return UINT64_C(0xfffff00f); /* Ia32SmrrPhysBase - Only writable in SMM. */
case 0x000001f3: return UINT64_C(0xfffff800); /* Ia32SmrrPhysMask - Only writable in SMM. */
/* these two have lock bits. */
case 0x0000064b: return UINT64_C(0x80000003);
case 0x0000064c: return UINT64_C(0x800000ff);
case 0xc0010015: return 1; /* SmmLock bit */
/* SmmLock effect: */
case 0xc0010111: return UINT32_MAX;
case 0xc0010112: return UINT64_C(0xfffe0000) | ((RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(uint64_t)UINT32_MAX);
case 0xc0010113: return UINT64_C(0xfffe773f) | ((RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(uint64_t)UINT32_MAX);
case 0xc0010116: return 0x1f;
case 0xc0010114: return RT_BIT_64(3) /* SVM lock */ | RT_BIT_64(4) /* SvmeDisable */;
/* Canonical */
case 0xc0011034:
case 0xc0011038:
case 0xc001103b:
return UINT64_C(0xffff800000000000);
case 0x00000060: case 0x00000061: case 0x00000062: case 0x00000063:
case 0x00000064: case 0x00000065: case 0x00000066: case 0x00000067:
case 0x00000040: case 0x00000041: case 0x00000042: case 0x00000043:
case 0x00000044: case 0x00000045: case 0x00000046: case 0x00000047:
if (g_enmMicroarch >= kCpumMicroarch_Intel_Core2_First)
return UINT64_C(0xffff800000000000);
break;
/* Time counters - fudge them to avoid incorrect ignore masks. */
case 0x00000010:
case 0x000000e7:
case 0x000000e8:
return RT_BIT_32(29) - 1;
}
return 0;
}
/** queryMsrWriteBadness return values. */
typedef enum
{
/** . */
VBCPUREPBADNESS_MOSTLY_HARMLESS = 0,
/** Not a problem if accessed with care. */
VBCPUREPBADNESS_MIGHT_BITE,
/** Worse than a bad james bond villain. */
VBCPUREPBADNESS_BOND_VILLAIN
} VBCPUREPBADNESS;
/**
* Backlisting and graylisting of MSRs which may cause tripple faults.
*
* @returns Badness factor.
* @param uMsr The MSR in question.
*/
static VBCPUREPBADNESS queryMsrWriteBadness(uint32_t uMsr)
{
/** @todo Having trouble in the 0xc0010247,0xc0011006,?? region on Bulldozer. */
/** @todo Having trouble in the 0xc001100f,0xc001100d,?? region on Opteron
* 2384. */
switch (uMsr)
{
case 0x00000050:
case 0x00000051:
case 0x00000052:
case 0x00000053:
case 0x00000054:
case 0x00001006:
case 0x00001007:
case 0xc0010010:
case 0xc0010016:
case 0xc0010017:
case 0xc0010018:
case 0xc0010019:
case 0xc001001a:
case 0xc001001d:
case 0xc001101e:
case 0xc0010064: /* P-state fequency, voltage, ++. */
case 0xc0010065: /* P-state fequency, voltage, ++. */
case 0xc0010066: /* P-state fequency, voltage, ++. */
case 0xc0010067: /* P-state fequency, voltage, ++. */
case 0xc0010068: /* P-state fequency, voltage, ++. */
case 0xc0010069: /* P-state fequency, voltage, ++. */
case 0xc001006a: /* P-state fequency, voltage, ++. */
case 0xc001006b: /* P-state fequency, voltage, ++. */
case 0xc0010070: /* COFVID Control. */
case 0xc0011021: /* IC_CFG (instruction cache configuration) */
case 0xc0011023: /* CU_CFG (combined unit configuration) */
case 0xc001102c: /* EX_CFG (execution unit configuration) */
return VBCPUREPBADNESS_BOND_VILLAIN;
case 0x000001a0: /* IA32_MISC_ENABLE */
case 0x00000199: /* IA32_PERF_CTL */
case 0x00002000: /* P6_CR0 */
case 0x00002003: /* P6_CR3 */
case 0x00002004: /* P6_CR4 */
case 0xc0000080: /* MSR_K6_EFER */
return VBCPUREPBADNESS_MIGHT_BITE;
}
return VBCPUREPBADNESS_MOSTLY_HARMLESS;
}
/**
* Prints a 64-bit value in the best way.
*
* @param uValue The value.
*/
static void printMsrValueU64(uint64_t uValue)
{
if (uValue == 0)
vbCpuRepPrintf(", 0");
else if (uValue == UINT16_MAX)
vbCpuRepPrintf(", UINT16_MAX");
else if (uValue == UINT32_MAX)
vbCpuRepPrintf(", UINT32_MAX");
else if (uValue == UINT64_MAX)
vbCpuRepPrintf(", UINT64_MAX");
else if (uValue == UINT64_C(0xffffffff00000000))
vbCpuRepPrintf(", ~(uint64_t)UINT32_MAX");
else if (uValue <= (UINT32_MAX >> 1))
vbCpuRepPrintf(", %#llx", uValue);
else if (uValue <= UINT32_MAX)
vbCpuRepPrintf(", UINT32_C(%#llx)", uValue);
else
vbCpuRepPrintf(", UINT64_C(%#llx)", uValue);
}
/**
* Prints the newline after an MSR line has been printed.
*
* This is used as a hook to slow down the output and make sure the remote
* terminal or/and output file has received the last update before we go and
* crash probing the next MSR.
*/
static void printMsrNewLine(void)
{
vbCpuRepPrintf("\n");
#if 1
RTThreadSleep(8);
#endif
}
static int printMsrWriteOnly(uint32_t uMsr, const char *pszWrFnName, const char *pszAnnotation)
{
if (!pszWrFnName)
pszWrFnName = "IgnoreWrite";
vbCpuRepPrintf(pszAnnotation
? " MFN(%#010x, \"%s\", WriteOnly, %s), /* %s */"
: " MFN(%#010x, \"%s\", WriteOnly, %s),",
uMsr, getMsrName(uMsr), pszWrFnName, pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrValueReadOnly(uint32_t uMsr, uint64_t uValue, const char *pszAnnotation)
{
vbCpuRepPrintf(" MVO(%#010x, \"%s\"", uMsr, getMsrName(uMsr));
printMsrValueU64(uValue);
vbCpuRepPrintf("),");
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrValueIgnoreWrites(uint32_t uMsr, uint64_t uValue, const char *pszAnnotation)
{
vbCpuRepPrintf(" MVI(%#010x, \"%s\"", uMsr, getMsrName(uMsr));
printMsrValueU64(uValue);
vbCpuRepPrintf("),");
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrValueExtended(uint32_t uMsr, uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask,
const char *pszAnnotation)
{
vbCpuRepPrintf(" MVX(%#010x, \"%s\"", uMsr, getMsrName(uMsr));
printMsrValueU64(uValue);
printMsrValueU64(fIgnMask);
printMsrValueU64(fGpMask);
vbCpuRepPrintf("),");
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrRangeValueReadOnly(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszAnnotation)
{
vbCpuRepPrintf(" RVO(%#010x, %#010x, \"%s\"", uMsr, uLast, getMsrRangeName(uMsr));
printMsrValueU64(uValue);
vbCpuRepPrintf("),");
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrRangeValueIgnoreWrites(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszAnnotation)
{
vbCpuRepPrintf(" RVI(%#010x, %#010x, \"%s\"", uMsr, uLast, getMsrRangeName(uMsr));
printMsrValueU64(uValue);
vbCpuRepPrintf("),");
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrFunction(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, const char *pszAnnotation)
{
if (!pszRdFnName)
pszRdFnName = getMsrFnName(uMsr, NULL);
if (!pszWrFnName)
pszWrFnName = pszRdFnName;
vbCpuRepPrintf(" MFN(%#010x, \"%s\", %s, %s),", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrFunctionReadOnly(uint32_t uMsr, const char *pszRdFnName, const char *pszAnnotation)
{
if (!pszRdFnName)
pszRdFnName = getMsrFnName(uMsr, NULL);
vbCpuRepPrintf(" MFO(%#010x, \"%s\", %s),", uMsr, getMsrName(uMsr), pszRdFnName);
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrFunctionIgnoreWrites(uint32_t uMsr, const char *pszRdFnName, const char *pszAnnotation)
{
if (!pszRdFnName)
pszRdFnName = getMsrFnName(uMsr, NULL);
vbCpuRepPrintf(" MFI(%#010x, \"%s\", %s),", uMsr, getMsrName(uMsr), pszRdFnName);
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrFunctionIgnoreMask(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName,
uint64_t fIgnMask, const char *pszAnnotation)
{
if (!pszRdFnName)
pszRdFnName = getMsrFnName(uMsr, NULL);
if (!pszWrFnName)
pszWrFnName = pszRdFnName;
vbCpuRepPrintf(" MFW(%#010x, \"%s\", %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
printMsrValueU64(fIgnMask);
vbCpuRepPrintf("),");
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrFunctionExtended(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, uint64_t uValue,
uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
{
if (!pszRdFnName)
pszRdFnName = getMsrFnName(uMsr, NULL);
if (!pszWrFnName)
pszWrFnName = pszRdFnName;
vbCpuRepPrintf(" MFX(%#010x, \"%s\", %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
printMsrValueU64(uValue);
printMsrValueU64(fIgnMask);
printMsrValueU64(fGpMask);
vbCpuRepPrintf("),");
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrFunctionExtendedIdxVal(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, uint64_t uValue,
uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
{
if (!pszRdFnName)
pszRdFnName = getMsrFnName(uMsr, NULL);
if (!pszWrFnName)
pszWrFnName = pszRdFnName;
vbCpuRepPrintf(" MFX(%#010x, \"%s\", %s, %s, %#x", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, uValue);
printMsrValueU64(fIgnMask);
printMsrValueU64(fGpMask);
vbCpuRepPrintf("),");
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrFunctionCpumCpu(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName,
const char *pszCpumCpuStorage, const char *pszAnnotation)
{
if (!pszRdFnName)
pszRdFnName = getMsrFnName(uMsr, NULL);
if (!pszWrFnName)
pszWrFnName = pszRdFnName;
if (!pszCpumCpuStorage)
pszCpumCpuStorage = getMsrCpumCpuVarName(uMsr);
if (!pszCpumCpuStorage)
return RTMsgErrorRc(VERR_NOT_FOUND, "Missing CPUMCPU member for %#s (%#x)\n", getMsrName(uMsr), uMsr);
vbCpuRepPrintf(" MFS(%#010x, \"%s\", %s, %s, %s),", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, pszCpumCpuStorage);
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrFunctionCpumCpuEx(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName,
const char *pszCpumCpuStorage, uint64_t fIgnMask, uint64_t fGpMask,
const char *pszAnnotation)
{
if (!pszRdFnName)
pszRdFnName = getMsrFnName(uMsr, NULL);
if (!pszWrFnName)
pszWrFnName = pszRdFnName;
if (!pszCpumCpuStorage)
pszCpumCpuStorage = getMsrCpumCpuVarName(uMsr);
if (!pszCpumCpuStorage)
return RTMsgErrorRc(VERR_NOT_FOUND, "Missing CPUMCPU member for %#s (%#x)\n", getMsrName(uMsr), uMsr);
vbCpuRepPrintf(" MFZ(%#010x, \"%s\", %s, %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, pszCpumCpuStorage);
printMsrValueU64(fIgnMask);
printMsrValueU64(fGpMask);
vbCpuRepPrintf("),");
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrRangeFunction(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
const char *pszAnnotation)
{
if (!pszRdFnName)
pszRdFnName = getMsrFnName(uMsr, NULL);
if (!pszWrFnName)
pszWrFnName = pszRdFnName;
vbCpuRepPrintf(" RFN(%#010x, %#010x, \"%s\", %s, %s),", uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName);
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrRangeFunctionEx(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
{
if (!pszRdFnName)
pszRdFnName = getMsrFnName(uMsr, NULL);
if (!pszWrFnName)
pszWrFnName = pszRdFnName;
vbCpuRepPrintf(" RSN(%#010x, %#010x, \"%s\", %s, %s", uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName);
printMsrValueU64(uValue);
printMsrValueU64(fIgnMask);
printMsrValueU64(fGpMask);
vbCpuRepPrintf("),");
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrRangeFunctionExIdxVal(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
{
if (!pszRdFnName)
pszRdFnName = getMsrFnName(uMsr, NULL);
if (!pszWrFnName)
pszWrFnName = pszRdFnName;
vbCpuRepPrintf(" RSN(%#010x, %#010x, \"%s\", %s, %s, %#x",
uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName, uValue);
printMsrValueU64(fIgnMask);
printMsrValueU64(fGpMask);
vbCpuRepPrintf("),");
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static int printMsrAlias(uint32_t uMsr, uint32_t uTarget, const char *pszAnnotation)
{
vbCpuRepPrintf(" MAL(%#010x, \"%s\", %#010x),", uMsr, getMsrName(uMsr), uTarget);
if (pszAnnotation)
vbCpuRepPrintf(" /* %s */", pszAnnotation);
printMsrNewLine();
return VINF_SUCCESS;
}
static const char *annotateValue(uint64_t uValue)
{
static char s_szBuf[40];
if (uValue <= UINT32_MAX)
RTStrPrintf(s_szBuf, sizeof(s_szBuf), "value=%#llx", uValue);
else
RTStrPrintf(s_szBuf, sizeof(s_szBuf), "value=%#x`%08x", RT_HI_U32(uValue), RT_LO_U32(uValue));
return s_szBuf;
}
static const char *annotateValueExtra(const char *pszExtra, uint64_t uValue)
{
static char s_szBuf[40];
if (uValue <= UINT32_MAX)
RTStrPrintf(s_szBuf, sizeof(s_szBuf), "%s value=%#llx", pszExtra, uValue);
else
RTStrPrintf(s_szBuf, sizeof(s_szBuf), "%s value=%#x`%08x", pszExtra, RT_HI_U32(uValue), RT_LO_U32(uValue));
return s_szBuf;
}
static const char *annotateIfMissingBits(uint64_t uValue, uint64_t fBits)
{
static char s_szBuf[80];
if ((uValue & fBits) == fBits)
return annotateValue(uValue);
RTStrPrintf(s_szBuf, sizeof(s_szBuf), "XXX: Unexpected value %#llx - wanted bits %#llx to be set.", uValue, fBits);
return s_szBuf;
}
static int reportMsr_Generic(uint32_t uMsr, uint32_t fFlags, uint64_t uValue)
{
int rc;
bool fTakesValue = false;
const char *pszFnName = getMsrFnName(uMsr, &fTakesValue);
if (fFlags & VBCPUREPMSR_F_WRITE_ONLY)
rc = printMsrWriteOnly(uMsr, pszFnName, NULL);
else
{
bool fReadAsZero = doesMsrReadAsZero(uMsr);
fTakesValue = fTakesValue && !fReadAsZero;
switch (queryMsrWriteBadness(uMsr))
{
/* This is what we're here for... */
case VBCPUREPBADNESS_MOSTLY_HARMLESS:
{
if ( msrProberModifyNoChange(uMsr)
|| msrProberModifyZero(uMsr))
{
uint64_t fSkipMask = getGenericSkipMask(uMsr);
uint64_t fIgnMask = 0;
uint64_t fGpMask = 0;
rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
if (RT_FAILURE(rc))
return rc;
if (pszFnName)
{
if (fGpMask == 0 && fIgnMask == UINT64_MAX && !fTakesValue)
rc = printMsrFunctionIgnoreWrites(uMsr, pszFnName, annotateValue(uValue));
else if (fGpMask == 0 && fIgnMask == 0 && (!fTakesValue || uValue == 0))
rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValue(uValue));
else
rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, fTakesValue ? uValue : 0,
fIgnMask, fGpMask, annotateValue(uValue));
}
else if (fGpMask == 0 && fIgnMask == UINT64_MAX)
rc = printMsrValueIgnoreWrites(uMsr, fReadAsZero ? 0 : uValue, fReadAsZero ? annotateValue(uValue) : NULL);
else
rc = printMsrValueExtended(uMsr, fReadAsZero ? 0 : uValue, fIgnMask, fGpMask,
fReadAsZero ? annotateValue(uValue) : NULL);
}
/* Most likely read-only. */
else if (pszFnName && !fTakesValue)
rc = printMsrFunctionReadOnly(uMsr, pszFnName, annotateValue(uValue));
else if (pszFnName)
rc = printMsrFunctionExtended(uMsr, pszFnName, "ReadOnly", uValue, 0, 0, annotateValue(uValue));
else if (fReadAsZero)
rc = printMsrValueReadOnly(uMsr, 0, annotateValue(uValue));
else
rc = printMsrValueReadOnly(uMsr, uValue, NULL);
break;
}
/* These should have special handling, so just do a simple
write back same value check to see if it's writable. */
case VBCPUREPBADNESS_MIGHT_BITE:
if (msrProberModifyNoChange(uMsr))
{
if (pszFnName && !fTakesValue)
rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValueExtra("Might bite.", uValue));
else if (pszFnName)
rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, uValue, 0, 0,
annotateValueExtra("Might bite.", uValue));
else if (fReadAsZero)
rc = printMsrValueIgnoreWrites(uMsr, 0, annotateValueExtra("Might bite.", uValue));
else
rc = printMsrValueIgnoreWrites(uMsr, uValue, "Might bite.");
}
else if (pszFnName && !fTakesValue)
rc = printMsrFunctionReadOnly(uMsr, pszFnName, annotateValueExtra("Might bite.", uValue));
else if (pszFnName)
rc = printMsrFunctionExtended(uMsr, pszFnName, "ReadOnly", uValue, 0, UINT64_MAX,
annotateValueExtra("Might bite.", uValue));
else if (fReadAsZero)
rc = printMsrValueReadOnly(uMsr, 0, annotateValueExtra("Might bite.", uValue));
else
rc = printMsrValueReadOnly(uMsr, uValue, "Might bite.");
break;
/* Don't try anything with these guys. */
case VBCPUREPBADNESS_BOND_VILLAIN:
default:
if (pszFnName && !fTakesValue)
rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValueExtra("Villain?", uValue));
else if (pszFnName)
rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, uValue, 0, 0,
annotateValueExtra("Villain?", uValue));
else if (fReadAsZero)
rc = printMsrValueIgnoreWrites(uMsr, 0, annotateValueExtra("Villain?", uValue));
else
rc = printMsrValueIgnoreWrites(uMsr, uValue, "Villain?");
break;
}
}
return rc;
}
static int reportMsr_GenRangeFunctionEx(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, const char *pszRdWrFnName,
uint32_t uMsrBase, bool fEarlyEndOk, bool fNoIgnMask, uint64_t fSkipMask, uint32_t *pidxLoop)
{
uint32_t uMsr = paMsrs[0].uMsr;
uint32_t iRange = uMsr - uMsrBase;
Assert(cMax > iRange);
cMax -= iRange;
/* Resolve default function name. */
if (!pszRdWrFnName)
{
pszRdWrFnName = getMsrFnName(uMsr, NULL);
if (!pszRdWrFnName)
return RTMsgErrorRc(VERR_INVALID_PARAMETER, "uMsr=%#x no function name\n", uMsr);
}
/* Figure the possible register count. */
if (cMax > cMsrs)
cMax = cMsrs;
uint32_t cRegs = 1;
while ( cRegs < cMax
&& paMsrs[cRegs].uMsr == uMsr + cRegs)
cRegs++;
/* Probe the first register and check that the others exhibit
the same characteristics. */
bool fReadOnly0;
uint64_t fIgnMask0, fGpMask0;
int rc = msrProberModifyBasicTests(uMsr, fSkipMask, &fReadOnly0, &fIgnMask0, &fGpMask0);
if (RT_FAILURE(rc))
return rc;
const char *pszAnnotation = NULL;
for (uint32_t i = 1; i < cRegs; i++)
{
bool fReadOnlyN;
uint64_t fIgnMaskN, fGpMaskN;
rc = msrProberModifyBasicTests(paMsrs[i].uMsr, fSkipMask, &fReadOnlyN, &fIgnMaskN, &fGpMaskN);
if (RT_FAILURE(rc))
return rc;
if ( fReadOnlyN != fReadOnly0
|| (fIgnMaskN != fIgnMask0 && !fNoIgnMask)
|| fGpMaskN != fGpMask0)
{
if (!fEarlyEndOk)
{
vbCpuRepDebug("MSR %s (%#x) range ended unexpectedly early on %#x: ro=%d ign=%#llx/%#llx gp=%#llx/%#llx [N/0]\n",
getMsrNameHandled(uMsr), uMsr, paMsrs[i].uMsr,
fReadOnlyN, fReadOnly0, fIgnMaskN, fIgnMask0, fGpMaskN, fGpMask0);
pszAnnotation = "XXX: The range ended earlier than expected!";
}
cRegs = i;
break;
}
}
/*
* Report the range (or single MSR as it might be).
*/
*pidxLoop += cRegs - 1;
if (fNoIgnMask)
fIgnMask0 = 0;
bool fSimple = fIgnMask0 == 0
&& (fGpMask0 == 0 || (fGpMask0 == UINT64_MAX && fReadOnly0))
&& iRange == 0;
if (cRegs == 1)
return printMsrFunctionExtendedIdxVal(uMsr, pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName,
iRange, fIgnMask0, fGpMask0,
pszAnnotation ? pszAnnotation : annotateValue(paMsrs[0].uValue));
if (fSimple)
return printMsrRangeFunction(uMsr, uMsr + cRegs - 1,
pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName, pszAnnotation);
return printMsrRangeFunctionExIdxVal(uMsr, uMsr + cRegs - 1, pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName,
iRange /*uValue*/, fIgnMask0, fGpMask0, pszAnnotation);
}
static int reportMsr_GenRangeFunction(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, const char *pszRdWrFnName,
uint32_t *pidxLoop)
{
return reportMsr_GenRangeFunctionEx(paMsrs, cMsrs, cMax, pszRdWrFnName, paMsrs[0].uMsr, false /*fEarlyEndOk*/, false /*fNoIgnMask*/,
getGenericSkipMask(paMsrs[0].uMsr), pidxLoop);
}
static int reportMsr_GenFunctionEx(uint32_t uMsr, const char *pszRdWrFnName, uint32_t uValue,
uint64_t fSkipMask, const char *pszAnnotate)
{
/* Resolve default function name. */
if (!pszRdWrFnName)
{
pszRdWrFnName = getMsrFnName(uMsr, NULL);
if (!pszRdWrFnName)
return RTMsgErrorRc(VERR_INVALID_PARAMETER, "uMsr=%#x no function name\n", uMsr);
}
/* Probe the register and report. */
uint64_t fIgnMask = 0;
uint64_t fGpMask = 0;
int rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
if (RT_SUCCESS(rc))
{
if (fGpMask == UINT64_MAX && uValue == 0 && !msrProberModifyZero(uMsr))
rc = printMsrFunctionReadOnly(uMsr, pszRdWrFnName, pszAnnotate);
else if (fIgnMask == UINT64_MAX && fGpMask == 0 && uValue == 0)
rc = printMsrFunctionIgnoreWrites(uMsr, pszRdWrFnName, pszAnnotate);
else if (fIgnMask != 0 && fGpMask == 0 && uValue == 0)
rc = printMsrFunctionIgnoreMask(uMsr, pszRdWrFnName, NULL, fIgnMask, pszAnnotate);
else if (fIgnMask == 0 && fGpMask == 0 && uValue == 0)
rc = printMsrFunction(uMsr, pszRdWrFnName, NULL, pszAnnotate);
else
rc = printMsrFunctionExtended(uMsr, pszRdWrFnName, NULL, uValue, fIgnMask, fGpMask, pszAnnotate);
}
return rc;
}
/**
* Special function for reporting the IA32_APIC_BASE register, as it seems to be
* causing trouble on newer systems.
*
* @returns
* @param uMsr The MSR number.
* @param uValue The value.
*/
static int reportMsr_Ia32ApicBase(uint32_t uMsr, uint64_t uValue)
{
/* Trouble with the generic treatment of both the "APIC Global Enable" and
"Enable x2APIC mode" bits on an i7-3820QM running OS X 10.8.5. */
uint64_t fSkipMask = RT_BIT_64(11);
if (vbCpuRepSupportsX2Apic())
fSkipMask |= RT_BIT_64(10);
return reportMsr_GenFunctionEx(uMsr, "Ia32ApicBase", uValue, fSkipMask, NULL);
}
/**
* Special function for reporting the IA32_MISC_ENABLE register, as it seems to
* be causing trouble on newer systems.
*
* @returns
* @param uMsr The MSR number.
* @param uValue The value.
*/
static int reportMsr_Ia32MiscEnable(uint32_t uMsr, uint64_t uValue)
{
uint64_t fSkipMask = 0;
/** @todo test & adjust on P4. */
if ( ( g_enmMicroarch >= kCpumMicroarch_Intel_NB_First
&& g_enmMicroarch <= kCpumMicroarch_Intel_NB_End)
|| ( g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Broadwell
&& g_enmMicroarch <= kCpumMicroarch_Intel_Core7_End)
|| ( g_enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
&& g_enmMicroarch <= kCpumMicroarch_Intel_Atom_End)
)
{
vbCpuRepPrintf("WARNING: IA32_MISC_ENABLE probing needs hacking on this CPU!\n");
RTThreadSleep(128);
}
/* The no execute related flag is deadly if clear. */
if ( !(uValue & MSR_IA32_MISC_ENABLE_XD_DISABLE)
&& ( g_enmMicroarch < kCpumMicroarch_Intel_First
|| g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
|| vbCpuRepSupportsNX() ) )
fSkipMask |= MSR_IA32_MISC_ENABLE_XD_DISABLE;
uint64_t fIgnMask = 0;
uint64_t fGpMask = 0;
int rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
if (RT_SUCCESS(rc))
rc = printMsrFunctionExtended(uMsr, "Ia32MiscEnable", "Ia32MiscEnable", uValue,
fIgnMask, fGpMask, annotateValue(uValue));
return rc;
}
/**
* Verifies that MTRR type field works correctly in the given MSR.
*
* @returns VBox status code (failure if bad MSR behavior).
* @param uMsr The MSR.
* @param iBit The first bit of the type field (8-bit wide).
* @param cExpected The number of types expected - PAT=8, MTRR=7.
*/
static int msrVerifyMtrrTypeGPs(uint32_t uMsr, uint32_t iBit, uint32_t cExpected)
{
uint32_t uEndTypes = 0;
while (uEndTypes < 255)
{
bool fGp = !msrProberModifySimpleGp(uMsr, ~(UINT64_C(0xff) << iBit), (uint64_t)uEndTypes << iBit);
if (!fGp && (uEndTypes == 2 || uEndTypes == 3))
return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR types %u does not cause a GP as it should. (msr %#x)\n",
uEndTypes, uMsr);
if (fGp && uEndTypes != 2 && uEndTypes != 3)
break;
uEndTypes++;
}
if (uEndTypes != cExpected)
return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR types detected to be %#x (msr %#x). Expected %#x.\n",
uEndTypes, uMsr, cExpected);
return VINF_SUCCESS;
}
/**
* Deals with the variable MTRR MSRs.
*
* @returns VBox status code.
* @param paMsrs Pointer to the first variable MTRR MSR (200h).
* @param cMsrs The number of MSRs in the array @a paMsr.
* @param pidxLoop Index variable that should be advanced to the
* last MTRR MSR entry.
*/
static int reportMsr_Ia32MtrrPhysBaseMaskN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
{
uint32_t uMsr = paMsrs[0].uMsr;
/* Count them. */
uint32_t cRegs = 1;
while ( cRegs < cMsrs
&& paMsrs[cRegs].uMsr == uMsr + cRegs)
cRegs++;
if (cRegs & 1)
return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR variable MSR range is odd: cRegs=%#x\n", cRegs);
if (cRegs > 0x20)
return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR variable MSR range is too large: cRegs=%#x\n", cRegs);
/* Find a disabled register that we can play around with. */
uint32_t iGuineaPig;
for (iGuineaPig = 0; iGuineaPig < cRegs; iGuineaPig += 2)
if (!(paMsrs[iGuineaPig + 1].uValue & RT_BIT_32(11)))
break;
if (iGuineaPig >= cRegs)
iGuineaPig = cRegs - 2;
vbCpuRepDebug("iGuineaPig=%#x -> %#x\n", iGuineaPig, uMsr + iGuineaPig);
/* Probe the base. */
uint64_t fIgnBase = 0;
uint64_t fGpBase = 0;
int rc = msrProberModifyBitChanges(uMsr + iGuineaPig, &fIgnBase, &fGpBase, 0);
if (RT_FAILURE(rc))
return rc;
rc = msrVerifyMtrrTypeGPs(uMsr + iGuineaPig, 0, 7);
if (RT_FAILURE(rc))
return rc;
vbCpuRepDebug("fIgnBase=%#llx fGpBase=%#llx\n", fIgnBase, fGpBase);
/* Probing the mask is relatively straight forward. */
uint64_t fIgnMask = 0;
uint64_t fGpMask = 0;
rc = msrProberModifyBitChanges(uMsr + iGuineaPig + 1, &fIgnMask, &fGpMask, 0);
if (RT_FAILURE(rc))
return rc;
vbCpuRepDebug("fIgnMask=%#llx fGpMask=%#llx\n", fIgnMask, fGpMask);
/* Validate that the whole range subscribes to the apprimately same GP rules. */
for (uint32_t i = 0; i < cRegs; i += 2)
{
uint64_t fSkipBase = ~fGpBase;
uint64_t fSkipMask = ~fGpMask;
if (!(paMsrs[i + 1].uValue & RT_BIT_32(11)))
fSkipBase = fSkipMask = 0;
fSkipBase |= 0x7; /* Always skip the type. */
fSkipMask |= RT_BIT_32(11); /* Always skip the enable bit. */
vbCpuRepDebug("i=%#x fSkipBase=%#llx fSkipMask=%#llx\n", i, fSkipBase, fSkipMask);
if (!(paMsrs[i + 1].uValue & RT_BIT_32(11)))
{
rc = msrVerifyMtrrTypeGPs(uMsr + iGuineaPig, 0, 7);
if (RT_FAILURE(rc))
return rc;
}
uint64_t fIgnBaseN = 0;
uint64_t fGpBaseN = 0;
rc = msrProberModifyBitChanges(uMsr + i, &fIgnBaseN, &fGpBaseN, fSkipBase);
if (RT_FAILURE(rc))
return rc;
if ( fIgnBaseN != (fIgnBase & ~fSkipBase)
|| fGpBaseN != (fGpBase & ~fSkipBase) )
return RTMsgErrorRc(VERR_INVALID_PARAMETER,
"MTRR PHYS BASE register %#x behaves differently from %#x: ign=%#llx/%#llx gp=%#llx/%#llx (fSkipBase=%#llx)\n",
uMsr + i, uMsr + iGuineaPig,
fIgnBaseN, fIgnBase & ~fSkipBase, fGpBaseN, fGpBase & ~fSkipBase, fSkipBase);
uint64_t fIgnMaskN = 0;
uint64_t fGpMaskN = 0;
rc = msrProberModifyBitChanges(uMsr + i + 1, &fIgnMaskN, &fGpMaskN, fSkipMask);
if (RT_FAILURE(rc))
return rc;
if ( fIgnMaskN != (fIgnMask & ~fSkipMask)
|| fGpMaskN != (fGpMask & ~fSkipMask) )
return RTMsgErrorRc(VERR_INVALID_PARAMETER,
"MTRR PHYS MASK register %#x behaves differently from %#x: ign=%#llx/%#llx gp=%#llx/%#llx (fSkipMask=%#llx)\n",
uMsr + i + 1, uMsr + iGuineaPig + 1,
fIgnMaskN, fIgnMask & ~fSkipMask, fGpMaskN, fGpMask & ~fSkipMask, fSkipMask);
}
/* Print the whole range. */
fGpBase &= ~(uint64_t)0x7; /* Valid type bits, see msrVerifyMtrrTypeGPs(). */
for (uint32_t i = 0; i < cRegs; i += 2)
{
printMsrFunctionExtendedIdxVal(uMsr + i, "Ia32MtrrPhysBaseN", NULL, i / 2, fIgnBase, fGpBase,
annotateValue(paMsrs[i].uValue));
printMsrFunctionExtendedIdxVal(uMsr + i + 1, "Ia32MtrrPhysMaskN", NULL, i / 2, fIgnMask, fGpMask,
annotateValue(paMsrs[i + 1].uValue));
}
*pidxLoop += cRegs - 1;
return VINF_SUCCESS;
}
/**
* Deals with fixed MTRR and PAT MSRs, checking the 8 memory type fields.
*
* @returns VBox status code.
* @param uMsr The MSR.
*/
static int reportMsr_Ia32MtrrFixedOrPat(uint32_t uMsr)
{
/* Had a spot of trouble on an old macbook pro with core2 duo T9900 (penryn)
running 64-bit win81pe. Not giving PAT such a scrutiny fixes it. */
if ( uMsr != 0x00000277
|| g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First)
{
/* Every 8 bytes is a type, check the type ranges one by one. */
for (uint32_t iBit = 0; iBit < 64; iBit += 8)
{
int rc = msrVerifyMtrrTypeGPs(uMsr, iBit, 7 + (uMsr == 0x00000277));
if (RT_FAILURE(rc))
return rc;
}
}
return printMsrFunctionCpumCpu(uMsr, NULL, NULL, NULL, NULL);
}
/**
* Deals with IA32_MTRR_DEF_TYPE.
*
* @returns VBox status code.
* @param uMsr The MSR.
*/
static int reportMsr_Ia32MtrrDefType(uint32_t uMsr)
{
int rc = msrVerifyMtrrTypeGPs(uMsr, 0, 7);
if (RT_FAILURE(rc))
return rc;
uint64_t fGpMask = 0;
uint64_t fIgnMask = 0;
rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, 0x7);
if (RT_FAILURE(rc))
return rc;
Assert(!(fGpMask & 7)); Assert(!(fIgnMask & 7));
return printMsrFunctionCpumCpuEx(uMsr, NULL, NULL, NULL, fIgnMask, fGpMask, NULL);
}
/**
* Deals with the Machine Check (MC) MSRs in the 400h+ area.
*
* @returns VBox status code.
* @param paMsrs Pointer to the first MC MSR (400h).
* @param cMsrs The number of MSRs in the array @a paMsr.
* @param pidxLoop Index variable that should be advanced to the
* last MC MSR entry.
*/
static int reportMsr_Ia32McCtlStatusAddrMiscN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
{
uint32_t uMsr = paMsrs[0].uMsr;
/* Count them. */
uint32_t cRegs = 1;
uint32_t cDetectedRegs = 1;
while ( cDetectedRegs < cMsrs
&& ( paMsrs[cDetectedRegs].uMsr == uMsr + cRegs
|| (cRegs & 3) == 2 /* ADDR may or may not be there, depends on STATUS and CPU. */
|| (cRegs & 3) == 3 /* MISC may or may not be there, depends on STATUS and CPU. */)
&& cRegs < 0x7f )
{
if (paMsrs[cDetectedRegs].uMsr == uMsr + cRegs)
cDetectedRegs++;
cRegs++;
}
if (cRegs & 3)
return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MC MSR range is odd: cRegs=%#x\n", cRegs);
/* Just report them. We don't bother probing here as the CTL format
and such seems to be a lot of work to test correctly and changes between
cpu generations. */
*pidxLoop += cDetectedRegs - 1;
return printMsrRangeFunction(uMsr, uMsr + cRegs - 1, "Ia32McCtlStatusAddrMiscN", NULL, NULL);
}
/**
* Deals with the X2APIC msrs.
*
* @returns VBox status code.
* @param paMsrs Pointer to the first X2APIC MSR.
* @param cMsrs The number of MSRs in the array @a paMsr.
* @param pidxLoop Index variable that should be advanced to the
* last X2APIC MSR entry.
*/
static int reportMsr_GenX2Apic(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
{
/* Advance. */
uint32_t cRegs = 1;
while ( cRegs < cMsrs
&& paMsrs[cRegs].uMsr <= 0x8ff)
cRegs++;
*pidxLoop += cRegs - 1;
/* Just emit an X2APIC range. */
return printMsrRangeFunction(0x800, 0x8ff, "Ia32X2ApicN", NULL, NULL);
}
/**
* Deals carefully with the EFER register.
*
* @returns VBox status code.
* @param uMsr The MSR number.
* @param uValue The current value.
*/
static int reportMsr_Amd64Efer(uint32_t uMsr, uint64_t uValue)
{
uint64_t fSkipMask = 0;
if (vbCpuRepSupportsLongMode())
fSkipMask |= MSR_K6_EFER_LME;
if ( (uValue & MSR_K6_EFER_NXE)
|| vbCpuRepSupportsNX())
fSkipMask |= MSR_K6_EFER_NXE;
return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, NULL);
}
/**
* Deals with the MC4_MISCn (n >= 1) range and the following reserved MSRs.
*
* @returns VBox status code.
* @param paMsrs Pointer to the first MSR.
* @param cMsrs The number of MSRs in the array @a paMsr.
* @param pidxLoop Index variable that should be advanced to the
* last MSR entry in the range.
*/
static int reportMsr_AmdFam10hMc4MiscN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
{
/* Count registers. */
uint32_t cRegs = 1;
while ( cRegs < cMsrs
&& cRegs < 8
&& paMsrs[cRegs].uMsr == paMsrs[0].uMsr + cRegs)
cRegs++;
/* Probe & report used MSRs. */
uint64_t fIgnMask = 0;
uint64_t fGpMask = 0;
uint32_t cUsed = 0;
while (cUsed < cRegs)
{
uint64_t fIgnMaskN = 0;
uint64_t fGpMaskN = 0;
int rc = msrProberModifyBitChanges(paMsrs[cUsed].uMsr, &fIgnMaskN, &fGpMaskN, 0);
if (RT_FAILURE(rc))
return rc;
if (fIgnMaskN == UINT64_MAX || fGpMaskN == UINT64_MAX)
break;
if (cUsed == 0)
{
fIgnMask = fIgnMaskN;
fGpMask = fGpMaskN;
}
else if ( fIgnMaskN != fIgnMask
|| fGpMaskN != fGpMask)
return RTMsgErrorRc(VERR_NOT_EQUAL, "AmdFam16hMc4MiscN mismatch: fIgn=%#llx/%#llx fGp=%#llx/%#llx uMsr=%#x\n",
fIgnMaskN, fIgnMask, fGpMaskN, fGpMask, paMsrs[cUsed].uMsr);
cUsed++;
}
if (cUsed > 0)
printMsrRangeFunctionEx(paMsrs[0].uMsr, paMsrs[cUsed - 1].uMsr, "AmdFam10hMc4MiscN", NULL, 0, fIgnMask, fGpMask, NULL);
/* Probe & report reserved MSRs. */
uint32_t cReserved = 0;
while (cUsed + cReserved < cRegs)
{
fIgnMask = fGpMask = 0;
int rc = msrProberModifyBitChanges(paMsrs[cUsed + cReserved].uMsr, &fIgnMask, &fGpMask, 0);
if (RT_FAILURE(rc))
return rc;
if ((fIgnMask != UINT64_MAX && fGpMask != UINT64_MAX) || paMsrs[cUsed + cReserved].uValue)
return RTMsgErrorRc(VERR_NOT_EQUAL,
"Unexpected reserved AmdFam16hMc4MiscN: fIgn=%#llx fGp=%#llx uMsr=%#x uValue=%#llx\n",
fIgnMask, fGpMask, paMsrs[cUsed + cReserved].uMsr, paMsrs[cUsed + cReserved].uValue);
cReserved++;
}
if (cReserved > 0 && fIgnMask == UINT64_MAX)
printMsrRangeValueIgnoreWrites(paMsrs[cUsed].uMsr, paMsrs[cUsed + cReserved - 1].uMsr, 0, NULL);
else if (cReserved > 0 && fGpMask == UINT64_MAX)
printMsrRangeValueReadOnly(paMsrs[cUsed].uMsr, paMsrs[cUsed + cReserved - 1].uMsr, 0, NULL);
*pidxLoop += cRegs - 1;
return VINF_SUCCESS;
}
/**
* Deals with the AMD PERF_CTL range.
*
* @returns VBox status code.
* @param paMsrs Pointer to the first MSR.
* @param cMsrs The number of MSRs in the array @a paMsr.
* @param pidxLoop Index variable that should be advanced to the
* last MSR entry in the range.
*/
static int reportMsr_AmdK8PerfCtlN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
{
uint32_t uMsr = paMsrs[0].uMsr;
Assert(uMsr == 0xc0010000);
/* Family 15h (bulldozer +) aliases these registers sparsely onto c001020x. */
if (CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
{
for (uint32_t i = 0; i < 4; i++)
printMsrAlias(uMsr + i, 0xc0010200 + i * 2, NULL);
*pidxLoop += 3;
}
else
return reportMsr_GenRangeFunction(paMsrs, cMsrs, 4, "AmdK8PerfCtlN", pidxLoop);
return VINF_SUCCESS;
}
/**
* Deals with the AMD PERF_CTR range.
*
* @returns VBox status code.
* @param paMsrs Pointer to the first MSR.
* @param cMsrs The number of MSRs in the array @a paMsr.
* @param pidxLoop Index variable that should be advanced to the
* last MSR entry in the range.
*/
static int reportMsr_AmdK8PerfCtrN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
{
uint32_t uMsr = paMsrs[0].uMsr;
Assert(uMsr == 0xc0010004);
/* Family 15h (bulldozer +) aliases these registers sparsely onto c001020x. */
if (CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
{
for (uint32_t i = 0; i < 4; i++)
printMsrAlias(uMsr + i, 0xc0010201 + i * 2, NULL);
*pidxLoop += 3;
}
else
return reportMsr_GenRangeFunction(paMsrs, cMsrs, 4, "AmdK8PerfCtrN", pidxLoop);
return VINF_SUCCESS;
}
/**
* Deals carefully with the SYS_CFG register.
*
* @returns VBox status code.
* @param uMsr The MSR number.
* @param uValue The current value.
*/
static int reportMsr_AmdK8SysCfg(uint32_t uMsr, uint64_t uValue)
{
uint64_t fSkipMask = 0;
/* Bit 21 (MtrrTom2En) is marked reserved in family 0fh, while in family
10h BKDG this changes (as does the document style). Testing this bit
causes bulldozer running win64 to restart, thus this special treatment. */
if (g_enmMicroarch >= kCpumMicroarch_AMD_K10)
fSkipMask |= RT_BIT(21);
/* Turns out there are more killer bits here, at least on Opteron 2384.
Skipping all known bits. */
if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_65nm /* Not sure when introduced - harmless? */)
fSkipMask |= RT_BIT(22); /* Tom2ForceMemTypeWB */
if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
fSkipMask |= RT_BIT(21); /* MtrrTom2En */
if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
fSkipMask |= RT_BIT(20); /* MtrrVarDramEn*/
if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
fSkipMask |= RT_BIT(19); /* MtrrFixDramModEn */
if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
fSkipMask |= RT_BIT(18); /* MtrrFixDramEn */
if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
fSkipMask |= RT_BIT(17); /* SysUcLockEn */
if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
fSkipMask |= RT_BIT(16); /* ChgToDirtyDis */
if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First && g_enmMicroarch < kCpumMicroarch_AMD_15h_First)
fSkipMask |= RT_BIT(10); /* SetDirtyEnO */
if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First && g_enmMicroarch < kCpumMicroarch_AMD_15h_First)
fSkipMask |= RT_BIT(9); /* SetDirtyEnS */
if ( CPUMMICROARCH_IS_AMD_FAM_8H(g_enmMicroarch)
|| CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
fSkipMask |= RT_BIT(8); /* SetDirtyEnE */
if ( CPUMMICROARCH_IS_AMD_FAM_8H(g_enmMicroarch)
|| CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
fSkipMask |= RT_BIT(7) /* SysVicLimit */
| RT_BIT(6) /* SysVicLimit */
| RT_BIT(5) /* SysVicLimit */
| RT_BIT(4) /* SysAckLimit */
| RT_BIT(3) /* SysAckLimit */
| RT_BIT(2) /* SysAckLimit */
| RT_BIT(1) /* SysAckLimit */
| RT_BIT(0) /* SysAckLimit */;
return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, annotateValue(uValue));
}
/**
* Deals carefully with the HWCR register.
*
* @returns VBox status code.
* @param uMsr The MSR number.
* @param uValue The current value.
*/
static int reportMsr_AmdK8HwCr(uint32_t uMsr, uint64_t uValue)
{
uint64_t fSkipMask = 0;
/* Trouble on Opteron 2384, skip some of the known bits. */
if (g_enmMicroarch >= kCpumMicroarch_AMD_K10 && !CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch))
fSkipMask |= /*RT_BIT(10)*/ 0 /* MonMwaitUserEn */
| RT_BIT(9); /* MonMwaitDis */
fSkipMask |= RT_BIT(8); /* #IGNNE port emulation */
if ( CPUMMICROARCH_IS_AMD_FAM_8H(g_enmMicroarch)
|| CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
fSkipMask |= RT_BIT(7) /* DisLock */
| RT_BIT(6); /* FFDis (TLB flush filter) */
fSkipMask |= RT_BIT(4); /* INVD to WBINVD */
fSkipMask |= RT_BIT(3); /* TLBCACHEDIS */
if ( CPUMMICROARCH_IS_AMD_FAM_8H(g_enmMicroarch)
|| CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch)
|| CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch) )
fSkipMask |= RT_BIT(1); /* SLOWFENCE */
fSkipMask |= RT_BIT(0); /* SMMLOCK */
return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, annotateValue(uValue));
}
/**
* Deals carefully with a IORRBasei register.
*
* @returns VBox status code.
* @param uMsr The MSR number.
* @param uValue The current value.
*/
static int reportMsr_AmdK8IorrBaseN(uint32_t uMsr, uint64_t uValue)
{
/* Skip know bits here, as harm seems to come from messing with them. */
uint64_t fSkipMask = RT_BIT(4) | RT_BIT(3);
fSkipMask |= (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & X86_PAGE_4K_BASE_MASK;
return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010016) / 2, fSkipMask, annotateValue(uValue));
}
/**
* Deals carefully with a IORRMaski register.
*
* @returns VBox status code.
* @param uMsr The MSR number.
* @param uValue The current value.
*/
static int reportMsr_AmdK8IorrMaskN(uint32_t uMsr, uint64_t uValue)
{
/* Skip know bits here, as harm seems to come from messing with them. */
uint64_t fSkipMask = RT_BIT(11);
fSkipMask |= (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & X86_PAGE_4K_BASE_MASK;
return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010017) / 2, fSkipMask, annotateValue(uValue));
}
/**
* Deals carefully with a IORRMaski register.
*
* @returns VBox status code.
* @param uMsr The MSR number.
* @param uValue The current value.
*/
static int reportMsr_AmdK8TopMemN(uint32_t uMsr, uint64_t uValue)
{
/* Skip know bits here, as harm seems to come from messing with them. */
uint64_t fSkipMask = (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(RT_BIT_64(23) - 1);
return reportMsr_GenFunctionEx(uMsr, NULL, uMsr == 0xc001001d, fSkipMask, annotateValue(uValue));
}
/**
* Deals with the AMD P-state config range.
*
* @returns VBox status code.
* @param paMsrs Pointer to the first MSR.
* @param cMsrs The number of MSRs in the array @a paMsr.
* @param pidxLoop Index variable that should be advanced to the
* last MSR entry in the range.
*/
static int reportMsr_AmdFam10hPStateN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
{
uint32_t uMsr = paMsrs[0].uMsr;
AssertRelease(uMsr == 0xc0010064);
/* Count them. */
uint32_t cRegs = 1;
while ( cRegs < 8
&& cRegs < cMsrs
&& paMsrs[cRegs].uMsr == uMsr + cRegs)
cRegs++;
/* Figure out which bits we should skip when probing. This is based on
specs and may need adjusting for real life when handy. */
uint64_t fSkipMask = RT_BIT_64(63); /* PstateEn */
fSkipMask |= RT_BIT_64(41) | RT_BIT_64(40); /* IddDiv */
fSkipMask |= UINT64_C(0x000000ff00000000); /* IddValue */
if (CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
fSkipMask |= UINT32_C(0xfe000000); /* NbVid - Northbridge VID */
if ( CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch)
|| CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
fSkipMask |= RT_BIT_32(22); /* NbDid or NbPstate. */
if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver) /* ?? - listed in 10-1Fh model BDKG as well asFam16h */
fSkipMask |= RT_BIT_32(16); /* CpuVid[7] */
fSkipMask |= UINT32_C(0x0000fe00); /* CpuVid[6:0] */
fSkipMask |= UINT32_C(0x000001c0); /* CpuDid */
fSkipMask |= UINT32_C(0x0000003f); /* CpuFid */
/* Probe and report them one by one since we're passing values instead of
register indexes to the functions. */
for (uint32_t i = 0; i < cRegs; i++)
{
uint64_t fIgnMask = 0;
uint64_t fGpMask = 0;
int rc = msrProberModifyBitChanges(uMsr + i, &fIgnMask, &fGpMask, fSkipMask);
if (RT_FAILURE(rc))
return rc;
printMsrFunctionExtended(uMsr + i, "AmdFam10hPStateN", NULL, paMsrs[i].uValue, fIgnMask, fGpMask,
annotateValue(paMsrs[i].uValue));
}
/* Advance. */
*pidxLoop += cRegs - 1;
return VINF_SUCCESS;
}
/**
* Deals carefully with a COFVID control register.
*
* @returns VBox status code.
* @param uMsr The MSR number.
* @param uValue The current value.
*/
static int reportMsr_AmdFam10hCofVidControl(uint32_t uMsr, uint64_t uValue)
{
/* Skip know bits here, as harm seems to come from messing with them. */
uint64_t fSkipMask = 0;
if (CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
fSkipMask |= UINT32_C(0xfe000000); /* NbVid - Northbridge VID */
else if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_First) /* Listed in preliminary Fam16h BDKG. */
fSkipMask |= UINT32_C(0xff000000); /* NbVid - Northbridge VID - includes bit 24 for Fam15h and Fam16h. Odd... */
if ( CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch)
|| g_enmMicroarch >= kCpumMicroarch_AMD_15h_First) /* Listed in preliminary Fam16h BDKG. */
fSkipMask |= RT_BIT_32(22); /* NbDid or NbPstate. */
if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver) /* ?? - listed in 10-1Fh model BDKG as well asFam16h */
fSkipMask |= RT_BIT_32(20); /* CpuVid[7] */
fSkipMask |= UINT32_C(0x00070000); /* PstatId */
fSkipMask |= UINT32_C(0x0000fe00); /* CpuVid[6:0] */
fSkipMask |= UINT32_C(0x000001c0); /* CpuDid */
fSkipMask |= UINT32_C(0x0000003f); /* CpuFid */
return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, annotateValue(uValue));
}
/**
* Deals with the AMD [|L2I_|NB_]PERF_CT[LR] mixed ranges.
*
* Mixed here refers to the control and counter being in mixed in pairs as
* opposed to them being two separate parallel arrays like in the 0xc0010000
* area.
*
* @returns VBox status code.
* @param paMsrs Pointer to the first MSR.
* @param cMsrs The number of MSRs in the array @a paMsr.
* @param cMax The max number of MSRs (not counters).
* @param pidxLoop Index variable that should be advanced to the
* last MSR entry in the range.
*/
static int reportMsr_AmdGenPerfMixedRange(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, uint32_t *pidxLoop)
{
uint32_t uMsr = paMsrs[0].uMsr;
/* Count them. */
uint32_t cRegs = 1;
while ( cRegs < cMax
&& cRegs < cMsrs
&& paMsrs[cRegs].uMsr == uMsr + cRegs)
cRegs++;
if (cRegs & 1)
return RTMsgErrorRc(VERR_INVALID_PARAMETER, "PERF range at %#x is odd: cRegs=%#x\n", uMsr, cRegs);
/* Report them as individual entries, using default names and such. */
for (uint32_t i = 0; i < cRegs; i++)
{
uint64_t fIgnMask = 0;
uint64_t fGpMask = 0;
int rc = msrProberModifyBitChanges(uMsr + i, &fIgnMask, &fGpMask, 0);
if (RT_FAILURE(rc))
return rc;
printMsrFunctionExtendedIdxVal(uMsr + i, NULL, NULL, i / 2, fIgnMask, fGpMask, annotateValue(paMsrs[i].uValue));
}
/* Advance. */
*pidxLoop += cRegs - 1;
return VINF_SUCCESS;
}
/**
* Deals carefully with a LS_CFG register.
*
* @returns VBox status code.
* @param uMsr The MSR number.
* @param uValue The current value.
*/
static int reportMsr_AmdK7InstrCacheCfg(uint32_t uMsr, uint64_t uValue)
{
/* Skip know bits here, as harm seems to come from messing with them. */
uint64_t fSkipMask = RT_BIT_64(9) /* DIS_SPEC_TLB_RLD */;
if (CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch))
fSkipMask |= RT_BIT_64(14); /* DIS_IND */
if (CPUMMICROARCH_IS_AMD_FAM_16H(g_enmMicroarch))
fSkipMask |= RT_BIT_64(26); /* DIS_WIDEREAD_PWR_SAVE */
if (CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
{
fSkipMask |= 0x1e; /* DisIcWayFilter */
fSkipMask |= RT_BIT_64(39); /* DisLoopPredictor */
fSkipMask |= RT_BIT_64(27); /* Unknown killer bit, possibly applicable to other microarchs. */
fSkipMask |= RT_BIT_64(28); /* Unknown killer bit, possibly applicable to other microarchs. */
}
return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, annotateValue(uValue));
}
/**
* Deals carefully with a CU_CFG register.
*
* @returns VBox status code.
* @param uMsr The MSR number.
* @param uValue The current value.
*/
static int reportMsr_AmdFam15hCombUnitCfg(uint32_t uMsr, uint64_t uValue)
{
/* Skip know bits here, as harm seems to come from messing with them. */
uint64_t fSkipMask = RT_BIT_64(23) /* L2WayLock */
| RT_BIT_64(22) /* L2FirstLockWay */
| RT_BIT_64(21) /* L2FirstLockWay */
| RT_BIT_64(20) /* L2FirstLockWay */
| RT_BIT_64(19) /* L2FirstLockWay */
| RT_BIT_64(10) /* DcacheAggressivePriority */;
fSkipMask |= RT_BIT_64(46) | RT_BIT_64(45); /* Killer field. Seen bit 46 set, 45 clear. Messing with either means reboot/BSOD. */
return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, annotateValue(uValue));
}
/**
* Deals carefully with a EX_CFG register.
*
* @returns VBox status code.
* @param uMsr The MSR number.
* @param uValue The current value.
*/
static int reportMsr_AmdFam15hExecUnitCfg(uint32_t uMsr, uint64_t uValue)
{
/* Skip know bits here, as harm seems to come from messing with them. */
uint64_t fSkipMask = RT_BIT_64(54) /* LateSbzResync */;
fSkipMask |= RT_BIT_64(35); /* Undocumented killer bit. */
return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, annotateValue(uValue));
}
static int produceMsrReport(VBCPUREPMSR *paMsrs, uint32_t cMsrs)
{
vbCpuRepDebug("produceMsrReport\n");
RTThreadSleep(500);
for (uint32_t i = 0; i < cMsrs; i++)
{
uint32_t uMsr = paMsrs[i].uMsr;
uint32_t fFlags = paMsrs[i].fFlags;
uint64_t uValue = paMsrs[i].uValue;
int rc;
#if 0
if (uMsr >= 0x10011007)
{
vbCpuRepDebug("produceMsrReport: uMsr=%#x (%s)...\n", uMsr, getMsrNameHandled(uMsr));
RTThreadSleep(1000);
}
#endif
/*
* Deal with write only regs first to avoid having to avoid them all the time.
*/
if (fFlags & VBCPUREPMSR_F_WRITE_ONLY)
{
if (uMsr == 0x00000079)
rc = printMsrWriteOnly(uMsr, NULL, NULL);
else
rc = reportMsr_Generic(uMsr, fFlags, uValue);
}
/*
* This shall be sorted by uMsr as much as possible.
*/
else if (uMsr == 0x00000000 && g_enmVendor == CPUMCPUVENDOR_AMD && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
rc = printMsrAlias(uMsr, 0x00000402, NULL);
else if (uMsr == 0x00000001 && g_enmVendor == CPUMCPUVENDOR_AMD && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
rc = printMsrAlias(uMsr, 0x00000401, NULL); /** @todo not 101% correct on Fam15h and later, 0xc0010015[McstatusWrEn] effect differs. */
else if (uMsr == 0x0000001b)
rc = reportMsr_Ia32ApicBase(uMsr, uValue);
else if (uMsr == 0x00000040 && g_enmMicroarch <= kCpumMicroarch_Intel_P6_M_Dothan)
rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchFromToN", &i);
else if (uMsr == 0x00000040)
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchToN", uMsr, false,
true, getGenericSkipMask(uMsr), &i);
else if (uMsr == 0x00000060 && g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah)
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchFromN", uMsr, false,
true, getGenericSkipMask(uMsr), &i);
else if (uMsr == 0x000000c1)
rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i,
g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? 8 : 4 /*cMax*/,
NULL, &i);
else if (uMsr == 0x00000186 && !g_fIntelNetBurst)
rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "Ia32PerfEvtSelN", &i);
else if (uMsr == 0x000001a0)
rc = reportMsr_Ia32MiscEnable(uMsr, uValue);
else if (uMsr >= 0x000001a6 && uMsr <= 0x000001a7)
rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 2 /*cMax*/, "IntelI7MsrOffCoreResponseN", &i);
else if (uMsr == 0x00000200)
rc = reportMsr_Ia32MtrrPhysBaseMaskN(&paMsrs[i], cMsrs - i, &i);
else if (uMsr >= 0x00000250 && uMsr <= 0x00000279)
rc = reportMsr_Ia32MtrrFixedOrPat(uMsr);
else if (uMsr >= 0x00000280 && uMsr <= 0x00000295)
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 22 /*cMax*/, NULL, 0x00000280, true /*fEarlyEndOk*/, false, 0, &i);
else if (uMsr == 0x000002ff)
rc = reportMsr_Ia32MtrrDefType(uMsr);
else if (uMsr >= 0x00000309 && uMsr <= 0x0000030b)
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3 /*cMax*/, NULL, 0x00000309, true /*fEarlyEndOk*/, false, 0, &i);
else if (uMsr == 0x000003f8 || uMsr == 0x000003fc || uMsr == 0x0000060a)
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 4, NULL, uMsr - 3, true, false, 0, &i);
else if (uMsr == 0x000003f9 || uMsr == 0x000003fd || uMsr == 0x0000060b)
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 6, true, false, 0, &i);
else if (uMsr == 0x000003fa || uMsr == 0x000003fe || uMsr == 0x0000060c)
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 7, true, false, 0, &i);
else if (uMsr >= 0x00000400 && uMsr <= 0x00000477)
rc = reportMsr_Ia32McCtlStatusAddrMiscN(&paMsrs[i], cMsrs - i, &i);
else if (uMsr == 0x000004c1)
rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8, NULL, &i);
else if (uMsr == 0x00000680 || uMsr == 0x000006c0)
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 16, NULL, uMsr, false, false, UINT64_C(0xffff800000000000), &i);
else if (uMsr >= 0x00000800 && uMsr <= 0x000008ff)
rc = reportMsr_GenX2Apic(&paMsrs[i], cMsrs - i, &i);
else if (uMsr == 0x00002000 && g_enmVendor == CPUMCPUVENDOR_INTEL)
rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 0, X86_CR0_PE | X86_CR0_PG,
annotateIfMissingBits(uValue, X86_CR0_PE | X86_CR0_PE | X86_CR0_ET));
else if (uMsr == 0x00002002 && g_enmVendor == CPUMCPUVENDOR_INTEL)
rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 2, 0, annotateValue(uValue));
else if (uMsr == 0x00002003 && g_enmVendor == CPUMCPUVENDOR_INTEL)
{
uint64_t fCr3Mask = (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & (X86_CR3_PAE_PAGE_MASK | X86_CR3_AMD64_PAGE_MASK);
if (!vbCpuRepSupportsPae())
fCr3Mask &= X86_CR3_PAGE_MASK | X86_CR3_AMD64_PAGE_MASK;
rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 3, fCr3Mask, annotateValue(uValue));
}
else if (uMsr == 0x00002004 && g_enmVendor == CPUMCPUVENDOR_INTEL)
rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 4,
X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE | X86_CR4_SMXE,
annotateValue(uValue));
else if (uMsr == 0xc0000080)
rc = reportMsr_Amd64Efer(uMsr, uValue);
else if (uMsr == 0xc0000082 || uMsr == 0xc0000083 || uMsr == 0xc0000100 || uMsr == 0xc0000101 || uMsr == 0xc0000102)
rc = reportMsr_GenFunctionEx(uMsr, NULL, 0, UINT64_C(0xffff800000000000), annotateValue(uValue)); /* Canoncial address hack. */
else if (uMsr >= 0xc0000408 && uMsr <= 0xc000040f)
rc = reportMsr_AmdFam10hMc4MiscN(&paMsrs[i], cMsrs - i, &i);
else if (uMsr == 0xc0010000)
rc = reportMsr_AmdK8PerfCtlN(&paMsrs[i], cMsrs - i, &i);
else if (uMsr == 0xc0010004)
rc = reportMsr_AmdK8PerfCtrN(&paMsrs[i], cMsrs - i, &i);
else if (uMsr == 0xc0010010)
rc = reportMsr_AmdK8SysCfg(uMsr, uValue);
else if (uMsr == 0xc0010015)
rc = reportMsr_AmdK8HwCr(uMsr, uValue);
else if (uMsr == 0xc0010016 || uMsr == 0xc0010018)
rc = reportMsr_AmdK8IorrBaseN(uMsr, uValue);
else if (uMsr == 0xc0010017 || uMsr == 0xc0010019)
rc = reportMsr_AmdK8IorrMaskN(uMsr, uValue);
else if (uMsr == 0xc001001a || uMsr == 0xc001001d)
rc = reportMsr_AmdK8TopMemN(uMsr, uValue);
else if (uMsr == 0xc0010030)
rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 6, "AmdK8CpuNameN", &i);
else if (uMsr >= 0xc0010044 && uMsr <= 0xc001004a)
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 7, "AmdK8McCtlMaskN", 0xc0010044, true /*fEarlyEndOk*/, false, 0, &i);
else if (uMsr == 0xc0010050)
rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 4, "AmdK8SmiOnIoTrapN", &i);
else if (uMsr == 0xc0010064)
rc = reportMsr_AmdFam10hPStateN(&paMsrs[i], cMsrs - i, &i);
else if (uMsr == 0xc0010070)
rc = reportMsr_AmdFam10hCofVidControl(uMsr, uValue);
else if (uMsr == 0xc0010118 || uMsr == 0xc0010119)
rc = printMsrFunction(uMsr, NULL, NULL, annotateValue(uValue)); /* RAZ, write key. */
else if (uMsr == 0xc0010200)
rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 12, &i);
else if (uMsr == 0xc0010230)
rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 8, &i);
else if (uMsr == 0xc0010240)
rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 8, &i);
else if (uMsr == 0xc0011019 && g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver)
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3, "AmdK7DrXAddrMaskN", 0xc0011019 - 1,
false /*fEarlyEndOk*/, false /*fNoIgnMask*/, 0, &i);
else if (uMsr == 0xc0011021)
rc = reportMsr_AmdK7InstrCacheCfg(uMsr, uValue);
else if (uMsr == 0xc0011023 && CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
rc = reportMsr_AmdFam15hCombUnitCfg(uMsr, uValue);
else if (uMsr == 0xc0011027)
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 1, "AmdK7DrXAddrMaskN", 0xc0011027,
false /*fEarlyEndOk*/, false /*fNoIgnMask*/, 0, &i);
else if (uMsr == 0xc001102c && CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
rc = reportMsr_AmdFam15hExecUnitCfg(uMsr, uValue);
/* generic handling. */
else
rc = reportMsr_Generic(uMsr, fFlags, uValue);
if (RT_FAILURE(rc))
return rc;
}
return VINF_SUCCESS;
}
/**
* Custom MSR hacking & probing.
*
* Called when the '-d' option is given.
*
* @returns VBox status code.
*/
static int hackingMsrs(void)
{
#if 0
vbCpuRepDebug("\nhackingMsrs:\n"); RTStrmFlush(g_pDebugOut); RTThreadSleep(2000);
uint32_t uMsr = 0xc0000081;
vbCpuRepDebug("%#x: msrProberModifyNoChange -> %RTbool\n", uMsr, msrProberModifyNoChange(uMsr));
RTThreadSleep(3000);
vbCpuRepDebug("%#x: msrProberModifyBit 30 -> %d\n", uMsr, msrProberModifyBit(uMsr, 30));
RTThreadSleep(3000);
vbCpuRepDebug("%#x: msrProberModifyZero -> %RTbool\n", uMsr, msrProberModifyZero(uMsr));
RTThreadSleep(3000);
for (uint32_t i = 0; i < 63; i++)
{
vbCpuRepDebug("%#x: bit=%02u -> %d\n", msrProberModifyBit(uMsr, i));
RTThreadSleep(500);
}
#else
uint32_t uMsr = 0xc0010015;
uint64_t uValue = 0;
msrProberRead(uMsr, &uValue);
reportMsr_AmdK8HwCr(uMsr, uValue);
#endif
return VINF_SUCCESS;
}
static int probeMsrs(bool fHacking, const char *pszNameC, const char *pszCpuDesc,
char *pszMsrMask, size_t cbMsrMask)
{
/* Initialize the mask. */
if (pszMsrMask && cbMsrMask)
RTStrCopy(pszMsrMask, cbMsrMask, "UINT32_MAX /** @todo */");
/*
* Are MSRs supported by the CPU?
*/
if ( !ASMIsValidStdRange(ASMCpuId_EAX(0))
|| !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_MSR) )
{
vbCpuRepDebug("Skipping MSR probing, CPUID indicates there isn't any MSR support.\n");
return VINF_SUCCESS;
}
/*
* Initialize the support library and check if we can read MSRs.
*/
int rc = SUPR3Init(NULL);
if (RT_FAILURE(rc))
{
vbCpuRepDebug("warning: Unable to initialize the support library (%Rrc), skipping MSR detection.\n", rc);
return VINF_SUCCESS;
}
uint64_t uValue;
bool fGp;
rc = SUPR3MsrProberRead(MSR_IA32_TSC, NIL_RTCPUID, &uValue, &fGp);
if (RT_FAILURE(rc))
{
vbCpuRepDebug("warning: MSR probing not supported by the support driver (%Rrc), skipping MSR detection.\n", rc);
return VINF_SUCCESS;
}
vbCpuRepDebug("MSR_IA32_TSC: %#llx fGp=%RTbool\n", uValue, fGp);
rc = SUPR3MsrProberRead(0xdeadface, NIL_RTCPUID, &uValue, &fGp);
vbCpuRepDebug("0xdeadface: %#llx fGp=%RTbool rc=%Rrc\n", uValue, fGp, rc);
/*
* Initialize globals we use.
*/
uint32_t uEax, uEbx, uEcx, uEdx;
ASMCpuIdExSlow(0, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
if (!ASMIsValidStdRange(uEax))
return RTMsgErrorRc(VERR_NOT_SUPPORTED, "Invalid std CPUID range: %#x\n", uEax);
g_enmVendor = CPUMR3CpuIdDetectVendorEx(uEax, uEbx, uEcx, uEdx);
ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
g_enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(g_enmVendor,
ASMGetCpuFamily(uEax),
ASMGetCpuModel(uEax, g_enmVendor == CPUMCPUVENDOR_INTEL),
ASMGetCpuStepping(uEax));
g_fIntelNetBurst = CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch);
/*
* Do the probing.
*/
if (fHacking)
rc = hackingMsrs();
else
{
/* Determine the MSR mask. */
uint32_t fMsrMask = determineMsrAndMask();
if (fMsrMask == UINT32_MAX)
RTStrCopy(pszMsrMask, cbMsrMask, "UINT32_MAX");
else
RTStrPrintf(pszMsrMask, cbMsrMask, "UINT32_C(%#x)", fMsrMask);
/* Detect MSR. */
VBCPUREPMSR *paMsrs;
uint32_t cMsrs;
rc = findMsrs(&paMsrs, &cMsrs, fMsrMask);
if (RT_FAILURE(rc))
return rc;
/* Probe the MSRs and spit out the database table. */
vbCpuRepPrintf("\n"
"#ifndef CPUM_DB_STANDALONE\n"
"/**\n"
" * MSR ranges for %s.\n"
" */\n"
"static CPUMMSRRANGE const g_aMsrRanges_%s[] = \n{\n",
pszCpuDesc,
pszNameC);
rc = produceMsrReport(paMsrs, cMsrs);
vbCpuRepPrintf("};\n"
"#endif /* !CPUM_DB_STANDALONE */\n"
"\n"
);
RTMemFree(paMsrs);
paMsrs = NULL;
}
return rc;
}
static int produceCpuIdArray(const char *pszNameC, const char *pszCpuDesc)
{
/*
* Collect the data.
*/
PCPUMCPUIDLEAF paLeaves;
uint32_t cLeaves;
int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
if (RT_FAILURE(rc))
return RTMsgErrorRc(rc, "CPUMR3CollectCpuIdInfo failed: %Rrc\n", rc);
/*
* Dump the array.
*/
vbCpuRepPrintf("\n"
"#ifndef CPUM_DB_STANDALONE\n"
"/**\n"
" * CPUID leaves for %s.\n"
" */\n"
"static CPUMCPUIDLEAF const g_aCpuIdLeaves_%s[] = \n{\n",
pszCpuDesc,
pszNameC);
for (uint32_t i = 0; i < cLeaves; i++)
{
vbCpuRepPrintf(" { %#010x, %#010x, ", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf);
if (paLeaves[i].fSubLeafMask == UINT32_MAX)
vbCpuRepPrintf("UINT32_MAX, ");
else
vbCpuRepPrintf("%#010x, ", paLeaves[i].fSubLeafMask);
vbCpuRepPrintf("%#010x, %#010x, %#010x, %#010x, ",
paLeaves[i].uEax, paLeaves[i].uEbx, paLeaves[i].uEcx, paLeaves[i].uEdx);
if (paLeaves[i].fFlags == 0)
vbCpuRepPrintf("0 },\n");
else
{
vbCpuRepPrintf("0");
uint32_t fFlags = paLeaves[i].fFlags;
if (paLeaves[i].fFlags & CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED)
{
vbCpuRepPrintf(" | CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED");
fFlags &= ~CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED;
}
if (fFlags)
{
RTMemFree(paLeaves);
return RTMsgErrorRc(rc, "Unknown CPUID flags %#x\n", fFlags);
}
vbCpuRepPrintf(" },\n");
}
}
vbCpuRepPrintf("};\n"
"#endif /* !CPUM_DB_STANDALONE */\n"
"\n");
RTMemFree(paLeaves);
return VINF_SUCCESS;
}
static const char *cpuVendorToString(CPUMCPUVENDOR enmCpuVendor)
{
switch (enmCpuVendor)
{
case CPUMCPUVENDOR_INTEL: return "Intel";
case CPUMCPUVENDOR_AMD: return "AMD";
case CPUMCPUVENDOR_VIA: return "VIA";
case CPUMCPUVENDOR_CYRIX: return "Cyrix";
case CPUMCPUVENDOR_INVALID:
case CPUMCPUVENDOR_UNKNOWN:
case CPUMCPUVENDOR_32BIT_HACK:
break;
}
return "invalid-cpu-vendor";
}
static int produceCpuReport(void)
{
/*
* Figure the cpu vendor.
*/
if (!ASMHasCpuId())
return RTMsgErrorRc(VERR_NOT_SUPPORTED, "No CPUID support.\n");
uint32_t uEax, uEbx, uEcx, uEdx;
ASMCpuIdExSlow(0, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
if (!ASMIsValidStdRange(uEax))
return RTMsgErrorRc(VERR_NOT_SUPPORTED, "Invalid std CPUID range: %#x\n", uEax);
CPUMCPUVENDOR enmVendor = CPUMR3CpuIdDetectVendorEx(uEax, uEbx, uEcx, uEdx);
if (enmVendor == CPUMCPUVENDOR_UNKNOWN)
return RTMsgErrorRc(VERR_NOT_IMPLEMENTED, "Unknown CPU vendor: %.4s%.4s%.4s\n", &uEbx, &uEdx, &uEcx);
vbCpuRepDebug("CPU Vendor: %s - %.4s%.4s%.4s\n", CPUMR3CpuVendorName(enmVendor), &uEbx, &uEdx, &uEcx);
/*
* Determine the micro arch.
*/
ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
CPUMMICROARCH enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor,
ASMGetCpuFamily(uEax),
ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL),
ASMGetCpuStepping(uEax));
/*
* Generate a name.
*/
char szName[16*3+1];
char szNameC[16*3+1];
char szNameRaw[16*3+1];
char *pszName = szName;
char *pszCpuDesc = (char *)"";
ASMCpuIdExSlow(0x80000000, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
if (ASMIsValidExtRange(uEax) && uEax >= UINT32_C(0x80000004))
{
/* Get the raw name and strip leading spaces. */
ASMCpuIdExSlow(0x80000002, 0, 0, 0, &szNameRaw[0 + 0], &szNameRaw[4 + 0], &szNameRaw[8 + 0], &szNameRaw[12 + 0]);
ASMCpuIdExSlow(0x80000003, 0, 0, 0, &szNameRaw[0 + 16], &szNameRaw[4 + 16], &szNameRaw[8 + 16], &szNameRaw[12 + 16]);
ASMCpuIdExSlow(0x80000004, 0, 0, 0, &szNameRaw[0 + 32], &szNameRaw[4 + 32], &szNameRaw[8 + 32], &szNameRaw[12 + 32]);
szNameRaw[48] = '\0';
pszCpuDesc = RTStrStrip(szNameRaw);
vbCpuRepDebug("Name2: %s\n", pszCpuDesc);
/* Reduce the name. */
pszName = strcpy(szName, pszCpuDesc);
static const char * const s_apszSuffixes[] =
{
"CPU @",
};
for (uint32_t i = 0; i < RT_ELEMENTS(s_apszSuffixes); i++)
{
char *pszHit = strstr(pszName, s_apszSuffixes[i]);
if (pszHit)
RT_BZERO(pszHit, strlen(pszHit));
}
static const char * const s_apszWords[] =
{
"(TM)", "(tm)", "(R)", "(r)", "Processor", "CPU", "@",
};
for (uint32_t i = 0; i < RT_ELEMENTS(s_apszWords); i++)
{
const char *pszWord = s_apszWords[i];
size_t cchWord = strlen(pszWord);
char *pszHit;
while ((pszHit = strstr(pszName, pszWord)) != NULL)
memmove(pszHit, pszHit + cchWord, strlen(pszHit + cchWord) + 1);
}
RTStrStripR(pszName);
for (char *psz = pszName; *psz; psz++)
if (RT_C_IS_BLANK(*psz))
{
size_t cchBlanks = 1;
while (RT_C_IS_BLANK(psz[cchBlanks]))
cchBlanks++;
*psz = ' ';
if (cchBlanks > 1)
memmove(psz + 1, psz + cchBlanks, strlen(psz + cchBlanks) + 1);
}
pszName = RTStrStripL(pszName);
vbCpuRepDebug("Name: %s\n", pszName);
/* Make it C/C++ acceptable. */
strcpy(szNameC, pszName);
for (char *psz = szNameC; *psz; psz++)
if (!RT_C_IS_ALNUM(*psz) && *psz != '_')
*psz = '_';
vbCpuRepDebug("NameC: %s\n", szNameC);
}
else
{
ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
RTStrPrintf(szNameC, sizeof(szNameC), "%s_%u_%u_%u", cpuVendorToString(enmVendor), ASMGetCpuFamily(uEax),
ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL), ASMGetCpuStepping(uEax));
pszCpuDesc = pszName = szNameC;
vbCpuRepDebug("Name/NameC: %s\n", szNameC);
}
/*
* Print a file header, if we're not outputting to stdout (assumption being
* that stdout is used while hacking the reporter and too much output is
* unwanted).
*/
if (g_pReportOut)
{
RTTIMESPEC Now;
char szNow[64];
RTTimeSpecToString(RTTimeNow(&Now), szNow, sizeof(szNow));
char *pchDot = strchr(szNow, '.');
if (pchDot)
strcpy(pchDot, "Z");
vbCpuRepPrintf("/* $" "Id" "$ */\n"
"/** @file\n"
" * CPU database entry \"%s\".\n"
" * Generated at %s by VBoxCpuReport v%sr%s on %s.%s.\n"
" */\n"
"\n"
"/*\n"
" * Copyright (C) 2013 Oracle Corporation\n"
" *\n"
" * This file is part of VirtualBox Open Source Edition (OSE), as\n"
" * available from http://www.virtualbox.org. This file is free software;\n"
" * you can redistribute it and/or modify it under the terms of the GNU\n"
" * General Public License (GPL) as published by the Free Software\n"
" * Foundation, in version 2 as it comes in the \"COPYING\" file of the\n"
" * VirtualBox OSE distribution. VirtualBox OSE is distributed in the\n"
" * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.\n"
" */\n"
"\n"
"#ifndef VBOX_CPUDB_%s\n"
"#define VBOX_CPUDB_%s\n"
"\n",
pszName,
szNow, RTBldCfgVersion(), RTBldCfgRevisionStr(), RTBldCfgTarget(), RTBldCfgTargetArch(),
szNameC, szNameC);
}
/*
* Extract CPUID based data.
*/
int rc = produceCpuIdArray(szNameC, pszCpuDesc);
if (RT_FAILURE(rc))
return rc;
CPUMUKNOWNCPUID enmUnknownMethod;
CPUMCPUID DefUnknown;
rc = CPUMR3CpuIdDetectUnknownLeafMethod(&enmUnknownMethod, &DefUnknown);
if (RT_FAILURE(rc))
return RTMsgErrorRc(rc, "CPUMR3DetectCpuIdUnknownMethod failed: %Rrc\n", rc);
vbCpuRepDebug("enmUnknownMethod=%s\n", CPUMR3CpuIdUnknownLeafMethodName(enmUnknownMethod));
/*
* Do the MSRs, if we can.
*/
char szMsrMask[64];
probeMsrs(false /*fHacking*/, szNameC, pszCpuDesc, szMsrMask, sizeof(szMsrMask));
/*
* Emit the CPUMDBENTRY record.
*/
ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
vbCpuRepPrintf("\n"
"/**\n"
" * Database entry for %s.\n"
" */\n"
"static CPUMDBENTRY const g_Entry_%s = \n"
"{\n"
" /*.pszName = */ \"%s\",\n"
" /*.pszFullName = */ \"%s\",\n"
" /*.enmVendor = */ CPUMCPUVENDOR_%s,\n"
" /*.uFamily = */ %u,\n"
" /*.uModel = */ %u,\n"
" /*.uStepping = */ %u,\n"
" /*.enmMicroarch = */ kCpumMicroarch_%s,\n"
" /*.fFlags = */ 0,\n"
" /*.cMaxPhysAddrWidth= */ %u,\n"
" /*.paCpuIdLeaves = */ NULL_ALONE(g_aCpuIdLeaves_%s),\n"
" /*.cCpuIdLeaves = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_%s)),\n"
" /*.enmUnknownCpuId = */ CPUMUKNOWNCPUID_%s,\n"
" /*.DefUnknownCpuId = */ { %#010x, %#010x, %#010x, %#010x },\n"
" /*.fMsrMask = */ %s,\n"
" /*.cMsrRanges = */ ZERO_ALONE(RT_ELEMENTS(g_aMsrRanges_%s)),\n"
" /*.paMsrRanges = */ NULL_ALONE(g_aMsrRanges_%s),\n"
"};\n"
"\n"
"#endif /* !VBOX_DB_%s */\n"
"\n",
pszCpuDesc,
szNameC,
pszName,
pszCpuDesc,
CPUMR3CpuVendorName(enmVendor),
ASMGetCpuFamily(uEax),
ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL),
ASMGetCpuStepping(uEax),
CPUMR3MicroarchName(enmMicroarch),
vbCpuRepGetPhysAddrWidth(),
szNameC,
szNameC,
CPUMR3CpuIdUnknownLeafMethodName(enmUnknownMethod),
DefUnknown.eax,
DefUnknown.ebx,
DefUnknown.ecx,
DefUnknown.edx,
szMsrMask,
szNameC,
szNameC,
szNameC
);
return VINF_SUCCESS;
}
int main(int argc, char **argv)
{
int rc = RTR3InitExe(argc, &argv, 0 /*fFlags*/);
if (RT_FAILURE(rc))
return RTMsgInitFailure(rc);
/*
* Argument parsing?
*/
static const RTGETOPTDEF s_aOptions[] =
{
{ "--msrs-only", 'm', RTGETOPT_REQ_NOTHING },
{ "--msrs-dev", 'd', RTGETOPT_REQ_NOTHING },
{ "--output", 'o', RTGETOPT_REQ_STRING },
};
RTGETOPTSTATE State;
RTGetOptInit(&State, argc, argv, &s_aOptions[0], RT_ELEMENTS(s_aOptions), 1, RTGETOPTINIT_FLAGS_OPTS_FIRST);
enum
{
kCpuReportOp_Normal,
kCpuReportOp_MsrsOnly,
kCpuReportOp_MsrsHacking
} enmOp = kCpuReportOp_Normal;
g_pReportOut = NULL;
g_pDebugOut = g_pStdErr;
const char *pszOutput = NULL;
int iOpt;
RTGETOPTUNION ValueUnion;
while ((iOpt = RTGetOpt(&State, &ValueUnion)) != 0)
{
switch (iOpt)
{
case 'm':
enmOp = kCpuReportOp_MsrsOnly;
break;
case 'd':
enmOp = kCpuReportOp_MsrsHacking;
break;
case 'o':
pszOutput = ValueUnion.psz;
break;
case 'h':
RTPrintf("Usage: VBoxCpuReport [-m|--msrs-only] [-d|--msrs-dev] [-h|--help] [-V|--version]\n");
RTPrintf("Internal tool for gathering information to the VMM CPU database.\n");
return RTEXITCODE_SUCCESS;
case 'V':
RTPrintf("%sr%s\n", RTBldCfgVersion(), RTBldCfgRevisionStr());
return RTEXITCODE_SUCCESS;
default:
return RTGetOptPrintError(iOpt, &ValueUnion);
}
}
/*
* Do the requested job.
*/
rc = VERR_INTERNAL_ERROR;
switch (enmOp)
{
case kCpuReportOp_Normal:
/* switch output file. */
if (pszOutput)
{
if (RTFileExists(pszOutput) && !RTSymlinkExists(pszOutput))
{
char szOld[RTPATH_MAX];
rc = RTStrCopy(szOld, sizeof(szOld), pszOutput);
if (RT_SUCCESS(rc))
rc = RTStrCat(szOld, sizeof(szOld), ".old");
if (RT_SUCCESS(rc))
RTFileRename(pszOutput, szOld, RTFILEMOVE_FLAGS_REPLACE);
}
rc = RTStrmOpen(pszOutput, "w", &g_pReportOut);
if (RT_FAILURE(rc))
{
RTMsgError("Error opening '%s': %Rrc", pszOutput, rc);
break;
}
}
rc = produceCpuReport();
break;
case kCpuReportOp_MsrsOnly:
case kCpuReportOp_MsrsHacking:
rc = probeMsrs(enmOp == kCpuReportOp_MsrsHacking, NULL, NULL, NULL, 0);
break;
}
return RT_SUCCESS(rc) ? RTEXITCODE_SUCCESS : RTEXITCODE_FAILURE;
}