VBoxCpuReport.cpp revision 4f9276b4c85a4617d08094484cc1d983791bbb16
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * VBoxCpuReport - Produces the basis for a CPU DB entry.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Copyright (C) 2013 Oracle Corporation
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * available from http://www.virtualbox.org. This file is free software;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * you can redistribute it and/or modify it under the terms of the GNU
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * General Public License (GPL) as published by the Free Software
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/*******************************************************************************
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync* Header Files *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync*******************************************************************************/
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/*******************************************************************************
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync* Structures and Typedefs *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync*******************************************************************************/
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** Write only register. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsynctypedef struct VBCPUREPMSR
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /** The first MSR register number. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /** Flags (MSRREPORT_F_XXX). */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /** The value we read, unless write-only. */
5eb36887f6970e0033f63fa135f3bb8fbfd6059bvboxsync/*******************************************************************************
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync* Global Variables *
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync*******************************************************************************/
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** The CPU vendor. Used by the MSR code. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic CPUMCPUVENDOR g_enmVendor = CPUMCPUVENDOR_INVALID;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** The CPU microarchitecture. Used by the MSR code. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic CPUMMICROARCH g_enmMicroarch = kCpumMicroarch_Invalid;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** Set if g_enmMicroarch indicates an Intel NetBurst CPU. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool g_fIntelNetBurst = false;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** The report stream. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** The debug stream. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Output to report file, if requested. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Always print a copy of the report to standard out. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic int vbCpuRepMsrsAddOne(VBCPUREPMSR **ppaMsrs, uint32_t *pcMsrs,
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Grow the array?
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync void *pvNew = RTMemRealloc(*ppaMsrs, (cMsrs + 64) * sizeof(**ppaMsrs));
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Returns the max physical address width as a number of bits.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @returns Bit count.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync else if (ASMIsValidExtRange(cMaxExt)&& cMaxExt >= 0x80000008)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PSE36))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool vbCpuRepSupportsPae(void)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool vbCpuRepSupportsLongMode(void)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool vbCpuRepSupportsNX(void)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool vbCpuRepSupportsX2Apic(void)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && (ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_X2APIC);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool msrProberWrite(uint32_t uMsr, uint64_t uValue)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync int rc = SUPR3MsrProberWrite(uMsr, NIL_RTCPUID, uValue, &fGp);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool msrProberRead(uint32_t uMsr, uint64_t *puValue)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync int rc = SUPR3MsrProberRead(uMsr, NIL_RTCPUID, puValue, &fGp);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** Tries to modify the register by writing the original value to it. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, UINT64_MAX, 0, &Result);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync/** Tries to modify the register by writing zero to it. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, 0, 0, &Result);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Tries to modify each bit in the MSR and see if we can make it change.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @returns VBox status code.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param uMsr The MSR.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param pfIgnMask The ignore mask to update.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param pfGpMask The GP mask to update.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param fSkipMask Mask of bits to skip.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic int msrProberModifyBitChanges(uint32_t uMsr, uint64_t *pfIgnMask, uint64_t *pfGpMask, uint64_t fSkipMask)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Set it. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, fBitMask, &ResultSet);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RTMsgErrorRc(rc, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, fBitMask, rc);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Clear it. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, 0, &ResultClear);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RTMsgErrorRc(rc, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, 0, rc);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync else if ( ( ((ResultSet.uBefore ^ ResultSet.uAfter) & fBitMask) == 0
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && ( ((ResultClear.uBefore ^ ResultClear.uAfter) & fBitMask) == 0
78df65edff21c11c537f38e736707ea434ab5623vboxsync * Tries to modify one bit.
78df65edff21c11c537f38e736707ea434ab5623vboxsync * @retval -2 on API error.
78df65edff21c11c537f38e736707ea434ab5623vboxsync * @retval -1 on \#GP.
78df65edff21c11c537f38e736707ea434ab5623vboxsync * @retval 0 if ignored.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @retval 1 if it changed.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param uMsr The MSR.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param iBit The bit to try modify.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic int msrProberModifyBit(uint32_t uMsr, unsigned iBit)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Set it. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, fBitMask, &ResultSet);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RTMsgErrorRc(-2, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, fBitMask, rc);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Clear it. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, 0, &ResultClear);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RTMsgErrorRc(-2, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, 0, rc);
78df65edff21c11c537f38e736707ea434ab5623vboxsync if ( ( ((ResultSet.uBefore ^ ResultSet.uAfter) & fBitMask) != 0
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync || ( ((ResultClear.uBefore ^ ResultClear.uAfter) & fBitMask) != 0
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Tries to do a simple AND+OR change and see if we \#GP or not.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @retval @c true if successfully modified.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @retval @c false if \#GP or other error.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param uMsr The MSR.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param fAndMask The AND mask.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param fOrMask The OR mask.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic bool msrProberModifySimpleGp(uint32_t uMsr, uint64_t fAndMask, uint64_t fOrMask)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, fAndMask, fOrMask, &Result);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTMsgError("SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, fAndMask, fOrMask, rc);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return false;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Combination of the basic tests.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @returns VBox status code.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param uMsr The MSR.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param fSkipMask Mask of bits to skip.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param pfReadOnly Where to return read-only status.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param pfIgnMask Where to return the write ignore mask. Need not
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * be initialized.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param pfGpMask Where to return the write GP mask. Need not
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * be initialized.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic int msrProberModifyBasicTests(uint32_t uMsr, uint64_t fSkipMask, bool *pfReadOnly, uint64_t *pfIgnMask, uint64_t *pfGpMask)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return msrProberModifyBitChanges(uMsr, pfIgnMask, pfGpMask, fSkipMask);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Determines for the MSR AND mask.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Older CPUs doesn't necessiarly implement all bits of the MSR register number.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * So, we have to approximate how many are used so we don't get an overly large
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * and confusing set of MSRs when probing.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @returns The mask.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync static uint32_t const s_aMsrs[VBCPUREP_MASK_TEST_MSRS] =
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Try a bunch of mostly read only registers: */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync MSR_P5_MC_TYPE, MSR_IA32_PLATFORM_ID, MSR_IA32_MTRR_CAP, MSR_IA32_MCG_CAP, MSR_IA32_CR_PAT,
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Then some which aren't supposed to be present on any CPU: */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Get the base values. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync for (unsigned i = 0; i < RT_ELEMENTS(s_aMsrs); i++)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //vbCpuRepDebug("Base: %#x -> %#llx\n", s_aMsrs[i], auBaseValues[i]);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Do the probing. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync for (unsigned iTest = 0; iTest <= 64 && fMsrOrMask < UINT32_MAX; iTest++)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync for (unsigned i = 0; i < RT_ELEMENTS(s_aMsrs); i++)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (!msrProberRead(s_aMsrs[i] | fMsrOrMask, &uValue))
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync uint32_t fMsrMask = iBit >= 31 ? UINT32_MAX : RT_BIT_32(iBit + 1) - 1;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync vbCpuRepDebug("MSR AND mask: quit on iBit=%u uMsr=%#x (%#x) %llx != %llx => fMsrMask=%#x\n",
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync iBit, s_aMsrs[i] | (uint32_t)fMsrOrMask, s_aMsrs[i], uValue, auBaseValues[i], fMsrMask);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Advance. */
090c459b9e90ca46e2ce2b8c81533ade3b23f3e9vboxsync vbCpuRepDebug("MSR AND mask: less that %u bits that matters?!? => fMsrMask=%#x\n", iBit + 1, fMsrMask);
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsyncstatic int findMsrs(VBCPUREPMSR **ppaMsrs, uint32_t *pcMsrs, uint32_t fMsrMask)
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync * Gather them.
7fee49908ea4b9f6cb4f9cc745633c4969ed6318vboxsync static struct { uint32_t uFirst, cMsrs; } const s_aRanges[] =
090c459b9e90ca46e2ce2b8c81533ade3b23f3e9vboxsync { 0xc0000000, 0x00022000 }, /* Had some trouble here on solaris with the tstVMM setup. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync for (unsigned i = 0; i < RT_ELEMENTS(s_aRanges); i++)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Skip 0xc0011012..13 as it seems to be bad for our health (Phenom II X6 1100T). */
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync if ((uMsr >= 0xc0011012 && uMsr <= 0xc0011013) && g_enmVendor == CPUMCPUVENDOR_AMD)
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync /* Read probing normally does it. */
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync bool fGp = true;
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync int rc = SUPR3MsrProberRead(uMsr, NIL_RTCPUID, &uValue, &fGp);
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync return RTMsgErrorRc(rc, "SUPR3MsrProberRead failed on %#x: %Rrc\n", uMsr, rc);
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync /* Is it a write only register? */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync rc = SUPR3MsrProberWrite(uMsr, NIL_RTCPUID, 0, &fGp);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RTMsgErrorRc(rc, "SUPR3MsrProberWrite failed on %#x: %Rrc\n", uMsr, rc);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Tweaks. On Intel CPUs we've got trouble detecting
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * IA32_BIOS_UPDT_TRIG (0x00000079), so we have to add it manually here.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && g_enmMicroarch >= kCpumMicroarch_Intel_P6_Core_Atom_First
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* Add it. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync rc = vbCpuRepMsrsAddOne(ppaMsrs, pcMsrs, uMsr, uValue, fFlags);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return RTMsgErrorRc(rc, "Out of memory (uMsr=%#x).\n", uMsr);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync vbCpuRepDebug("%#010x: uValue=%#llx fFlags=%#x\n", uMsr, uValue, fFlags);
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Get the name of the specified MSR, if we know it and can handle it.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Do _NOT_ add any new names here without ALSO at the SAME TIME making sure it
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * is handled correctly by the PROBING CODE and REPORTED correctly!!
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @returns Pointer to name if handled, NULL if not yet explored.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param uMsr The MSR in question.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /** @todo figure out where NCU_EVENT_CORE_MASK might be... */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000006:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (g_enmMicroarch >= kCpumMicroarch_Intel_First && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_First)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return NULL; /* TR4 / cache tag on Pentium, but that's for later. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "IA32_MONITOR_FILTER_LINE_SIZE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x0000000e: return "P?_TR12"; /* K6-III docs */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000018: return "P6_UNK_0000_0018"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000021: return "C2_UNK_0000_0021"; /* Core2_Penryn */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000002e: return "I7_UNK_0000_002e"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000002f: return "P6_UNK_0000_002f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000032: return "P6_UNK_0000_0032"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000034: return "P6_UNK_0000_0034"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000035: return "P6_UNK_0000_0035"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000036: return "I7_UNK_0000_0036"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000039: return "C2_UNK_0000_0039"; /* Core2_Penryn */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000003b: return "P6_UNK_0000_003b"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000003e: return "I7_UNK_0000_003e"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000003f: return "P6_UNK_0000_003f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000040: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_0_FROM_IP" : "MSR_LASTBRANCH_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000041: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_1_FROM_IP" : "MSR_LASTBRANCH_1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000042: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_2_FROM_IP" : "MSR_LASTBRANCH_2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000043: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_3_FROM_IP" : "MSR_LASTBRANCH_3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000044: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_4_FROM_IP" : "MSR_LASTBRANCH_4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000045: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_5_FROM_IP" : "MSR_LASTBRANCH_5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000046: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_6_FROM_IP" : "MSR_LASTBRANCH_6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000047: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_7_FROM_IP" : "MSR_LASTBRANCH_7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000004a: return "P6_UNK_0000_004a"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000004b: return "P6_UNK_0000_004b"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000004c: return "P6_UNK_0000_004c"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000004d: return "P6_UNK_0000_004d"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000004e: return "P6_UNK_0000_004e"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000004f: return "P6_UNK_0000_004f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000050: return "P6_UNK_0000_0050"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000051: return "P6_UNK_0000_0051"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000052: return "P6_UNK_0000_0052"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000053: return "P6_UNK_0000_0053"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000054: return "P6_UNK_0000_0054"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000060: return "MSR_LASTBRANCH_0_TO_IP"; /* Core2_Penryn */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000061: return "MSR_LASTBRANCH_1_TO_IP"; /* Core2_Penryn */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000062: return "MSR_LASTBRANCH_2_TO_IP"; /* Core2_Penryn */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000063: return "MSR_LASTBRANCH_3_TO_IP"; /* Core2_Penryn */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000064: return "MSR_LASTBRANCH_4_TO_IP"; /* Atom? */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000006c: return "P6_UNK_0000_006c"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000006d: return "P6_UNK_0000_006d"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000006e: return "P6_UNK_0000_006e"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000006f: return "P6_UNK_0000_006f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000008c: return "P6_UNK_0000_008c"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000008d: return "P6_UNK_0000_008d"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000008e: return "P6_UNK_0000_008e"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000008f: return "P6_UNK_0000_008f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000090: return "P6_UNK_0000_0090"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ae: return "P6_UNK_0000_00ae"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* PMC4+ first seen on SandyBridge. The earlier cut off is just to be
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync on the safe side as we must avoid P6_M_Dothan and possibly others. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c5: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC4" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c6: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC5" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c7: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC6" : "P6_UNK_0000_00c7"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC7" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000cd: return "P6_UNK_0000_00cd"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ce: return "P6_UNK_0000_00ce"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000cf: return "C2_UNK_0000_00cf"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e0: return "C2_UNK_0000_00e0"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e1: return "C2_UNK_0000_00e1"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e2: return "MSR_PKG_CST_CONFIG_CONTROL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e3: return "C2_SMM_CST_MISC_INFO"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e5: return "C2_UNK_0000_00e5"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ee: return "C1_EXT_CONFIG"; /* Core2_Penryn. msrtool lists it for Core1 as well. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000102: return "I7_IB_UNK_0000_0102"; /* IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000103: return "I7_IB_UNK_0000_0103"; /* IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000104: return "I7_IB_UNK_0000_0104"; /* IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000011b: return "P6_UNK_0000_011b"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000011c: return "C2_UNK_0000_011c"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000130: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000131: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync ? "CPUID80000001_FEATURE_MASK" : "P6_UNK_0000_0131" /* P6_M_Dothan. */;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000132: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000133: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000134: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000013c: return "I7_SB_AES_NI_CTL"; /* SandyBridge. Bit 0 is lock bit, bit 1 disables AES-NI. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000140: return "I7_IB_UNK_0000_0140"; /* IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000142: return "I7_IB_UNK_0000_0142"; /* IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000014e: return "P6_UNK_0000_014e"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000014f: return "P6_UNK_0000_014f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000150: return "P6_UNK_0000_0150"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000151: return "P6_UNK_0000_0151"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000154: return "P6_UNK_0000_0154"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000015b: return "P6_UNK_0000_015b"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000015e: return "C2_UNK_0000_015e"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000015f: return "C1_DTS_CAL_CTRL"; /* Core2_Penryn. msrtool only docs this for core1! */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000017f: return "I7_SB_ERROR_CONTROL"; /* SandyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000180: return g_fIntelNetBurst ? "MSR_MCG_RAX" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000181: return g_fIntelNetBurst ? "MSR_MCG_RBX" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000182: return g_fIntelNetBurst ? "MSR_MCG_RCX" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000183: return g_fIntelNetBurst ? "MSR_MCG_RDX" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000184: return g_fIntelNetBurst ? "MSR_MCG_RSI" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000185: return g_fIntelNetBurst ? "MSR_MCG_RDI" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000186: return g_fIntelNetBurst ? "MSR_MCG_RBP" : "IA32_PERFEVTSEL0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000187: return g_fIntelNetBurst ? "MSR_MCG_RSP" : "IA32_PERFEVTSEL1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000188: return g_fIntelNetBurst ? "MSR_MCG_RFLAGS" : "IA32_PERFEVTSEL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000189: return g_fIntelNetBurst ? "MSR_MCG_RIP" : "IA32_PERFEVTSEL3";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000018a: return g_fIntelNetBurst ? "MSR_MCG_MISC" : "IA32_PERFEVTSEL4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000018b: return g_fIntelNetBurst ? "MSR_MCG_RESERVED1" : "IA32_PERFEVTSEL5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000018c: return g_fIntelNetBurst ? "MSR_MCG_RESERVED2" : "IA32_PERFEVTSEL6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000018d: return g_fIntelNetBurst ? "MSR_MCG_RESERVED3" : "IA32_PERFEVTSEL7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000018e: return g_fIntelNetBurst ? "MSR_MCG_RESERVED4" : "IA32_PERFEVTSEL8";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000018f: return g_fIntelNetBurst ? "MSR_MCG_RESERVED5" : "IA32_PERFEVTSEL9";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000190: return g_fIntelNetBurst ? "MSR_MCG_R8" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000191: return g_fIntelNetBurst ? "MSR_MCG_R9" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000192: return g_fIntelNetBurst ? "MSR_MCG_R10" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000193: return g_fIntelNetBurst ? "MSR_MCG_R11" : "C2_UNK_0000_0193";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000194: return g_fIntelNetBurst ? "MSR_MCG_R12" : "CLOCK_FLEX_MAX";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000195: return g_fIntelNetBurst ? "MSR_MCG_R13" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000196: return g_fIntelNetBurst ? "MSR_MCG_R14" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000197: return g_fIntelNetBurst ? "MSR_MCG_R15" : NULL;
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x0000019e: return "P6_UNK_0000_019e"; /* P6_M_Dothan. */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x0000019f: return "P6_UNK_0000_019f"; /* P6_M_Dothan. */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001a1: return "P6_UNK_0000_01a1"; /* P6_M_Dothan. */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001a2: return "I7_MSR_TEMPERATURE_TARGET"; /* SandyBridge, IvyBridge. */
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0x000001a4: return "I7_UNK_0000_01a4"; /* SandyBridge, IvyBridge. */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001a8: return "I7_UNK_0000_01a8"; /* SandyBridge, IvyBridge. */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001aa: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "MSR_MISC_PWR_MGMT" : "P6_PIC_SENS_CFG" /* Pentium M. */;
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001ad: return "I7_MSR_TURBO_RATIO_LIMIT"; /* SandyBridge+, Silvermount+ */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001ae: return "P6_UNK_0000_01ae"; /* P6_M_Dothan. */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001af: return "P6_UNK_0000_01af"; /* P6_M_Dothan. */
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001b1: return "IA32_PACKAGE_THERM_STATUS";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x000001b2: return "IA32_PACKAGE_THERM_INTERRUPT";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001bf: return "C2_UNK_0000_01bf"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001c6: return "I7_UNK_0000_01c6"; /* SandyBridge*/
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Nehalem ? "MSR_LBR_SELECT" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001c9: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_End
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync ? "MSR_LASTBRANCH_TOS" : NULL /* Pentium M Dothan seems to have something else here. */;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001d3: return "P6_UNK_0000_01d3"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001db: return "P6_LAST_BRANCH_FROM_IP"; /* Not exclusive to P6, also AMD. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000001f0: return "I7_VLW_CAPABILITY"; /* SandyBridge. Bit 1 is A20M and was implemented incorrectly (AAJ49). */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x00000296: return "IA32_MC22_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x00000297: return "IA32_MC23_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x00000298: return "IA32_MC24_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x00000299: return "IA32_MC25_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x0000029a: return "IA32_MC26_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x0000029b: return "IA32_MC27_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x0000029c: return "IA32_MC28_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x0000029d: return "IA32_MC29_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x0000029e: return "IA32_MC30_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x0000029f: return "IA32_MC31_CTL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000002e0: return "I7_SB_NO_EVICT_MODE"; /* (Bits 1 & 0 are said to have something to do with no-evict cache mode used during early boot.) */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000002e6: return "I7_IB_UNK_0000_02e6"; /* IvyBridge */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000002e7: return "I7_IB_UNK_0000_02e7"; /* IvyBridge */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000300: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_BPU_COUNTER0" : "I7_SB_UNK_0000_0300" /* SandyBridge */;
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0x00000305: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_MS_COUNTER1" : "I7_SB_UNK_0000_0305" /* SandyBridge, IvyBridge */;
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0x00000309: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_FLAME_COUNTER1" : "IA32_FIXED_CTR0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000030a: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_FLAME_COUNTER2" : "IA32_FIXED_CTR1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000030b: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? "P4_MSR_FLAME_COUNTER3" : "IA32_FIXED_CTR2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000390: return "IA32_PERF_GLOBAL_OVF_CTRL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000391: return "I7_UNC_PERF_GLOBAL_CTRL"; /* S,H,X */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000392: return "I7_UNC_PERF_GLOBAL_STATUS"; /* S,H,X */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000393: return "I7_UNC_PERF_GLOBAL_OVF_CTRL"; /* X. ASSUMING this is the same on sandybridge and later. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000394: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PERF_FIXED_CTR" /* X */ : "I7_UNC_PERF_FIXED_CTR_CTRL"; /* >= S,H */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000395: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PERF_FIXED_CTR_CTRL" /* X*/ : "I7_UNC_PERF_FIXED_CTR"; /* >= S,H */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_ADDR_OPCODE_MATCH" /* X */ : "I7_UNC_CBO_CONFIG"; /* >= S,H */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000397: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_IvyBridge ? NULL : "I7_IB_UNK_0000_0397";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003b0: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC0" /* X */ : "I7_UNC_ARB_PERF_CTR0"; /* >= S,H */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003b1: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC1" /* X */ : "I7_UNC_ARB_PERF_CTR1"; /* >= S,H */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003b2: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC2" /* X */ : "I7_UNC_ARB_PERF_EVT_SEL0"; /* >= S,H */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003b3: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC3" /* X */ : "I7_UNC_ARB_PERF_EVT_SEL1"; /* >= S,H */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fc: return "I7_MSR_CORE_C3_RESIDENCY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fd: return "I7_MSR_CORE_C6_RESIDENCY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fe: return "I7_MSR_CORE_C7_RESIDENCY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000478: return g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "CPUID1_FEATURE_MASK" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000048b: return "IA32_VMX_PROCBASED_CTLS2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000048d: return "IA32_VMX_TRUE_PINBASED_CTLS";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0x0000048e: return "IA32_VMX_TRUE_PROCBASED_CTLS";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0x00000490: return "IA32_VMX_TRUE_ENTRY_CTLS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004f8: return "C2_UNK_0000_04f8"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004f9: return "C2_UNK_0000_04f9"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004fa: return "C2_UNK_0000_04fa"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004fb: return "C2_UNK_0000_04fb"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004fc: return "C2_UNK_0000_04fc"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004fd: return "C2_UNK_0000_04fd"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004fe: return "C2_UNK_0000_04fe"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000004ff: return "C2_UNK_0000_04ff"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000590: return "C2_UNK_0000_0590"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000591: return "C2_UNK_0000_0591"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000005a0: return "C2_PECI_CTL"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000005a1: return "C2_UNK_0000_05a1"; /* Core2_Penryn. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000601: return "I7_SB_MSR_VR_CURRENT_CONFIG"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000603: return "I7_SB_MSR_VR_MISC_CONFIG"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000606: return "I7_SB_MSR_RAPL_POWER_UNIT"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000060a: return "I7_SB_MSR_PKGC3_IRTL"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000060b: return "I7_SB_MSR_PKGC6_IRTL"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000060c: return "I7_SB_MSR_PKGC7_IRTL"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000060d: return "I7_SB_MSR_PKG_C2_RESIDENCY"; /* SandyBridge, IvyBridge. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000610: return "I7_SB_MSR_PKG_POWER_LIMIT";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000611: return "I7_SB_MSR_PKG_ENERGY_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000613: return "I7_SB_MSR_PKG_PERF_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000614: return "I7_SB_MSR_PKG_POWER_INFO";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000618: return "I7_SB_MSR_DRAM_POWER_LIMIT";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000619: return "I7_SB_MSR_DRAM_ENERGY_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000061b: return "I7_SB_MSR_DRAM_PERF_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000061c: return "I7_SB_MSR_DRAM_POWER_INFO";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000638: return "I7_SB_MSR_PP0_POWER_LIMIT";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000639: return "I7_SB_MSR_PP0_ENERGY_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000063b: return "I7_SB_MSR_PP0_PERF_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000640: return "I7_HW_MSR_PP0_POWER_LIMIT";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000641: return "I7_HW_MSR_PP0_ENERGY_STATUS";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000648: return "I7_IB_MSR_CONFIG_TDP_NOMINAL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000649: return "I7_IB_MSR_CONFIG_TDP_LEVEL1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000064a: return "I7_IB_MSR_CONFIG_TDP_LEVEL2";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000064b: return "I7_IB_MSR_CONFIG_TDP_CONTROL";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000064c: return "I7_IB_MSR_TURBO_ACTIVATION_RATIO";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000680: return "MSR_LASTBRANCH_0_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000681: return "MSR_LASTBRANCH_1_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000682: return "MSR_LASTBRANCH_2_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000683: return "MSR_LASTBRANCH_3_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000684: return "MSR_LASTBRANCH_4_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000685: return "MSR_LASTBRANCH_5_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000686: return "MSR_LASTBRANCH_6_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000687: return "MSR_LASTBRANCH_7_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000688: return "MSR_LASTBRANCH_8_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000689: return "MSR_LASTBRANCH_9_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000068a: return "MSR_LASTBRANCH_10_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000068b: return "MSR_LASTBRANCH_11_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000068c: return "MSR_LASTBRANCH_12_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000068d: return "MSR_LASTBRANCH_13_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000068e: return "MSR_LASTBRANCH_14_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000068f: return "MSR_LASTBRANCH_15_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c80: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "IA32_DEBUG_INTERFACE" : NULL; /* Mentioned in an intel dataskit called 4th-gen-core-family-desktop-vol-1-datasheet.pdf. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c81: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c81" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c82: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c82" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c83: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c83" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync /* 0x1000..0x1004 seems to have been used by IBM 386 and 486 clones too. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000103f: return "P6_UNK_0000_103f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000010cd: return "P6_UNK_0000_10cd"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000203f: return "P6_UNK_0000_203f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000020cd: return "P6_UNK_0000_20cd"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000303f: return "P6_UNK_0000_303f"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000030cd: return "P6_UNK_0000_30cd"; /* P6_M_Dothan. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000105: return "AMD_15H_LWP_CFG"; /* Only Family 15h? */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0000106: return "AMD_15H_LWP_CBADDR"; /* Only Family 15h? */
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010043: return "AMD_K8_THERMTRIP_STATUS"; /* BDKG says it was removed in K8 revision C.*/
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync //case 0xc001004b: return "AMD_K8_MC_CTL_MASK_7";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0xc0010054: return "AMD_K8_SMI_ON_IO_TRAP_CTL_STS";
04b02ffb8824a60fd37777bc1f7d2f35104a274cvboxsync case 0xc0010056: return "AMD_K8_SMI_TRIGGER_IO_CYCLE";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010058: return "AMD_10H_MMIO_CFG_BASE_ADDR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0010059: return "AMD_10H_TRAP_CTL?"; /* Undocumented, only one google hit. */
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010060: return "AMD_K8_BIST_RESULT"; /* BDKG says it as introduced with revision F. */
be9960565d2df0031f0e6c8a4610f5f0ae8c1845vboxsync case 0xc0010073: return "AMD_10H_C_ST_IO_BASE_ADDR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync // case 0xc0010075: return "AMD_15H_APML_TDP_LIM";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync // case 0xc0010077: return "AMD_15H_CPU_PWR_IN_TDP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync // case 0xc0010078: return "AMD_15H_PWR_AVG_PERIOD";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync // case 0xc0010079: return "AMD_15H_DRAM_CTR_CMD_THR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync // case 0xc0010080: return "AMD_16H_FSFM_ACT_CNT_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync // case 0xc0010081: return "AMD_16H_FSFM_REF_CNT_0";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001020c: return "AMD_K8_PERF_CTL_6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001020e: return "AMD_K8_PERF_CTL_7";
78df65edff21c11c537f38e736707ea434ab5623vboxsync //case 0xc001020d: return "AMD_K8_PERF_CTR_6";
78df65edff21c11c537f38e736707ea434ab5623vboxsync //case 0xc001020f: return "AMD_K8_PERF_CTR_7";
78df65edff21c11c537f38e736707ea434ab5623vboxsync //case 0xc0010238: return "AMD_16H_L2I_PERF_CTL_4";
78df65edff21c11c537f38e736707ea434ab5623vboxsync //case 0xc001023a: return "AMD_16H_L2I_PERF_CTL_5";
78df65edff21c11c537f38e736707ea434ab5623vboxsync //case 0xc001030c: return "AMD_16H_L2I_PERF_CTL_6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001023e: return "AMD_16H_L2I_PERF_CTL_7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc0010239: return "AMD_16H_L2I_PERF_CTR_4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001023b: return "AMD_16H_L2I_PERF_CTR_5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001023d: return "AMD_16H_L2I_PERF_CTR_6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001023f: return "AMD_16H_L2I_PERF_CTR_7";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc0010248: return "AMD_15H_NB_PERF_CTL_4";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001024a: return "AMD_15H_NB_PERF_CTL_5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001024c: return "AMD_15H_NB_PERF_CTL_6";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0xc001024e: return "AMD_15H_NB_PERF_CTL_7";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync //case 0xc0010249: return "AMD_15H_NB_PERF_CTR_4";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync //case 0xc001024b: return "AMD_15H_NB_PERF_CTR_5";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync //case 0xc001024d: return "AMD_15H_NB_PERF_CTR_6";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync //case 0xc001024f: return "AMD_15H_NB_PERF_CTR_7";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011001: return "AMD_K7_APIC_CLUSTER_ID"; /* Mentioned in BKDG (r3.00) for fam16h when describing EBL_CR_POWERON. */
0fc8a97f9a19a44f1ad4670454edf26d80c42281vboxsync case 0xc0011002: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD07" : NULL;
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011003: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD06" : NULL;
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011004: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD01" : NULL;
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011005: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_EXT01" : NULL;
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc001100b: return "AMD_K7_FAST_FLUSH_COUNT?";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001100d: return "AMD_K8_LOGICAL_CPUS_NUM?";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc0011014: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_RIP?" : "AMD_K7_MOBIL_DEBUG?";
2506c2bcd77fcc75b5640fa0f6a55fb5ab48ff80vboxsync case 0xc0011015: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_RIP_MASK?" : NULL;
2506c2bcd77fcc75b5640fa0f6a55fb5ab48ff80vboxsync case 0xc0011016: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_COND_HDT_VAL?" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011017: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_COND_HDT_VAL_MASK?" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011018: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_CTL?" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011019: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR1_ADDR_MASK" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001101a: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR2_ADDR_MASK" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001101b: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR3_ADDR_MASK" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001101d: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_NB_BIST?" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001101e: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_THERMTRIP_2?" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001101f: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_NB_CFG?" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011023: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG" : "AMD_K7_BU_CFG";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011028: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AMD_15H_FP_CFG"
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) ? "AMD_10H_UNK_c001_1028"
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011029: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AMD_15H_DC_CFG"
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) ? "AMD_10H_UNK_c001_1029"
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001102a: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG2"
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) || g_enmMicroarch > kCpumMicroarch_AMD_15h_End
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001102b: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG3" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc001102c: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_EX_CFG" : NULL;
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0xc001102d: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_LS_CFG2" : NULL;
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011031: return "AMD_10H_IBS_FETCH_LIN_ADDR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011032: return "AMD_10H_IBS_FETCH_PHYS_ADDR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011039: return "AMD_10H_IBS_DC_PHYS_ADDR";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0xc0011070: return "AMD_15H_UNK_c001_1070"; /* coreboot defines this, but with a numerical name. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Bunch of unknown sandy bridge registers. They might seem like the
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * nehalem based xeon stuff, but the layout doesn't match. I bet it's the
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync * same kind of registes though (i.e. uncore (UNC)).
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Kudos to Intel for keeping these a secret! Many thanks guys!!
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_SandyBridge)
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0x00000a00: return "I7_SB_UNK_0000_0a00"; case 0x00000a01: return "I7_SB_UNK_0000_0a01";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000c00: return "I7_SB_UNK_0000_0c00"; case 0x00000c01: return "I7_SB_UNK_0000_0c01";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000c06: return "I7_SB_UNK_0000_0c06"; case 0x00000c08: return "I7_SB_UNK_0000_0c08";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000c09: return "I7_SB_UNK_0000_0c09"; case 0x00000c10: return "I7_SB_UNK_0000_0c10";
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0x00000c11: return "I7_SB_UNK_0000_0c11"; case 0x00000c14: return "I7_SB_UNK_0000_0c14";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c15: return "I7_SB_UNK_0000_0c15"; case 0x00000c16: return "I7_SB_UNK_0000_0c16";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c17: return "I7_SB_UNK_0000_0c17"; case 0x00000c24: return "I7_SB_UNK_0000_0c24";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c30: return "I7_SB_UNK_0000_0c30"; case 0x00000c31: return "I7_SB_UNK_0000_0c31";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000c32: return "I7_SB_UNK_0000_0c32"; case 0x00000c33: return "I7_SB_UNK_0000_0c33";
b2e90826ea719b22452d1ff7b977d4f40995b428vboxsync case 0x00000c34: return "I7_SB_UNK_0000_0c34"; case 0x00000c35: return "I7_SB_UNK_0000_0c35";
78df65edff21c11c537f38e736707ea434ab5623vboxsync case 0x00000c36: return "I7_SB_UNK_0000_0c36"; case 0x00000c37: return "I7_SB_UNK_0000_0c37";
02e851310fa6b70ff20500172a9758a50731a451vboxsync case 0x00000c38: return "I7_SB_UNK_0000_0c38"; case 0x00000c39: return "I7_SB_UNK_0000_0c39";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d10: return "I7_SB_UNK_0000_0d10"; case 0x00000d11: return "I7_SB_UNK_0000_0d11";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d12: return "I7_SB_UNK_0000_0d12"; case 0x00000d13: return "I7_SB_UNK_0000_0d13";
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0x00000d14: return "I7_SB_UNK_0000_0d14"; case 0x00000d15: return "I7_SB_UNK_0000_0d15";
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0x00000d16: return "I7_SB_UNK_0000_0d16"; case 0x00000d17: return "I7_SB_UNK_0000_0d17";
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync case 0x00000d18: return "I7_SB_UNK_0000_0d18"; case 0x00000d19: return "I7_SB_UNK_0000_0d19";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d30: return "I7_SB_UNK_0000_0d30"; case 0x00000d31: return "I7_SB_UNK_0000_0d31";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d32: return "I7_SB_UNK_0000_0d32"; case 0x00000d33: return "I7_SB_UNK_0000_0d33";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d34: return "I7_SB_UNK_0000_0d34"; case 0x00000d35: return "I7_SB_UNK_0000_0d35";
a144bb4a097a1818739e00ba31bea88ce63f5345vboxsync case 0x00000d36: return "I7_SB_UNK_0000_0d36"; case 0x00000d37: return "I7_SB_UNK_0000_0d37";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0x00000d38: return "I7_SB_UNK_0000_0d38"; case 0x00000d39: return "I7_SB_UNK_0000_0d39";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d50: return "I7_SB_UNK_0000_0d50"; case 0x00000d51: return "I7_SB_UNK_0000_0d51";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d52: return "I7_SB_UNK_0000_0d52"; case 0x00000d53: return "I7_SB_UNK_0000_0d53";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d54: return "I7_SB_UNK_0000_0d54"; case 0x00000d55: return "I7_SB_UNK_0000_0d55";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d56: return "I7_SB_UNK_0000_0d56"; case 0x00000d57: return "I7_SB_UNK_0000_0d57";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d58: return "I7_SB_UNK_0000_0d58"; case 0x00000d59: return "I7_SB_UNK_0000_0d59";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d70: return "I7_SB_UNK_0000_0d70"; case 0x00000d71: return "I7_SB_UNK_0000_0d71";
78df65edff21c11c537f38e736707ea434ab5623vboxsync case 0x00000d72: return "I7_SB_UNK_0000_0d72"; case 0x00000d73: return "I7_SB_UNK_0000_0d73";
78df65edff21c11c537f38e736707ea434ab5623vboxsync case 0x00000d74: return "I7_SB_UNK_0000_0d74"; case 0x00000d75: return "I7_SB_UNK_0000_0d75";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d76: return "I7_SB_UNK_0000_0d76"; case 0x00000d77: return "I7_SB_UNK_0000_0d77";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d78: return "I7_SB_UNK_0000_0d78"; case 0x00000d79: return "I7_SB_UNK_0000_0d79";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d90: return "I7_SB_UNK_0000_0d90"; case 0x00000d91: return "I7_SB_UNK_0000_0d91";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d92: return "I7_SB_UNK_0000_0d92"; case 0x00000d93: return "I7_SB_UNK_0000_0d93";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d94: return "I7_SB_UNK_0000_0d94"; case 0x00000d95: return "I7_SB_UNK_0000_0d95";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000d96: return "I7_SB_UNK_0000_0d96"; case 0x00000d97: return "I7_SB_UNK_0000_0d97";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000d98: return "I7_SB_UNK_0000_0d98"; case 0x00000d99: return "I7_SB_UNK_0000_0d99";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000db0: return "I7_SB_UNK_0000_0db0"; case 0x00000db1: return "I7_SB_UNK_0000_0db1";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000db2: return "I7_SB_UNK_0000_0db2"; case 0x00000db3: return "I7_SB_UNK_0000_0db3";
090c459b9e90ca46e2ce2b8c81533ade3b23f3e9vboxsync case 0x00000db4: return "I7_SB_UNK_0000_0db4"; case 0x00000db5: return "I7_SB_UNK_0000_0db5";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000db6: return "I7_SB_UNK_0000_0db6"; case 0x00000db7: return "I7_SB_UNK_0000_0db7";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync case 0x00000db8: return "I7_SB_UNK_0000_0db8"; case 0x00000db9: return "I7_SB_UNK_0000_0db9";
daf1b2aee694fc8aca9e056e825b3359170ecf37vboxsync * Ditto for ivy bridge (observed on the i5-3570). There are some haswell
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * and sandybridge related docs on registers in this ares, but either
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * things are different for ivy or they're very incomplete. Again, kudos
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * to intel!
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_IvyBridge)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000700: return "I7_IB_UNK_0000_0700"; case 0x00000701: return "I7_IB_UNK_0000_0701";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000702: return "I7_IB_UNK_0000_0702"; case 0x00000703: return "I7_IB_UNK_0000_0703";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000704: return "I7_IB_UNK_0000_0704"; case 0x00000705: return "I7_IB_UNK_0000_0705";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000706: return "I7_IB_UNK_0000_0706"; case 0x00000707: return "I7_IB_UNK_0000_0707";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000708: return "I7_IB_UNK_0000_0708"; case 0x00000709: return "I7_IB_UNK_0000_0709";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x00000710: return "I7_IB_UNK_0000_0710"; case 0x00000711: return "I7_IB_UNK_0000_0711";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000712: return "I7_IB_UNK_0000_0712"; case 0x00000713: return "I7_IB_UNK_0000_0713";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000714: return "I7_IB_UNK_0000_0714"; case 0x00000715: return "I7_IB_UNK_0000_0715";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x00000716: return "I7_IB_UNK_0000_0716"; case 0x00000717: return "I7_IB_UNK_0000_0717";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000718: return "I7_IB_UNK_0000_0718"; case 0x00000719: return "I7_IB_UNK_0000_0719";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x00000720: return "I7_IB_UNK_0000_0720"; case 0x00000721: return "I7_IB_UNK_0000_0721";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000722: return "I7_IB_UNK_0000_0722"; case 0x00000723: return "I7_IB_UNK_0000_0723";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000724: return "I7_IB_UNK_0000_0724"; case 0x00000725: return "I7_IB_UNK_0000_0725";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0x00000726: return "I7_IB_UNK_0000_0726"; case 0x00000727: return "I7_IB_UNK_0000_0727";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x00000728: return "I7_IB_UNK_0000_0728"; case 0x00000729: return "I7_IB_UNK_0000_0729";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000730: return "I7_IB_UNK_0000_0730"; case 0x00000731: return "I7_IB_UNK_0000_0731";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x00000732: return "I7_IB_UNK_0000_0732"; case 0x00000733: return "I7_IB_UNK_0000_0733";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0x00000734: return "I7_IB_UNK_0000_0734"; case 0x00000735: return "I7_IB_UNK_0000_0735";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000736: return "I7_IB_UNK_0000_0736"; case 0x00000737: return "I7_IB_UNK_0000_0737";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000738: return "I7_IB_UNK_0000_0738"; case 0x00000739: return "I7_IB_UNK_0000_0739";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000740: return "I7_IB_UNK_0000_0740"; case 0x00000741: return "I7_IB_UNK_0000_0741";
af0a09edb4c1431b606fe207d4138da008f67f13vboxsync case 0x00000742: return "I7_IB_UNK_0000_0742"; case 0x00000743: return "I7_IB_UNK_0000_0743";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000744: return "I7_IB_UNK_0000_0744"; case 0x00000745: return "I7_IB_UNK_0000_0745";
37a7e3e6f9ce5f6cabeb3f734044e9e8ca9cb1bfvboxsync case 0x00000746: return "I7_IB_UNK_0000_0746"; case 0x00000747: return "I7_IB_UNK_0000_0747";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000748: return "I7_IB_UNK_0000_0748"; case 0x00000749: return "I7_IB_UNK_0000_0749";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Gets the name of an MSR.
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync * This may return a static buffer, so the content should only be considered
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync * valid until the next time this function is called!.
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync * @returns MSR name.
564cc620447c495b6ff9cbb9274e225692fe38dfvboxsync * @param uMsr The MSR in question.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * This MSR needs looking into, return a TODO_XXXX_XXXX name.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTStrPrintf(s_szBuf, sizeof(s_szBuf), "TODO_%04x_%04x", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Gets the name of an MSR range.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * This may return a static buffer, so the content should only be considered
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * valid until the next time this function is called!.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @returns MSR name.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param uMsr The first MSR in the range.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000040:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_n_FROM_IP" : "MSR_LASTBRANCH_n";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000060:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "MSR_LASTBRANCH_n_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003f8:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003f9:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fa:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "I7_MSR_PKG_Cn_RESIDENCY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fc:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fd:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000003fe:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "I7_MSR_CORE_Cn_RESIDENCY";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000400:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "IA32_MCi_CTL_STATUS_ADDR_MISC";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000680:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "MSR_LASTBRANCH_n_FROM_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000006c0:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "MSR_LASTBRANCH_n_TO_IP";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000800: case 0x00000801: case 0x00000802: case 0x00000803:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000804: case 0x00000805: case 0x00000806: case 0x00000807:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000808: case 0x00000809: case 0x0000080a: case 0x0000080b:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000080c: case 0x0000080d: case 0x0000080e: case 0x0000080f:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "IA32_X2APIC_n";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Replace the last char with 'n'.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * This MSR needs looking into, return a TODO_XXXX_XXXX_n name.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync RTStrPrintf(s_szBuf, sizeof(s_szBuf), "TODO_%04x_%04x_n", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Returns the function name for MSRs that have one or two.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @returns Function name if applicable, NULL if not.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param uMsr The MSR in question.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * @param pfTakesValue Whether this MSR function takes a value or not.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync * Optional.
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsyncstatic const char *getMsrFnName(uint32_t uMsr, bool *pfTakesValue)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000006:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (g_enmMicroarch >= kCpumMicroarch_Intel_First && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_First)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return NULL; /* TR4 / cache tag on Pentium, but that's for later. */
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "Ia32MonitorFilterLineSize";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x0000002a: *pfTakesValue = true; return "IntelEblCrPowerOn";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync //case 0x00000033: return "IntelTestCtl";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000040:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000041:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000042:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000043:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000044:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000045:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000046:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x00000047:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "IntelLastBranchFromToN";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000a8:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000a9:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000aa:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ab:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ac:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000ad:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "IntelCore2EmttmCrTablesN";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c1:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c2:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c3:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c4:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "Ia32PmcN";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c5:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c6:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c7:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000c8:
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync if (g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First)
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync return "Ia32PmcN";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e2: return "IntelPkgCStConfigControl";
30a23dfc653298a09d77d3045cf873b1bd6ddecfvboxsync case 0x000000e3: return "IntelCore2SmmCStMiscInfo";
case 0x00000193: return /*CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? NULL :*/ NULL /* Core2_Penryn. */;
case 0x000001aa: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "IntelI7MiscPwrMgmt" : NULL /*"P6PicSensCfg"*/;
case 0x000001ad: *pfTakesValue = true; return "IntelI7TurboRatioLimit"; /* SandyBridge+, Silvermount+ */
case 0x000001c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Nehalem ? "IntelI7LbrSelect" : NULL;
case 0x00000309: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
case 0x0000030a: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
case 0x0000030b: return CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch) ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
case 0x00000393: return "IntelI7UncPerfGlobalOvfCtrl"; /* X. ASSUMING this is the same on sandybridge and later. */
case 0x00000394: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPerfFixedCtr" /* X */ : "IntelI7UncPerfFixedCtrCtrl"; /* >= S,H */
case 0x00000395: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPerfFixedCtrCtrl" /* X*/ : "IntelI7UncPerfFixedCtr"; /* >= S,H */
case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncAddrOpcodeMatch" /* X */ : "IntelI7UncCBoxConfig"; /* >= S,H */
case 0x000003b0: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfCtrN"; /* >= S,H */
case 0x000003b1: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfCtrN"; /* >= S,H */
case 0x000003b2: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfEvtSelN"; /* >= S,H */
case 0x000003b3: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfEvtSelN"; /* >= S,H */
case 0x00000478: return g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "IntelCpuId1FeatureMaskEcdx" : NULL;
case 0x00000c80: return g_enmMicroarch > kCpumMicroarch_Intel_Core7_Nehalem ? "Ia32DebugInterface" : NULL;
case 0xc0011002: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd07hEbax" : NULL;
case 0xc0011003: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd06hEcx" : NULL;
case 0xc0011004: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd01hEdcx" : NULL;
case 0xc0011005: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlExt01hEdcx" : NULL;
case 0xc001100c: return "AmdK7NodeId"; /** @todo dunno if this was there is K7 already. Kinda doubt it. */
case 0xc0011019: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
case 0xc001101a: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
case 0xc001101b: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
case 0xc0011023: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg" : "AmdK7BusUnitCfg";
case 0xc0011029: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AmdFam15hDecoderCfg" : NULL;
case 0xc001102b: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg3" : NULL;
case 0xc001102c: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hExecUnitCfg" : NULL;
case 0xc001102d: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hLoadStoreCfg2" : NULL;
return NULL;
switch (uMsr)
return NULL;
switch (uMsr)
switch (uMsr)
case 0xc0010112: return UINT64_C(0xfffe0000) | ((RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(uint64_t)UINT32_MAX);
case 0xc0010113: return UINT64_C(0xfffe773f) | ((RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(uint64_t)UINT32_MAX);
switch (uMsr)
return VBCPUREPBADNESS_BOND_VILLAIN;
return VBCPUREPBADNESS_MIGHT_BITE;
return VBCPUREPBADNESS_MOSTLY_HARMLESS;
if (uValue == 0)
static void printMsrNewLine(void)
if (!pszWrFnName)
return VINF_SUCCESS;
if (pszAnnotation)
return VINF_SUCCESS;
if (pszAnnotation)
return VINF_SUCCESS;
static int printMsrValueExtended(uint32_t uMsr, uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask,
const char *pszAnnotation)
if (pszAnnotation)
return VINF_SUCCESS;
static int printMsrRangeValueReadOnly(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszAnnotation)
if (pszAnnotation)
return VINF_SUCCESS;
static int printMsrRangeValueIgnoreWrites(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszAnnotation)
if (pszAnnotation)
return VINF_SUCCESS;
static int printMsrFunction(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, const char *pszAnnotation)
if (!pszRdFnName)
if (!pszWrFnName)
if (pszAnnotation)
return VINF_SUCCESS;
static int printMsrFunctionReadOnly(uint32_t uMsr, const char *pszRdFnName, const char *pszAnnotation)
if (!pszRdFnName)
if (pszAnnotation)
return VINF_SUCCESS;
static int printMsrFunctionIgnoreWrites(uint32_t uMsr, const char *pszRdFnName, const char *pszAnnotation)
if (!pszRdFnName)
if (pszAnnotation)
return VINF_SUCCESS;
static int printMsrFunctionIgnoreMask(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName,
if (!pszRdFnName)
if (!pszWrFnName)
if (pszAnnotation)
return VINF_SUCCESS;
static int printMsrFunctionExtended(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, uint64_t uValue,
if (!pszRdFnName)
if (!pszWrFnName)
if (pszAnnotation)
return VINF_SUCCESS;
static int printMsrFunctionExtendedIdxVal(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, uint64_t uValue,
if (!pszRdFnName)
if (!pszWrFnName)
vbCpuRepPrintf(" MFX(%#010x, \"%s\", %s, %s, %#x", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, uValue);
if (pszAnnotation)
return VINF_SUCCESS;
if (!pszRdFnName)
if (!pszWrFnName)
if (!pszCpumCpuStorage)
if (!pszCpumCpuStorage)
return RTMsgErrorRc(VERR_NOT_FOUND, "Missing CPUMCPU member for %#s (%#x)\n", getMsrName(uMsr), uMsr);
vbCpuRepPrintf(" MFS(%#010x, \"%s\", %s, %s, %s),", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, pszCpumCpuStorage);
if (pszAnnotation)
return VINF_SUCCESS;
static int printMsrFunctionCpumCpuEx(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName,
const char *pszAnnotation)
if (!pszRdFnName)
if (!pszWrFnName)
if (!pszCpumCpuStorage)
if (!pszCpumCpuStorage)
return RTMsgErrorRc(VERR_NOT_FOUND, "Missing CPUMCPU member for %#s (%#x)\n", getMsrName(uMsr), uMsr);
vbCpuRepPrintf(" MFZ(%#010x, \"%s\", %s, %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, pszCpumCpuStorage);
if (pszAnnotation)
return VINF_SUCCESS;
static int printMsrRangeFunction(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
const char *pszAnnotation)
if (!pszRdFnName)
if (!pszWrFnName)
vbCpuRepPrintf(" RFN(%#010x, %#010x, \"%s\", %s, %s),", uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName);
if (pszAnnotation)
return VINF_SUCCESS;
static int printMsrRangeFunctionEx(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
if (!pszRdFnName)
if (!pszWrFnName)
vbCpuRepPrintf(" RSN(%#010x, %#010x, \"%s\", %s, %s", uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName);
if (pszAnnotation)
return VINF_SUCCESS;
static int printMsrRangeFunctionExIdxVal(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
if (!pszRdFnName)
if (!pszWrFnName)
if (pszAnnotation)
return VINF_SUCCESS;
if (pszAnnotation)
return VINF_SUCCESS;
return s_szBuf;
RTStrPrintf(s_szBuf, sizeof(s_szBuf), "%s value=%#x`%08x", pszExtra, RT_HI_U32(uValue), RT_LO_U32(uValue));
return s_szBuf;
RTStrPrintf(s_szBuf, sizeof(s_szBuf), "XXX: Unexpected value %#llx - wanted bits %#llx to be set.", uValue, fBits);
return s_szBuf;
int rc;
bool fTakesValue = false;
return rc;
if (pszFnName)
rc = printMsrValueIgnoreWrites(uMsr, fReadAsZero ? 0 : uValue, fReadAsZero ? annotateValue(uValue) : NULL);
else if (pszFnName)
else if (fReadAsZero)
else if (pszFnName)
else if (fReadAsZero)
else if (pszFnName)
else if (fReadAsZero)
else if (pszFnName)
else if (fReadAsZero)
return rc;
static int reportMsr_GenRangeFunctionEx(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, const char *pszRdWrFnName,
if (!pszRdWrFnName)
if (!pszRdWrFnName)
cRegs++;
bool fReadOnly0;
return rc;
bool fReadOnlyN;
return rc;
if (!fEarlyEndOk)
vbCpuRepDebug("MSR %s (%#x) range ended unexpectedly early on %#x: ro=%d ign=%#llx/%#llx gp=%#llx/%#llx [N/0]\n",
cRegs = i;
if (fNoIgnMask)
fIgnMask0 = 0;
&& iRange == 0;
if (fSimple)
return printMsrRangeFunctionExIdxVal(uMsr, uMsr + cRegs - 1, pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName,
static int reportMsr_GenRangeFunction(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, const char *pszRdWrFnName,
return reportMsr_GenRangeFunctionEx(paMsrs, cMsrs, cMax, pszRdWrFnName, paMsrs[0].uMsr, false /*fEarlyEndOk*/, false /*fNoIgnMask*/,
if (!pszRdWrFnName)
if (!pszRdWrFnName)
return rc;
if (vbCpuRepSupportsX2Apic())
|| vbCpuRepSupportsNX() ) )
return rc;
return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR types %u does not cause a GP as it should. (msr %#x)\n",
uEndTypes++;
return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR types detected to be %#x (msr %#x). Expected %#x.\n",
return VINF_SUCCESS;
static int reportMsr_Ia32MtrrPhysBaseMaskN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
cRegs++;
return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR variable MSR range is too large: cRegs=%#x\n", cRegs);
return rc;
return rc;
return rc;
return rc;
return rc;
"MTRR PHYS BASE register %#x behaves differently from %#x: ign=%#llx/%#llx gp=%#llx/%#llx (fSkipBase=%#llx)\n",
return rc;
"MTRR PHYS MASK register %#x behaves differently from %#x: ign=%#llx/%#llx gp=%#llx/%#llx (fSkipMask=%#llx)\n",
return VINF_SUCCESS;
return rc;
return rc;
return rc;
static int reportMsr_Ia32McCtlStatusAddrMiscN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
cRegs++;
cRegs++;
if (vbCpuRepSupportsLongMode())
|| vbCpuRepSupportsNX())
static int reportMsr_AmdFam10hMc4MiscN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
cRegs++;
return rc;
if (cUsed == 0)
return RTMsgErrorRc(VERR_NOT_EQUAL, "AmdFam16hMc4MiscN mismatch: fIgn=%#llx/%#llx fGp=%#llx/%#llx uMsr=%#x\n",
cUsed++;
if (cUsed > 0)
printMsrRangeFunctionEx(paMsrs[0].uMsr, paMsrs[cUsed - 1].uMsr, "AmdFam10hMc4MiscN", NULL, 0, fIgnMask, fGpMask, NULL);
return rc;
cReserved++;
return VINF_SUCCESS;
return VINF_SUCCESS;
return VINF_SUCCESS;
return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010016) / 2, fSkipMask, annotateValue(uValue));
return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010017) / 2, fSkipMask, annotateValue(uValue));
static int reportMsr_AmdFam10hPStateN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
cRegs++;
if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver) /* ?? - listed in 10-1Fh model BDKG as well asFam16h */
return rc;
return VINF_SUCCESS;
fSkipMask |= UINT32_C(0xff000000); /* NbVid - Northbridge VID - includes bit 24 for Fam15h and Fam16h. Odd... */
if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver) /* ?? - listed in 10-1Fh model BDKG as well asFam16h */
static int reportMsr_AmdGenPerfMixedRange(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, uint32_t *pidxLoop)
cRegs++;
return rc;
printMsrFunctionExtendedIdxVal(uMsr + i, NULL, NULL, i / 2, fIgnMask, fGpMask, annotateValue(paMsrs[i].uValue));
return VINF_SUCCESS;
fSkipMask |= RT_BIT_64(46) | RT_BIT_64(45); /* Killer field. Seen bit 46 set, 45 clear. Messing with either means reboot/BSOD. */
int rc;
else if (uMsr == 0x00000000 && g_enmVendor == CPUMCPUVENDOR_AMD && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
else if (uMsr == 0x00000001 && g_enmVendor == CPUMCPUVENDOR_AMD && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
rc = printMsrAlias(uMsr, 0x00000401, NULL); /** @todo not 101% correct on Fam15h and later, 0xc0010015[McstatusWrEn] effect differs. */
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchToN", uMsr, false,
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchFromN", uMsr, false,
NULL, &i);
rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 2 /*cMax*/, "IntelI7MsrOffCoreResponseN", &i);
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 22 /*cMax*/, NULL, 0x00000280, true /*fEarlyEndOk*/, false, 0, &i);
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3 /*cMax*/, NULL, 0x00000309, true /*fEarlyEndOk*/, false, 0, &i);
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 16, NULL, uMsr, false, false, UINT64_C(0xffff800000000000), &i);
uint64_t fCr3Mask = (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & (X86_CR3_PAE_PAGE_MASK | X86_CR3_AMD64_PAGE_MASK);
if (!vbCpuRepSupportsPae())
else if (uMsr == 0xc0000082 || uMsr == 0xc0000083 || uMsr == 0xc0000100 || uMsr == 0xc0000101 || uMsr == 0xc0000102)
rc = reportMsr_GenFunctionEx(uMsr, NULL, 0, UINT64_C(0xffff800000000000), annotateValue(uValue)); /* Canoncial address hack. */
rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 7, "AmdK8McCtlMaskN", 0xc0010044, true /*fEarlyEndOk*/, false, 0, &i);
return rc;
return VINF_SUCCESS;
static int hackingMsrs(void)
return VINF_SUCCESS;
return VINF_SUCCESS;
vbCpuRepDebug("warning: Unable to initialize the support library (%Rrc), skipping MSR detection.\n", rc);
return VINF_SUCCESS;
bool fGp;
vbCpuRepDebug("warning: MSR probing not supported by the support driver (%Rrc), skipping MSR detection.\n", rc);
return VINF_SUCCESS;
if (fHacking)
return rc;
pszNameC);
return rc;
pszNameC);
if (fFlags)
return VINF_SUCCESS;
switch (enmCpuVendor)
case CPUMCPUVENDOR_INVALID:
case CPUMCPUVENDOR_UNKNOWN:
case CPUMCPUVENDOR_32BIT_HACK:
static int produceCpuReport(void)
if (!ASMHasCpuId())
return RTMsgErrorRc(VERR_NOT_IMPLEMENTED, "Unknown CPU vendor: %.4s%.4s%.4s\n", &uEbx, &uEdx, &uEcx);
vbCpuRepDebug("CPU Vendor: %s - %.4s%.4s%.4s\n", CPUMR3CpuVendorName(enmVendor), &uEbx, &uEdx, &uEcx);
ASMCpuIdExSlow(0x80000002, 0, 0, 0, &szNameRaw[0 + 0], &szNameRaw[4 + 0], &szNameRaw[8 + 0], &szNameRaw[12 + 0]);
ASMCpuIdExSlow(0x80000003, 0, 0, 0, &szNameRaw[0 + 16], &szNameRaw[4 + 16], &szNameRaw[8 + 16], &szNameRaw[12 + 16]);
ASMCpuIdExSlow(0x80000004, 0, 0, 0, &szNameRaw[0 + 32], &szNameRaw[4 + 32], &szNameRaw[8 + 32], &szNameRaw[12 + 32]);
static const char * const s_apszSuffixes[] =
if (pszHit)
static const char * const s_apszWords[] =
char *pszHit;
cchBlanks++;
RTStrPrintf(szNameC, sizeof(szNameC), "%s_%u_%u_%u", cpuVendorToString(enmVendor), ASMGetCpuFamily(uEax),
if (g_pReportOut)
if (pchDot)
" * available from http://www.virtualbox.org. This file is free software;\n"
return rc;
return VINF_SUCCESS;
RTGetOptInit(&State, argc, argv, &s_aOptions[0], RT_ELEMENTS(s_aOptions), 1, RTGETOPTINIT_FLAGS_OPTS_FIRST);
int iOpt;
switch (iOpt)
return RTEXITCODE_SUCCESS;
return RTEXITCODE_SUCCESS;
switch (enmOp)
case kCpuReportOp_Normal:
if (pszOutput)
case kCpuReportOp_MsrsOnly:
case kCpuReportOp_MsrsHacking: