VBoxCpuReport.cpp revision 1e0e13b23ace43d2fe93d45953b123f63b7e547c
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * VBoxCpuReport - Produces the basis for a CPU DB entry.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Copyright (C) 2013 Oracle Corporation
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * available from http://www.virtualbox.org. This file is free software;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * you can redistribute it and/or modify it under the terms of the GNU
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * General Public License (GPL) as published by the Free Software
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/*******************************************************************************
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync* Header Files *
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync*******************************************************************************/
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/*******************************************************************************
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync* Structures and Typedefs *
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync*******************************************************************************/
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Write only register. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsynctypedef struct VBCPUREPMSR
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The first MSR register number. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** Flags (MSRREPORT_F_XXX). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The value we read, unless write-only. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/*******************************************************************************
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync* Global Variables *
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync*******************************************************************************/
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** The CPU vendor. Used by the MSR code. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic CPUMCPUVENDOR g_enmVendor = CPUMCPUVENDOR_INVALID;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** The CPU microarchitecture. Used by the MSR code. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic CPUMMICROARCH g_enmMicroarch = kCpumMicroarch_Invalid;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Set if g_enmMicroarch indicates an Intel NetBurst CPU. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic bool g_fIntelNetBurst = false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** The alternative report stream. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** The alternative debug stream. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Always print a copy of the report to standard error. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Alternatively, also print to a log file. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Give the output device a chance to write / display it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Output to report file, if requested. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Always print a copy of the report to standard out. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int vbCpuRepMsrsAddOne(VBCPUREPMSR **ppaMsrs, uint32_t *pcMsrs,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Grow the array?
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync void *pvNew = RTMemRealloc(*ppaMsrs, (cMsrs + 64) * sizeof(**ppaMsrs));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Returns the max physical address width as a number of bits.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns Bit count.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (ASMIsValidExtRange(cMaxExt)&& cMaxExt >= 0x80000008)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && (ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PSE36))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic bool vbCpuRepSupportsPae(void)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic bool vbCpuRepSupportsLongMode(void)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic bool vbCpuRepSupportsNX(void)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic bool vbCpuRepSupportsX2Apic(void)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && (ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_X2APIC);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic bool msrProberWrite(uint32_t uMsr, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = SUPR3MsrProberWrite(uMsr, NIL_RTCPUID, uValue, &fGp);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic bool msrProberRead(uint32_t uMsr, uint64_t *puValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = SUPR3MsrProberRead(uMsr, NIL_RTCPUID, puValue, &fGp);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Tries to modify the register by writing the original value to it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, UINT64_MAX, 0, &Result);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Tries to modify the register by writing zero to it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, 0, 0, &Result);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Tries to modify each bit in the MSR and see if we can make it change.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pfIgnMask The ignore mask to update.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pfGpMask The GP mask to update.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param fSkipMask Mask of bits to skip.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int msrProberModifyBitChanges(uint32_t uMsr, uint64_t *pfIgnMask, uint64_t *pfGpMask, uint64_t fSkipMask)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Set it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, fBitMask, &ResultSet);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(rc, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, fBitMask, rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Clear it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, 0, &ResultClear);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(rc, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, 0, rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if ( ( ((ResultSet.uBefore ^ ResultSet.uAfter) & fBitMask) == 0
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && ( ((ResultClear.uBefore ^ ResultClear.uAfter) & fBitMask) == 0
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Tries to modify one bit.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @retval -2 on API error.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @retval -1 on \#GP.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @retval 0 if ignored.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @retval 1 if it changed.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param iBit The bit to try modify.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int msrProberModifyBit(uint32_t uMsr, unsigned iBit)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Set it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, fBitMask, &ResultSet);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(-2, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, fBitMask, rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Clear it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, ~fBitMask, 0, &ResultClear);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(-2, "SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, ~fBitMask, 0, rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ( ( ((ResultSet.uBefore ^ ResultSet.uAfter) & fBitMask) != 0
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || ( ((ResultClear.uBefore ^ ResultClear.uAfter) & fBitMask) != 0
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Tries to do a simple AND+OR change and see if we \#GP or not.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @retval @c true if successfully modified.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @retval @c false if \#GP or other error.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param fAndMask The AND mask.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param fOrMask The OR mask.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic bool msrProberModifySimpleGp(uint32_t uMsr, uint64_t fAndMask, uint64_t fOrMask)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = SUPR3MsrProberModify(uMsr, NIL_RTCPUID, fAndMask, fOrMask, &Result);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTMsgError("SUPR3MsrProberModify(%#x,,%#llx,%#llx,): %Rrc", uMsr, fAndMask, fOrMask, rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Combination of the basic tests.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param fSkipMask Mask of bits to skip.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pfReadOnly Where to return read-only status.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pfIgnMask Where to return the write ignore mask. Need not
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * be initialized.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pfGpMask Where to return the write GP mask. Need not
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * be initialized.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int msrProberModifyBasicTests(uint32_t uMsr, uint64_t fSkipMask, bool *pfReadOnly, uint64_t *pfIgnMask, uint64_t *pfGpMask)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return msrProberModifyBitChanges(uMsr, pfIgnMask, pfGpMask, fSkipMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Determines for the MSR AND mask.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Older CPUs doesn't necessiarly implement all bits of the MSR register number.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * So, we have to approximate how many are used so we don't get an overly large
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * and confusing set of MSRs when probing.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns The mask.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync static uint32_t const s_aMsrs[VBCPUREP_MASK_TEST_MSRS] =
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Try a bunch of mostly read only registers: */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync MSR_P5_MC_TYPE, MSR_IA32_PLATFORM_ID, MSR_IA32_MTRR_CAP, MSR_IA32_MCG_CAP, MSR_IA32_CR_PAT,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Then some which aren't supposed to be present on any CPU: */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Get the base values. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync for (unsigned i = 0; i < RT_ELEMENTS(s_aMsrs); i++)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //vbCpuRepDebug("Base: %#x -> %#llx\n", s_aMsrs[i], auBaseValues[i]);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Do the probing. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync for (unsigned iTest = 0; iTest <= 64 && fMsrOrMask < UINT32_MAX; iTest++)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync for (unsigned i = 0; i < RT_ELEMENTS(s_aMsrs); i++)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (!msrProberRead(s_aMsrs[i] | fMsrOrMask, &uValue))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint32_t fMsrMask = iBit >= 31 ? UINT32_MAX : RT_BIT_32(iBit + 1) - 1;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("MSR AND mask: quit on iBit=%u uMsr=%#x (%#x) %llx != %llx => fMsrMask=%#x\n",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync iBit, s_aMsrs[i] | (uint32_t)fMsrOrMask, s_aMsrs[i], uValue, auBaseValues[i], fMsrMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Advance. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("MSR AND mask: less that %u bits that matters?!? => fMsrMask=%#x\n", iBit + 1, fMsrMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int findMsrs(VBCPUREPMSR **ppaMsrs, uint32_t *pcMsrs, uint32_t fMsrMask)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Gather them.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync static struct { uint32_t uFirst, cMsrs; } const s_aRanges[] =
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync { 0xc0000000, 0x00022000 }, /* Had some trouble here on solaris with the tstVMM setup. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync for (unsigned i = 0; i < RT_ELEMENTS(s_aRanges); i++)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Skip 0xc0011012..13 as it seems to be bad for our health (Phenom II X6 1100T). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ((uMsr >= 0xc0011012 && uMsr <= 0xc0011013) && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Read probing normally does it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync bool fGp = true;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = SUPR3MsrProberRead(uMsr, NIL_RTCPUID, &uValue, &fGp);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(rc, "SUPR3MsrProberRead failed on %#x: %Rrc\n", uMsr, rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* VIA HACK - writing to 0x0000317e on a quad core make the core unresponsive. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0x0000317e && g_enmVendor == CPUMCPUVENDOR_VIA)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || (*ppaMsrs)[*pcMsrs - 1].fFlags != VBCPUREPMSR_F_WRITE_ONLY;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Is it a write only register? */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = SUPR3MsrProberWrite(uMsr, NIL_RTCPUID, 0, &fGp);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(rc, "SUPR3MsrProberWrite failed on %#x: %Rrc\n", uMsr, rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Tweaks. On Intel CPUs we've got trouble detecting
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * IA32_BIOS_UPDT_TRIG (0x00000079), so we have to add it manually here.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Ditto on AMD with PATCH_LOADER (0xc0010020).
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && g_enmMicroarch >= kCpumMicroarch_Intel_P6_Core_Atom_First
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Add it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = vbCpuRepMsrsAddOne(ppaMsrs, pcMsrs, uMsr, uValue, fFlags);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(rc, "Out of memory (uMsr=%#x).\n", uMsr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("%#010x: uValue=%#llx fFlags=%#x\n", uMsr, uValue, fFlags);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Get the name of the specified MSR, if we know it and can handle it.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Do _NOT_ add any new names here without ALSO at the SAME TIME making sure it
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * is handled correctly by the PROBING CODE and REPORTED correctly!!
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns Pointer to name if handled, NULL if not yet explored.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR in question.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo figure out where NCU_EVENT_CORE_MASK might be... */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000006:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (g_enmMicroarch >= kCpumMicroarch_Intel_First && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_First)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return NULL; /* TR4 / cache tag on Pentium, but that's for later. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "IA32_MONITOR_FILTER_LINE_SIZE";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x0000000e: return "P?_TR12"; /* K6-III docs */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000018: return "P6_UNK_0000_0018"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000021: return "C2_UNK_0000_0021"; /* Core2_Penryn */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000002a: return g_fIntelNetBurst ? "P4_EBC_HARD_POWERON" : "EBL_CR_POWERON";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000002b: return g_fIntelNetBurst ? "P4_EBC_SOFT_POWERON" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000002c: return g_fIntelNetBurst ? "P4_EBC_FREQUENCY_ID" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000002e: return "I7_UNK_0000_002e"; /* SandyBridge, IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000002f: return "P6_UNK_0000_002f"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000032: return "P6_UNK_0000_0032"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000034: return "P6_UNK_0000_0034"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000035: return "P6_UNK_0000_0035"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000036: return "I7_UNK_0000_0036"; /* SandyBridge, IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000039: return "C2_UNK_0000_0039"; /* Core2_Penryn */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000003b: return "P6_UNK_0000_003b"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000003e: return "I7_UNK_0000_003e"; /* SandyBridge, IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000003f: return "P6_UNK_0000_003f"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000040: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_0_FROM_IP" : "MSR_LASTBRANCH_0";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000041: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_1_FROM_IP" : "MSR_LASTBRANCH_1";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000042: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_2_FROM_IP" : "MSR_LASTBRANCH_2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000043: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_3_FROM_IP" : "MSR_LASTBRANCH_3";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000044: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_4_FROM_IP" : "MSR_LASTBRANCH_4";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000045: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_5_FROM_IP" : "MSR_LASTBRANCH_5";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000046: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_6_FROM_IP" : "MSR_LASTBRANCH_6";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000047: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_7_FROM_IP" : "MSR_LASTBRANCH_7";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000004a: return "P6_UNK_0000_004a"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000004b: return "P6_UNK_0000_004b"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000004c: return "P6_UNK_0000_004c"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000004d: return "P6_UNK_0000_004d"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000004e: return "P6_UNK_0000_004e"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000004f: return "P6_UNK_0000_004f"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000050: return "P6_UNK_0000_0050"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000051: return "P6_UNK_0000_0051"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000052: return "P6_UNK_0000_0052"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000053: return "P6_UNK_0000_0053"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000054: return "P6_UNK_0000_0054"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000060: return "MSR_LASTBRANCH_0_TO_IP"; /* Core2_Penryn */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000061: return "MSR_LASTBRANCH_1_TO_IP"; /* Core2_Penryn */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000062: return "MSR_LASTBRANCH_2_TO_IP"; /* Core2_Penryn */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000063: return "MSR_LASTBRANCH_3_TO_IP"; /* Core2_Penryn */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000064: return "MSR_LASTBRANCH_4_TO_IP"; /* Atom? */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000006c: return "P6_UNK_0000_006c"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000006d: return "P6_UNK_0000_006d"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000006e: return "P6_UNK_0000_006e"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000006f: return "P6_UNK_0000_006f"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000008b: return g_enmVendor == CPUMCPUVENDOR_AMD ? "AMD_K8_PATCH_LEVEL"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync : g_fIntelNetBurst ? "IA32_BIOS_SIGN_ID" : "BBL_CR_D3|BIOS_SIGN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000008c: return "P6_UNK_0000_008c"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000008d: return "P6_UNK_0000_008d"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000008e: return "P6_UNK_0000_008e"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000008f: return "P6_UNK_0000_008f"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000090: return "P6_UNK_0000_0090"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000ae: return "P6_UNK_0000_00ae"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* PMC4+ first seen on SandyBridge. The earlier cut off is just to be
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync on the safe side as we must avoid P6_M_Dothan and possibly others. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000c5: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC4" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000c6: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC5" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000c7: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC6" : "P6_UNK_0000_00c7"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? "IA32_PMC7" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000cd: return "P6_UNK_0000_00cd"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000ce: return "P6_UNK_0000_00ce"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000cf: return "C2_UNK_0000_00cf"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000e0: return "C2_UNK_0000_00e0"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000e1: return "C2_UNK_0000_00e1"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000e2: return "MSR_PKG_CST_CONFIG_CONTROL";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000e3: return "C2_SMM_CST_MISC_INFO"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000e5: return "C2_UNK_0000_00e5"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000ee: return "C1_EXT_CONFIG"; /* Core2_Penryn. msrtool lists it for Core1 as well. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000102: return "I7_IB_UNK_0000_0102"; /* IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000103: return "I7_IB_UNK_0000_0103"; /* IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000104: return "I7_IB_UNK_0000_0104"; /* IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000011b: return "P6_UNK_0000_011b"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000011c: return "C2_UNK_0000_011c"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000130: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000131: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ? "CPUID80000001_FEATURE_MASK" : "P6_UNK_0000_0131" /* P6_M_Dothan. */;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000132: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000133: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000134: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000013c: return "I7_SB_AES_NI_CTL"; /* SandyBridge. Bit 0 is lock bit, bit 1 disables AES-NI. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000140: return "I7_IB_UNK_0000_0140"; /* IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000142: return "I7_IB_UNK_0000_0142"; /* IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000014e: return "P6_UNK_0000_014e"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000014f: return "P6_UNK_0000_014f"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000150: return "P6_UNK_0000_0150"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000151: return "P6_UNK_0000_0151"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000154: return "P6_UNK_0000_0154"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000015b: return "P6_UNK_0000_015b"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000015e: return "C2_UNK_0000_015e"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000015f: return "C1_DTS_CAL_CTRL"; /* Core2_Penryn. msrtool only docs this for core1! */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000017f: return "I7_SB_ERROR_CONTROL"; /* SandyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000180: return g_fIntelNetBurst ? "MSR_MCG_RAX" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000181: return g_fIntelNetBurst ? "MSR_MCG_RBX" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000182: return g_fIntelNetBurst ? "MSR_MCG_RCX" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000183: return g_fIntelNetBurst ? "MSR_MCG_RDX" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000184: return g_fIntelNetBurst ? "MSR_MCG_RSI" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000185: return g_fIntelNetBurst ? "MSR_MCG_RDI" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000186: return g_fIntelNetBurst ? "MSR_MCG_RBP" : "IA32_PERFEVTSEL0";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000187: return g_fIntelNetBurst ? "MSR_MCG_RSP" : "IA32_PERFEVTSEL1";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000188: return g_fIntelNetBurst ? "MSR_MCG_RFLAGS" : "IA32_PERFEVTSEL2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000189: return g_fIntelNetBurst ? "MSR_MCG_RIP" : "IA32_PERFEVTSEL3";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000018a: return g_fIntelNetBurst ? "MSR_MCG_MISC" : "IA32_PERFEVTSEL4";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000018b: return g_fIntelNetBurst ? "MSR_MCG_RESERVED1" : "IA32_PERFEVTSEL5";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000018c: return g_fIntelNetBurst ? "MSR_MCG_RESERVED2" : "IA32_PERFEVTSEL6";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000018d: return g_fIntelNetBurst ? "MSR_MCG_RESERVED3" : "IA32_PERFEVTSEL7";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000018e: return g_fIntelNetBurst ? "MSR_MCG_RESERVED4" : "IA32_PERFEVTSEL8";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000018f: return g_fIntelNetBurst ? "MSR_MCG_RESERVED5" : "IA32_PERFEVTSEL9";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000190: return g_fIntelNetBurst ? "MSR_MCG_R8" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000191: return g_fIntelNetBurst ? "MSR_MCG_R9" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000192: return g_fIntelNetBurst ? "MSR_MCG_R10" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000193: return g_fIntelNetBurst ? "MSR_MCG_R11" : "C2_UNK_0000_0193";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000194: return g_fIntelNetBurst ? "MSR_MCG_R12" : "CLOCK_FLEX_MAX";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000195: return g_fIntelNetBurst ? "MSR_MCG_R13" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000196: return g_fIntelNetBurst ? "MSR_MCG_R14" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000197: return g_fIntelNetBurst ? "MSR_MCG_R15" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000019e: return "P6_UNK_0000_019e"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000019f: return "P6_UNK_0000_019f"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001a1: return g_fIntelNetBurst ? "MSR_PLATFORM_BRV" : "P6_UNK_0000_01a1" /* P6_M_Dothan. */;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001a2: return g_fIntelNetBurst ? "P4_UNK_0000_01a2" : "I7_MSR_TEMPERATURE_TARGET" /* SandyBridge, IvyBridge. */;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001a4: return "I7_UNK_0000_01a4"; /* SandyBridge, IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001a8: return "I7_UNK_0000_01a8"; /* SandyBridge, IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001aa: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "MSR_MISC_PWR_MGMT" : "P6_PIC_SENS_CFG" /* Pentium M. */;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001ad: return "I7_MSR_TURBO_RATIO_LIMIT"; /* SandyBridge+, Silvermount+ */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001ae: return "P6_UNK_0000_01ae"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001af: return "P6_UNK_0000_01af"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001b1: return "IA32_PACKAGE_THERM_STATUS";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001b2: return "IA32_PACKAGE_THERM_INTERRUPT";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001bf: return "C2_UNK_0000_01bf"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001c6: return "I7_UNK_0000_01c6"; /* SandyBridge*/
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Nehalem ? "MSR_LBR_SELECT" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001c9: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_End
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ? "MSR_LASTBRANCH_TOS" : NULL /* Pentium M Dothan seems to have something else here. */;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001d3: return "P6_UNK_0000_01d3"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001d7: return g_fIntelNetBurst ? "MSR_LER_FROM_LIP" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001d8: return g_fIntelNetBurst ? "MSR_LER_TO_LIP" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001da: return g_fIntelNetBurst ? "MSR_LASTBRANCH_TOS" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001db: return g_fIntelNetBurst ? "P6_LASTBRANCH_0" : "P6_LAST_BRANCH_FROM_IP"; /* Not exclusive to P6, also AMD. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001dc: return g_fIntelNetBurst ? "P6_LASTBRANCH_1" : "P6_LAST_BRANCH_TO_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001dd: return g_fIntelNetBurst ? "P6_LASTBRANCH_2" : "P6_LAST_INT_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001de: return g_fIntelNetBurst ? "P6_LASTBRANCH_3" : "P6_LAST_INT_TO_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001f0: return "I7_VLW_CAPABILITY"; /* SandyBridge. Bit 1 is A20M and was implemented incorrectly (AAJ49). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x00000296: return "IA32_MC22_CTL2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x00000297: return "IA32_MC23_CTL2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x00000298: return "IA32_MC24_CTL2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x00000299: return "IA32_MC25_CTL2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x0000029a: return "IA32_MC26_CTL2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x0000029b: return "IA32_MC27_CTL2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x0000029c: return "IA32_MC28_CTL2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x0000029d: return "IA32_MC29_CTL2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x0000029e: return "IA32_MC30_CTL2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x0000029f: return "IA32_MC31_CTL2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000002e0: return "I7_SB_NO_EVICT_MODE"; /* (Bits 1 & 0 are said to have something to do with no-evict cache mode used during early boot.) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000002e6: return "I7_IB_UNK_0000_02e6"; /* IvyBridge */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000002e7: return "I7_IB_UNK_0000_02e7"; /* IvyBridge */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000300: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER0" : "I7_SB_UNK_0000_0300" /* SandyBridge */;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000301: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000302: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER2" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000303: return g_fIntelNetBurst ? "P4_MSR_BPU_COUNTER3" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000304: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000305: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER1" : "I7_SB_UNK_0000_0305" /* SandyBridge, IvyBridge */;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000306: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER2" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000307: return g_fIntelNetBurst ? "P4_MSR_MS_COUNTER3" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000308: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000309: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER1" : "IA32_FIXED_CTR0";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000030a: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER2" : "IA32_FIXED_CTR1";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000030b: return g_fIntelNetBurst ? "P4_MSR_FLAME_COUNTER3" : "IA32_FIXED_CTR2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000030c: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000030d: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000030e: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER2" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000030f: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER3" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000310: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER4" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000311: return g_fIntelNetBurst ? "P4_MSR_IQ_COUNTER5" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000360: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000361: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000362: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR2" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000363: return g_fIntelNetBurst ? "P4_MSR_BPU_CCCR3" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000364: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000365: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000366: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR2" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000367: return g_fIntelNetBurst ? "P4_MSR_MS_CCCR3" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000368: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000369: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000036a: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR2" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000036b: return g_fIntelNetBurst ? "P4_MSR_FLAME_CCCR3" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000036c: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000036d: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000036e: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR2" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000036f: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR3" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000370: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR4" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000371: return g_fIntelNetBurst ? "P4_MSR_IQ_CCCR5" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000390: return "IA32_PERF_GLOBAL_OVF_CTRL";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000391: return "I7_UNC_PERF_GLOBAL_CTRL"; /* S,H,X */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000392: return "I7_UNC_PERF_GLOBAL_STATUS"; /* S,H,X */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000393: return "I7_UNC_PERF_GLOBAL_OVF_CTRL"; /* X. ASSUMING this is the same on sandybridge and later. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000394: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PERF_FIXED_CTR" /* X */ : "I7_UNC_PERF_FIXED_CTR_CTRL"; /* >= S,H */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000395: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PERF_FIXED_CTR_CTRL" /* X*/ : "I7_UNC_PERF_FIXED_CTR"; /* >= S,H */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_ADDR_OPCODE_MATCH" /* X */ : "I7_UNC_CBO_CONFIG"; /* >= S,H */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000397: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_IvyBridge ? NULL : "I7_IB_UNK_0000_0397";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003a0: return g_fIntelNetBurst ? "P4_MSR_BSU_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003a1: return g_fIntelNetBurst ? "P4_MSR_BSU_ESCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003a2: return g_fIntelNetBurst ? "P4_MSR_FSB_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003a3: return g_fIntelNetBurst ? "P4_MSR_FSB_ESCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003a4: return g_fIntelNetBurst ? "P4_MSR_FIRM_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003a5: return g_fIntelNetBurst ? "P4_MSR_FIRM_ESCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003a6: return g_fIntelNetBurst ? "P4_MSR_FLAME_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003a7: return g_fIntelNetBurst ? "P4_MSR_FLAME_ESCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003a8: return g_fIntelNetBurst ? "P4_MSR_DAC_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003a9: return g_fIntelNetBurst ? "P4_MSR_DAC_ESCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003aa: return g_fIntelNetBurst ? "P4_MSR_MOB_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003ab: return g_fIntelNetBurst ? "P4_MSR_MOB_ESCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003ac: return g_fIntelNetBurst ? "P4_MSR_PMH_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003ad: return g_fIntelNetBurst ? "P4_MSR_PMH_ESCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003ae: return g_fIntelNetBurst ? "P4_MSR_SAAT_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003af: return g_fIntelNetBurst ? "P4_MSR_SAAT_ESCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b0: return g_fIntelNetBurst ? "P4_MSR_U2L_ESCR0" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC0" /* X */ : "I7_UNC_ARB_PERF_CTR0"; /* >= S,H */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b1: return g_fIntelNetBurst ? "P4_MSR_U2L_ESCR1" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC1" /* X */ : "I7_UNC_ARB_PERF_CTR1"; /* >= S,H */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b2: return g_fIntelNetBurst ? "P4_MSR_BPU_ESCR0" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC2" /* X */ : "I7_UNC_ARB_PERF_EVT_SEL0"; /* >= S,H */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b3: return g_fIntelNetBurst ? "P4_MSR_BPU_ESCR1" : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "I7_UNC_PMC3" /* X */ : "I7_UNC_ARB_PERF_EVT_SEL1"; /* >= S,H */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b4: return g_fIntelNetBurst ? "P4_MSR_IS_ESCR0" : "I7_UNC_PMC4";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b5: return g_fIntelNetBurst ? "P4_MSR_IS_ESCR1" : "I7_UNC_PMC5";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b6: return g_fIntelNetBurst ? "P4_MSR_ITLB_ESCR0" : "I7_UNC_PMC6";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b7: return g_fIntelNetBurst ? "P4_MSR_ITLB_ESCR1" : "I7_UNC_PMC7";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b8: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b9: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003ba: return g_fIntelNetBurst ? "P4_MSR_IQ_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003bb: return g_fIntelNetBurst ? "P4_MSR_IQ_ESCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003bc: return g_fIntelNetBurst ? "P4_MSR_RAT_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003bd: return g_fIntelNetBurst ? "P4_MSR_RAT_ESCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003be: return g_fIntelNetBurst ? "P4_MSR_SSU_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003c0: return g_fIntelNetBurst ? "P4_MSR_MS_ESCR0" : "I7_UNC_PERF_EVT_SEL0";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003c1: return g_fIntelNetBurst ? "P4_MSR_MS_ESCR1" : "I7_UNC_PERF_EVT_SEL1";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003c2: return g_fIntelNetBurst ? "P4_MSR_TBPU_ESCR0" : "I7_UNC_PERF_EVT_SEL2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003c3: return g_fIntelNetBurst ? "P4_MSR_TBPU_ESCR1" : "I7_UNC_PERF_EVT_SEL3";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003c4: return g_fIntelNetBurst ? "P4_MSR_TC_ESCR0" : "I7_UNC_PERF_EVT_SEL4";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003c5: return g_fIntelNetBurst ? "P4_MSR_TC_ESCR1" : "I7_UNC_PERF_EVT_SEL5";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003c6: return g_fIntelNetBurst ? NULL : "I7_UNC_PERF_EVT_SEL6";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003c7: return g_fIntelNetBurst ? NULL : "I7_UNC_PERF_EVT_SEL7";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003c8: return g_fIntelNetBurst ? "P4_MSR_IX_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003c9: return g_fIntelNetBurst ? "P4_MSR_IX_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003ca: return g_fIntelNetBurst ? "P4_MSR_ALF_ESCR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003cb: return g_fIntelNetBurst ? "P4_MSR_ALF_ESCR1" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003cc: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR2" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003cd: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR3" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003e0: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR4" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003e1: return g_fIntelNetBurst ? "P4_MSR_CRU_ESCR5" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003f0: return g_fIntelNetBurst ? "P4_MSR_TC_PRECISE_EVENT" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003f2: return g_fIntelNetBurst ? "P4_MSR_PEBS_MATRIX_VERT" : "IA32_PEBS_ENABLE";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003f3: return g_fIntelNetBurst ? "P4_UNK_0000_03f3" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003f4: return g_fIntelNetBurst ? "P4_UNK_0000_03f4" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003f5: return g_fIntelNetBurst ? "P4_UNK_0000_03f5" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003f6: return g_fIntelNetBurst ? "P4_UNK_0000_03f6" : "I7_MSR_PEBS_LD_LAT";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003f7: return g_fIntelNetBurst ? "P4_UNK_0000_03f7" : "I7_MSR_PEBS_LD_LAT";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003f8: return g_fIntelNetBurst ? "P4_UNK_0000_03f8" : "I7_MSR_PKG_C3_RESIDENCY";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003fc: return "I7_MSR_CORE_C3_RESIDENCY";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003fd: return "I7_MSR_CORE_C6_RESIDENCY";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003fe: return "I7_MSR_CORE_C7_RESIDENCY";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000478: return g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "CPUID1_FEATURE_MASK" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000048b: return "IA32_VMX_PROCBASED_CTLS2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000048d: return "IA32_VMX_TRUE_PINBASED_CTLS";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000048e: return "IA32_VMX_TRUE_PROCBASED_CTLS";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000490: return "IA32_VMX_TRUE_ENTRY_CTLS";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004f8: return "C2_UNK_0000_04f8"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004f9: return "C2_UNK_0000_04f9"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004fa: return "C2_UNK_0000_04fa"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004fb: return "C2_UNK_0000_04fb"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004fc: return "C2_UNK_0000_04fc"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004fd: return "C2_UNK_0000_04fd"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004fe: return "C2_UNK_0000_04fe"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004ff: return "C2_UNK_0000_04ff"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000590: return "C2_UNK_0000_0590"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000591: return "C2_UNK_0000_0591"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000005a0: return "C2_PECI_CTL"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000005a1: return "C2_UNK_0000_05a1"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000601: return "I7_SB_MSR_VR_CURRENT_CONFIG"; /* SandyBridge, IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000603: return "I7_SB_MSR_VR_MISC_CONFIG"; /* SandyBridge, IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000606: return "I7_SB_MSR_RAPL_POWER_UNIT"; /* SandyBridge, IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000060a: return "I7_SB_MSR_PKGC3_IRTL"; /* SandyBridge, IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000060b: return "I7_SB_MSR_PKGC6_IRTL"; /* SandyBridge, IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000060c: return "I7_SB_MSR_PKGC7_IRTL"; /* SandyBridge, IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000060d: return "I7_SB_MSR_PKG_C2_RESIDENCY"; /* SandyBridge, IvyBridge. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000610: return "I7_SB_MSR_PKG_POWER_LIMIT";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000611: return "I7_SB_MSR_PKG_ENERGY_STATUS";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000613: return "I7_SB_MSR_PKG_PERF_STATUS";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000614: return "I7_SB_MSR_PKG_POWER_INFO";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000618: return "I7_SB_MSR_DRAM_POWER_LIMIT";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000619: return "I7_SB_MSR_DRAM_ENERGY_STATUS";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000061b: return "I7_SB_MSR_DRAM_PERF_STATUS";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000061c: return "I7_SB_MSR_DRAM_POWER_INFO";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000638: return "I7_SB_MSR_PP0_POWER_LIMIT";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000639: return "I7_SB_MSR_PP0_ENERGY_STATUS";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000063b: return "I7_SB_MSR_PP0_PERF_STATUS";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000640: return "I7_HW_MSR_PP0_POWER_LIMIT";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000641: return "I7_HW_MSR_PP0_ENERGY_STATUS";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000648: return "I7_IB_MSR_CONFIG_TDP_NOMINAL";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000649: return "I7_IB_MSR_CONFIG_TDP_LEVEL1";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000064a: return "I7_IB_MSR_CONFIG_TDP_LEVEL2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000064b: return "I7_IB_MSR_CONFIG_TDP_CONTROL";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000064c: return "I7_IB_MSR_TURBO_ACTIVATION_RATIO";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000680: return "MSR_LASTBRANCH_0_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000681: return "MSR_LASTBRANCH_1_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000682: return "MSR_LASTBRANCH_2_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000683: return "MSR_LASTBRANCH_3_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000684: return "MSR_LASTBRANCH_4_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000685: return "MSR_LASTBRANCH_5_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000686: return "MSR_LASTBRANCH_6_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000687: return "MSR_LASTBRANCH_7_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000688: return "MSR_LASTBRANCH_8_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000689: return "MSR_LASTBRANCH_9_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000068a: return "MSR_LASTBRANCH_10_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000068b: return "MSR_LASTBRANCH_11_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000068c: return "MSR_LASTBRANCH_12_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000068d: return "MSR_LASTBRANCH_13_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000068e: return "MSR_LASTBRANCH_14_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000068f: return "MSR_LASTBRANCH_15_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c80: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "IA32_DEBUG_INTERFACE" : NULL; /* Mentioned in an intel dataskit called 4th-gen-core-family-desktop-vol-1-datasheet.pdf. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c81: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c81" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c82: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c82" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c83: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "I7_IB_UNK_0000_0c83" : NULL; /* Probably related to IA32_DEBUG_INTERFACE... */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* 0x1000..0x1004 seems to have been used by IBM 386 and 486 clones too. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000103f: return "P6_UNK_0000_103f"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000010cd: return "P6_UNK_0000_10cd"; /* P6_M_Dothan. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00002000: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR0" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00002002: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR2" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00002003: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR3" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00002004: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_CR4" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000203f: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_203f" /* P6_M_Dothan. */ : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000020cd: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_20cd" /* P6_M_Dothan. */ : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000303f: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_303f" /* P6_M_Dothan. */ : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000030cd: return g_enmVendor == CPUMCPUVENDOR_INTEL ? "P6_UNK_0000_30cd" /* P6_M_Dothan. */ : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0000105: return "AMD_15H_LWP_CFG"; /* Only Family 15h? */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0000106: return "AMD_15H_LWP_CBADDR"; /* Only Family 15h? */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010043: return "AMD_K8_THERMTRIP_STATUS"; /* BDKG says it was removed in K8 revision C.*/
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001004b: return "AMD_K8_MC_CTL_MASK_7";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010054: return "AMD_K8_SMI_ON_IO_TRAP_CTL_STS";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010056: return "AMD_K8_SMI_TRIGGER_IO_CYCLE";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010058: return "AMD_10H_MMIO_CFG_BASE_ADDR";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010059: return "AMD_10H_TRAP_CTL?"; /* Undocumented, only one google hit. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010060: return "AMD_K8_BIST_RESULT"; /* BDKG says it as introduced with revision F. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010073: return "AMD_10H_C_ST_IO_BASE_ADDR";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync // case 0xc0010075: return "AMD_15H_APML_TDP_LIM";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync // case 0xc0010077: return "AMD_15H_CPU_PWR_IN_TDP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync // case 0xc0010078: return "AMD_15H_PWR_AVG_PERIOD";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync // case 0xc0010079: return "AMD_15H_DRAM_CTR_CMD_THR";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync // case 0xc0010080: return "AMD_16H_FSFM_ACT_CNT_0";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync // case 0xc0010081: return "AMD_16H_FSFM_REF_CNT_0";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010114: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_K8_VM_CR" : "AMD_K8_UNK_c001_0114";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010115: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_K8_IGNNE" : "AMD_K8_UNK_c001_0115";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010116: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_K8_SMM_CTL" : "AMD_K8_UNK_c001_0116";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010117: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_K8_VM_HSAVE_PA" : "AMD_K8_UNK_c001_0117";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010118: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AMD_10H_VM_LOCK_KEY" : "AMD_K8_UNK_c001_0118";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010119: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_10H_SSM_LOCK_KEY" : "AMD_K8_UNK_c001_0119";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001011a: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AMD_10H_LOCAL_SMI_STS" : "AMD_K8_UNK_c001_011a";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001020c: return "AMD_K8_PERF_CTL_6";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001020e: return "AMD_K8_PERF_CTL_7";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001020d: return "AMD_K8_PERF_CTR_6";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001020f: return "AMD_K8_PERF_CTR_7";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc0010238: return "AMD_16H_L2I_PERF_CTL_4";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001023a: return "AMD_16H_L2I_PERF_CTL_5";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001030c: return "AMD_16H_L2I_PERF_CTL_6";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001023e: return "AMD_16H_L2I_PERF_CTL_7";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc0010239: return "AMD_16H_L2I_PERF_CTR_4";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001023b: return "AMD_16H_L2I_PERF_CTR_5";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001023d: return "AMD_16H_L2I_PERF_CTR_6";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001023f: return "AMD_16H_L2I_PERF_CTR_7";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc0010248: return "AMD_15H_NB_PERF_CTL_4";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001024a: return "AMD_15H_NB_PERF_CTL_5";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001024c: return "AMD_15H_NB_PERF_CTL_6";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001024e: return "AMD_15H_NB_PERF_CTL_7";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc0010249: return "AMD_15H_NB_PERF_CTR_4";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001024b: return "AMD_15H_NB_PERF_CTR_5";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001024d: return "AMD_15H_NB_PERF_CTR_6";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc001024f: return "AMD_15H_NB_PERF_CTR_7";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011001: return "AMD_K7_APIC_CLUSTER_ID"; /* Mentioned in BKDG (r3.00) for fam16h when describing EBL_CR_POWERON. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011002: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD07" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011003: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD06" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011004: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_STD01" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011005: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_CPUID_CTL_EXT01" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001100b: return "AMD_K7_FAST_FLUSH_COUNT?";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001100d: return "AMD_K8_LOGICAL_CPUS_NUM?";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011014: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_RIP?" : "AMD_K7_MOBIL_DEBUG?";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011015: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_RIP_MASK?" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011016: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_COND_HDT_VAL?" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011017: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_COND_HDT_VAL_MASK?" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011018: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_XCPT_BP_CTL?" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011019: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR1_ADDR_MASK" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001101a: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR2_ADDR_MASK" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001101b: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AMD_16H_DR3_ADDR_MASK" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001101d: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_NB_BIST?" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001101e: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_THERMTRIP_2?" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001101f: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AMD_K8_NB_CFG?" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011023: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG" : "AMD_K7_BU_CFG";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011028: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AMD_15H_FP_CFG"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) ? "AMD_10H_UNK_c001_1028"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011029: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AMD_15H_DC_CFG"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) ? "AMD_10H_UNK_c001_1029"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001102a: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG2"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) || g_enmMicroarch > kCpumMicroarch_AMD_15h_End
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001102b: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_CU_CFG3" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001102c: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_EX_CFG" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001102d: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AMD_15H_LS_CFG2" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011031: return "AMD_10H_IBS_FETCH_LIN_ADDR";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011032: return "AMD_10H_IBS_FETCH_PHYS_ADDR";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011039: return "AMD_10H_IBS_DC_PHYS_ADDR";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011070: return "AMD_15H_UNK_c001_1070"; /* coreboot defines this, but with a numerical name. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Bunch of unknown sandy bridge registers. They might seem like the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * nehalem based xeon stuff, but the layout doesn't match. I bet it's the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * same kind of registes though (i.e. uncore (UNC)).
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Kudos to Intel for keeping these a secret! Many thanks guys!!
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_SandyBridge)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000a00: return "I7_SB_UNK_0000_0a00"; case 0x00000a01: return "I7_SB_UNK_0000_0a01";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c00: return "I7_SB_UNK_0000_0c00"; case 0x00000c01: return "I7_SB_UNK_0000_0c01";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c06: return "I7_SB_UNK_0000_0c06"; case 0x00000c08: return "I7_SB_UNK_0000_0c08";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c09: return "I7_SB_UNK_0000_0c09"; case 0x00000c10: return "I7_SB_UNK_0000_0c10";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c11: return "I7_SB_UNK_0000_0c11"; case 0x00000c14: return "I7_SB_UNK_0000_0c14";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c15: return "I7_SB_UNK_0000_0c15"; case 0x00000c16: return "I7_SB_UNK_0000_0c16";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c17: return "I7_SB_UNK_0000_0c17"; case 0x00000c24: return "I7_SB_UNK_0000_0c24";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c30: return "I7_SB_UNK_0000_0c30"; case 0x00000c31: return "I7_SB_UNK_0000_0c31";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c32: return "I7_SB_UNK_0000_0c32"; case 0x00000c33: return "I7_SB_UNK_0000_0c33";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c34: return "I7_SB_UNK_0000_0c34"; case 0x00000c35: return "I7_SB_UNK_0000_0c35";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c36: return "I7_SB_UNK_0000_0c36"; case 0x00000c37: return "I7_SB_UNK_0000_0c37";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c38: return "I7_SB_UNK_0000_0c38"; case 0x00000c39: return "I7_SB_UNK_0000_0c39";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d10: return "I7_SB_UNK_0000_0d10"; case 0x00000d11: return "I7_SB_UNK_0000_0d11";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d12: return "I7_SB_UNK_0000_0d12"; case 0x00000d13: return "I7_SB_UNK_0000_0d13";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d14: return "I7_SB_UNK_0000_0d14"; case 0x00000d15: return "I7_SB_UNK_0000_0d15";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d16: return "I7_SB_UNK_0000_0d16"; case 0x00000d17: return "I7_SB_UNK_0000_0d17";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d18: return "I7_SB_UNK_0000_0d18"; case 0x00000d19: return "I7_SB_UNK_0000_0d19";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d30: return "I7_SB_UNK_0000_0d30"; case 0x00000d31: return "I7_SB_UNK_0000_0d31";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d32: return "I7_SB_UNK_0000_0d32"; case 0x00000d33: return "I7_SB_UNK_0000_0d33";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d34: return "I7_SB_UNK_0000_0d34"; case 0x00000d35: return "I7_SB_UNK_0000_0d35";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d36: return "I7_SB_UNK_0000_0d36"; case 0x00000d37: return "I7_SB_UNK_0000_0d37";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d38: return "I7_SB_UNK_0000_0d38"; case 0x00000d39: return "I7_SB_UNK_0000_0d39";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d50: return "I7_SB_UNK_0000_0d50"; case 0x00000d51: return "I7_SB_UNK_0000_0d51";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d52: return "I7_SB_UNK_0000_0d52"; case 0x00000d53: return "I7_SB_UNK_0000_0d53";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d54: return "I7_SB_UNK_0000_0d54"; case 0x00000d55: return "I7_SB_UNK_0000_0d55";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d56: return "I7_SB_UNK_0000_0d56"; case 0x00000d57: return "I7_SB_UNK_0000_0d57";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d58: return "I7_SB_UNK_0000_0d58"; case 0x00000d59: return "I7_SB_UNK_0000_0d59";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d70: return "I7_SB_UNK_0000_0d70"; case 0x00000d71: return "I7_SB_UNK_0000_0d71";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d72: return "I7_SB_UNK_0000_0d72"; case 0x00000d73: return "I7_SB_UNK_0000_0d73";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d74: return "I7_SB_UNK_0000_0d74"; case 0x00000d75: return "I7_SB_UNK_0000_0d75";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d76: return "I7_SB_UNK_0000_0d76"; case 0x00000d77: return "I7_SB_UNK_0000_0d77";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d78: return "I7_SB_UNK_0000_0d78"; case 0x00000d79: return "I7_SB_UNK_0000_0d79";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d90: return "I7_SB_UNK_0000_0d90"; case 0x00000d91: return "I7_SB_UNK_0000_0d91";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d92: return "I7_SB_UNK_0000_0d92"; case 0x00000d93: return "I7_SB_UNK_0000_0d93";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d94: return "I7_SB_UNK_0000_0d94"; case 0x00000d95: return "I7_SB_UNK_0000_0d95";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d96: return "I7_SB_UNK_0000_0d96"; case 0x00000d97: return "I7_SB_UNK_0000_0d97";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000d98: return "I7_SB_UNK_0000_0d98"; case 0x00000d99: return "I7_SB_UNK_0000_0d99";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000db0: return "I7_SB_UNK_0000_0db0"; case 0x00000db1: return "I7_SB_UNK_0000_0db1";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000db2: return "I7_SB_UNK_0000_0db2"; case 0x00000db3: return "I7_SB_UNK_0000_0db3";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000db4: return "I7_SB_UNK_0000_0db4"; case 0x00000db5: return "I7_SB_UNK_0000_0db5";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000db6: return "I7_SB_UNK_0000_0db6"; case 0x00000db7: return "I7_SB_UNK_0000_0db7";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000db8: return "I7_SB_UNK_0000_0db8"; case 0x00000db9: return "I7_SB_UNK_0000_0db9";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Ditto for ivy bridge (observed on the i5-3570). There are some haswell
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * and sandybridge related docs on registers in this ares, but either
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * things are different for ivy or they're very incomplete. Again, kudos
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * to intel!
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (g_enmMicroarch == kCpumMicroarch_Intel_Core7_IvyBridge)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000700: return "I7_IB_UNK_0000_0700"; case 0x00000701: return "I7_IB_UNK_0000_0701";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000702: return "I7_IB_UNK_0000_0702"; case 0x00000703: return "I7_IB_UNK_0000_0703";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000704: return "I7_IB_UNK_0000_0704"; case 0x00000705: return "I7_IB_UNK_0000_0705";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000706: return "I7_IB_UNK_0000_0706"; case 0x00000707: return "I7_IB_UNK_0000_0707";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000708: return "I7_IB_UNK_0000_0708"; case 0x00000709: return "I7_IB_UNK_0000_0709";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000710: return "I7_IB_UNK_0000_0710"; case 0x00000711: return "I7_IB_UNK_0000_0711";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000712: return "I7_IB_UNK_0000_0712"; case 0x00000713: return "I7_IB_UNK_0000_0713";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000714: return "I7_IB_UNK_0000_0714"; case 0x00000715: return "I7_IB_UNK_0000_0715";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000716: return "I7_IB_UNK_0000_0716"; case 0x00000717: return "I7_IB_UNK_0000_0717";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000718: return "I7_IB_UNK_0000_0718"; case 0x00000719: return "I7_IB_UNK_0000_0719";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000720: return "I7_IB_UNK_0000_0720"; case 0x00000721: return "I7_IB_UNK_0000_0721";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000722: return "I7_IB_UNK_0000_0722"; case 0x00000723: return "I7_IB_UNK_0000_0723";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000724: return "I7_IB_UNK_0000_0724"; case 0x00000725: return "I7_IB_UNK_0000_0725";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000726: return "I7_IB_UNK_0000_0726"; case 0x00000727: return "I7_IB_UNK_0000_0727";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000728: return "I7_IB_UNK_0000_0728"; case 0x00000729: return "I7_IB_UNK_0000_0729";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000730: return "I7_IB_UNK_0000_0730"; case 0x00000731: return "I7_IB_UNK_0000_0731";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000732: return "I7_IB_UNK_0000_0732"; case 0x00000733: return "I7_IB_UNK_0000_0733";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000734: return "I7_IB_UNK_0000_0734"; case 0x00000735: return "I7_IB_UNK_0000_0735";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000736: return "I7_IB_UNK_0000_0736"; case 0x00000737: return "I7_IB_UNK_0000_0737";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000738: return "I7_IB_UNK_0000_0738"; case 0x00000739: return "I7_IB_UNK_0000_0739";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000740: return "I7_IB_UNK_0000_0740"; case 0x00000741: return "I7_IB_UNK_0000_0741";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000742: return "I7_IB_UNK_0000_0742"; case 0x00000743: return "I7_IB_UNK_0000_0743";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000744: return "I7_IB_UNK_0000_0744"; case 0x00000745: return "I7_IB_UNK_0000_0745";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000746: return "I7_IB_UNK_0000_0746"; case 0x00000747: return "I7_IB_UNK_0000_0747";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000748: return "I7_IB_UNK_0000_0748"; case 0x00000749: return "I7_IB_UNK_0000_0749";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Gets the name of an MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * This may return a static buffer, so the content should only be considered
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * valid until the next time this function is called!.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns MSR name.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR in question.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * This MSR needs looking into, return a TODO_XXXX_XXXX name.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTStrPrintf(s_szBuf, sizeof(s_szBuf), "TODO_%04x_%04x", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Gets the name of an MSR range.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * This may return a static buffer, so the content should only be considered
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * valid until the next time this function is called!.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns MSR name.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The first MSR in the range.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000040:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah ? "MSR_LASTBRANCH_n_FROM_IP" : "MSR_LASTBRANCH_n";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000060:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "MSR_LASTBRANCH_n_TO_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003f8:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003f9:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003fa:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "I7_MSR_PKG_Cn_RESIDENCY";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003fc:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003fd:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003fe:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "I7_MSR_CORE_Cn_RESIDENCY";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000400:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "IA32_MCi_CTL_STATUS_ADDR_MISC";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000680:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "MSR_LASTBRANCH_n_FROM_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000006c0:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "MSR_LASTBRANCH_n_TO_IP";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000800: case 0x00000801: case 0x00000802: case 0x00000803:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000804: case 0x00000805: case 0x00000806: case 0x00000807:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000808: case 0x00000809: case 0x0000080a: case 0x0000080b:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000080c: case 0x0000080d: case 0x0000080e: case 0x0000080f:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "IA32_X2APIC_n";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Replace the last char with 'n'.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * This MSR needs looking into, return a TODO_XXXX_XXXX_n name.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTStrPrintf(s_szBuf, sizeof(s_szBuf), "TODO_%04x_%04x_n", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Returns the function name for MSRs that have one or two.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns Function name if applicable, NULL if not.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR in question.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pfTakesValue Whether this MSR function takes a value or not.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Optional.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic const char *getMsrFnName(uint32_t uMsr, bool *pfTakesValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000006:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (g_enmMicroarch >= kCpumMicroarch_Intel_First && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_First)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return NULL; /* TR4 / cache tag on Pentium, but that's for later. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "Ia32MonitorFilterLineSize";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000002a: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcHardPowerOn" : "IntelEblCrPowerOn";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000002b: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcSoftPowerOn" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000002c: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcFrequencyId" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x00000033: return "IntelTestCtl";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000040:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000041:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000042:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000043:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000044:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000045:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000046:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000047:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "IntelLastBranchFromToN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000008b: return g_enmVendor == CPUMCPUVENDOR_AMD ? "AmdK8PatchLevel" : "Ia32BiosSignId";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000a8:
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000000a9:
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000000aa:
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000000ab:
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000000ac:
11923fc977be1686f5428c3e790c04d0701a074cvboxsync case 0x000000ad:
11923fc977be1686f5428c3e790c04d0701a074cvboxsync return "IntelCore2EmttmCrTablesN";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000000c1:
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000000c2:
11923fc977be1686f5428c3e790c04d0701a074cvboxsync case 0x000000c3:
11923fc977be1686f5428c3e790c04d0701a074cvboxsync case 0x000000c4:
11923fc977be1686f5428c3e790c04d0701a074cvboxsync return "Ia32PmcN";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000000c5:
11923fc977be1686f5428c3e790c04d0701a074cvboxsync case 0x000000c6:
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000000c7:
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000000c8:
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync if (g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First)
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync return "Ia32PmcN";
11923fc977be1686f5428c3e790c04d0701a074cvboxsync case 0x000000e2: return "IntelPkgCStConfigControl";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000000e3: return "IntelCore2SmmCStMiscInfo";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000000fe: *pfTakesValue = true; return "Ia32MtrrCap";
11923fc977be1686f5428c3e790c04d0701a074cvboxsync case 0x00000119: *pfTakesValue = true; return "IntelBblCrCtl";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x0000011e: *pfTakesValue = true; return "IntelBblCrCtl3";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000130: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x00000131: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x00000132: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
11923fc977be1686f5428c3e790c04d0701a074cvboxsync case 0x00000133: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x00000134: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
11923fc977be1686f5428c3e790c04d0701a074cvboxsync case 0x00000179: *pfTakesValue = true; return "Ia32McgCap";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x0000017f: return "IntelI7SandyErrorControl"; /* SandyBridge. */
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x00000193: return /*g_fIntelNetBurst ? NULL :*/ NULL /* Core2_Penryn. */;
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x00000198: *pfTakesValue = true; return "Ia32PerfStatus";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x00000199: *pfTakesValue = true; return "Ia32PerfCtl";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x0000019a: *pfTakesValue = true; return "Ia32ClockModulation";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x0000019b: *pfTakesValue = true; return "Ia32ThermInterrupt";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x0000019c: *pfTakesValue = true; return "Ia32ThermStatus";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x0000019d: *pfTakesValue = true; return "Ia32Therm2Ctl";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001a0: *pfTakesValue = true; return "Ia32MiscEnable";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001a2: *pfTakesValue = true; return "IntelI7TemperatureTarget";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001a6: return "IntelI7MsrOffCoreResponseN";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001a7: return "IntelI7MsrOffCoreResponseN";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001aa: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "IntelI7MiscPwrMgmt" : NULL /*"P6PicSensCfg"*/;
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001ad: *pfTakesValue = true; return "IntelI7TurboRatioLimit"; /* SandyBridge+, Silvermount+ */
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001c8: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Nehalem ? "IntelI7LbrSelect" : NULL;
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001c9: return g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync && g_enmMicroarch <= kCpumMicroarch_Intel_P6_Core_Atom_End
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync ? "IntelLastBranchTos" : NULL /* Pentium M Dothan seems to have something else here. */;
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001d7: return g_fIntelNetBurst ? "P6LastIntFromIp" : NULL;
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001d8: return g_fIntelNetBurst ? "P6LastIntToIp" : NULL;
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001da: return g_fIntelNetBurst ? "IntelLastBranchTos" : NULL;
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001db: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastBranchFromIp";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001dc: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastBranchToIp";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001dd: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastIntFromIp";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001de: return g_fIntelNetBurst ? "IntelLastBranchFromToN" : "P6LastIntToIp";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x000001f0: return "IntelI7VirtualLegacyWireCap"; /* SandyBridge. */
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x00000200: case 0x00000202: case 0x00000204: case 0x00000206:
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x00000208: case 0x0000020a: case 0x0000020c: case 0x0000020e:
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x00000210: case 0x00000212: case 0x00000214: case 0x00000216:
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x00000218: case 0x0000021a: case 0x0000021c: case 0x0000021e:
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync return "Ia32MtrrPhysBaseN";
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x00000201: case 0x00000203: case 0x00000205: case 0x00000207:
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync case 0x00000209: case 0x0000020b: case 0x0000020d: case 0x0000020f:
11923fc977be1686f5428c3e790c04d0701a074cvboxsync case 0x00000211: case 0x00000213: case 0x00000215: case 0x00000217:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000219: case 0x0000021b: case 0x0000021d: case 0x0000021f:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "Ia32MtrrPhysMaskN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000250:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000268: case 0x00000269: case 0x0000026a: case 0x0000026b:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000026c: case 0x0000026d: case 0x0000026e: case 0x0000026f:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "Ia32MtrrFixed";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000277: *pfTakesValue = true; return "Ia32Pat";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000280: case 0x00000281: case 0x00000282: case 0x00000283:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000284: case 0x00000285: case 0x00000286: case 0x00000287:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000288: case 0x00000289: case 0x0000028a: case 0x0000028b:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000028c: case 0x0000028d: case 0x0000028e: case 0x0000028f:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000290: case 0x00000291: case 0x00000292: case 0x00000293:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000294: case 0x00000295: //case 0x00000296: case 0x00000297:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x00000298: case 0x00000299: case 0x0000029a: case 0x0000029b:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x0000029c: case 0x0000029d: case 0x0000029e: case 0x0000029f:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "Ia32McNCtl2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x00000305: return g_fIntelNetBurst ? TODO : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000309: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000030a: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000030b: return g_fIntelNetBurst ? NULL /** @todo P4 */ : "Ia32FixedCtrN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000345: *pfTakesValue = true; return "Ia32PerfCapabilities";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note! Lots of P4 MSR 0x00000360..0x00000371. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000038e: *pfTakesValue = true; return "Ia32PerfGlobalStatus";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000391: return "IntelI7UncPerfGlobalCtrl"; /* S,H,X */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000392: return "IntelI7UncPerfGlobalStatus"; /* S,H,X */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000393: return "IntelI7UncPerfGlobalOvfCtrl"; /* X. ASSUMING this is the same on sandybridge and later. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000394: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPerfFixedCtr" /* X */ : "IntelI7UncPerfFixedCtrCtrl"; /* >= S,H */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000395: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPerfFixedCtrCtrl" /* X*/ : "IntelI7UncPerfFixedCtr"; /* >= S,H */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000396: return g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncAddrOpcodeMatch" /* X */ : "IntelI7UncCBoxConfig"; /* >= S,H */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Note! Lots of P4 MSR 0x000003a0..0x000003e1. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b0: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfCtrN"; /* >= S,H */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b1: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfCtrN"; /* >= S,H */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b2: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfEvtSelN"; /* >= S,H */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b3: return g_fIntelNetBurst ? NULL : g_enmMicroarch < kCpumMicroarch_Intel_Core7_SandyBridge ? "IntelI7UncPmcN" /* X */ : "IntelI7UncArbPerfEvtSelN"; /* >= S,H */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003b4: case 0x000003b5: case 0x000003b6: case 0x000003b7:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003c0: case 0x000003c1: case 0x000003c2: case 0x000003c3:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003c4: case 0x000003c5: case 0x000003c6: case 0x000003c7:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return g_fIntelNetBurst ? NULL : "IntelI7UncPerfEvtSelN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003f6: return g_fIntelNetBurst ? NULL /*??*/ : "IntelI7PebsLdLat";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000003f8: return g_fIntelNetBurst ? NULL : "IntelI7PkgCnResidencyN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000478: return g_enmMicroarch == kCpumMicroarch_Intel_Core2_Penryn ? "IntelCpuId1FeatureMaskEcdx" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000480: *pfTakesValue = true; return "Ia32VmxBase";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000481: *pfTakesValue = true; return "Ia32VmxPinbasedCtls";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000482: *pfTakesValue = true; return "Ia32VmxProcbasedCtls";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000483: *pfTakesValue = true; return "Ia32VmxExitCtls";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000484: *pfTakesValue = true; return "Ia32VmxEntryCtls";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000485: *pfTakesValue = true; return "Ia32VmxMisc";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000486: *pfTakesValue = true; return "Ia32VmxCr0Fixed0";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000487: *pfTakesValue = true; return "Ia32VmxCr0Fixed1";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000488: *pfTakesValue = true; return "Ia32VmxCr4Fixed0";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000489: *pfTakesValue = true; return "Ia32VmxCr4Fixed1";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000048a: *pfTakesValue = true; return "Ia32VmxVmcsEnum";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000048b: *pfTakesValue = true; return "Ia32VmxProcBasedCtls2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000048c: *pfTakesValue = true; return "Ia32VmxEptVpidCap";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000048d: *pfTakesValue = true; return "Ia32VmxTruePinbasedCtls";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000048e: *pfTakesValue = true; return "Ia32VmxTrueProcbasedCtls";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000048f: *pfTakesValue = true; return "Ia32VmxTrueExitCtls";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000490: *pfTakesValue = true; return "Ia32VmxTrueEntryCtls";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004c1:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004c2:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004c3:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004c4:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004c5:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004c6:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004c7:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000004c8:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "Ia32PmcN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000005a0: return "IntelCore2PeciControl"; /* Core2_Penryn. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000601: return "IntelI7SandyVrCurrentConfig";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000603: return "IntelI7SandyVrMiscConfig";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000606: return "IntelI7SandyRaplPowerUnit";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000060d: return "IntelI7SandyPkgC2Residency";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000610: return "IntelI7RaplPkgPowerLimit";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000611: return "IntelI7RaplPkgEnergyStatus";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000613: return "IntelI7RaplPkgPerfStatus";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000618: return "IntelI7RaplDramPowerLimit";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000619: return "IntelI7RaplDramEnergyStatus";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000061b: return "IntelI7RaplDramPerfStatus";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000061c: return "IntelI7RaplDramPowerInfo";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000638: return "IntelI7RaplPp0PowerLimit";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000639: return "IntelI7RaplPp0EnergyStatus";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000063b: return "IntelI7RaplPp0PerfStatus";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000640: return "IntelI7RaplPp1PowerLimit";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000641: return "IntelI7RaplPp1EnergyStatus";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000648: return "IntelI7IvyConfigTdpNominal";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000649: return "IntelI7IvyConfigTdpLevel1";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000064a: return "IntelI7IvyConfigTdpLevel2";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000064b: return "IntelI7IvyConfigTdpControl";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000064c: return "IntelI7IvyTurboActivationRatio";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000680: case 0x00000681: case 0x00000682: case 0x00000683:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000684: case 0x00000685: case 0x00000686: case 0x00000687:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000688: case 0x00000689: case 0x0000068a: case 0x0000068b:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000068c: case 0x0000068d: case 0x0000068e: case 0x0000068f:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x00000690: case 0x00000691: case 0x00000692: case 0x00000693:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x00000694: case 0x00000695: case 0x00000696: case 0x00000697:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x00000698: case 0x00000699: case 0x0000069a: case 0x0000069b:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x0000069c: case 0x0000069d: case 0x0000069e: case 0x0000069f:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "IntelLastBranchFromN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000006c0: case 0x000006c1: case 0x000006c2: case 0x000006c3:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000006c4: case 0x000006c5: case 0x000006c6: case 0x000006c7:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000006c8: case 0x000006c9: case 0x000006ca: case 0x000006cb:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000006cc: case 0x000006cd: case 0x000006ce: case 0x000006cf:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x000006d0: case 0x000006d1: case 0x000006d2: case 0x000006d3:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x000006d4: case 0x000006d5: case 0x000006d6: case 0x000006d7:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x000006d8: case 0x000006d9: case 0x000006da: case 0x000006db:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x000006dc: case 0x000006dd: case 0x000006de: case 0x000006df:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "IntelLastBranchToN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000006e0: return "Ia32TscDeadline"; /** @todo detect this correctly! */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000c80: return g_enmMicroarch > kCpumMicroarch_Intel_Core7_Nehalem ? "Ia32DebugInterface" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010010: *pfTakesValue = true; return "AmdK8SysCfg";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010016: case 0xc0010018: return "AmdK8IorrBaseN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010017: case 0xc0010019: return "AmdK8IorrMaskN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001001a: case 0xc001001d: return "AmdK8TopOfMemN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "AmdK8CpuNameN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001003e: *pfTakesValue = true; return "AmdK8HwThermalCtrl";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010041: *pfTakesValue = true; return "AmdK8FidVidControl";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010042: *pfTakesValue = true; return "AmdK8FidVidStatus";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010044: case 0xc0010045: case 0xc0010046: case 0xc0010047:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010048: case 0xc0010049: case 0xc001004a: //case 0xc001004b:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "AmdK8McCtlMaskN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010050: case 0xc0010051: case 0xc0010052: case 0xc0010053:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "AmdK8SmiOnIoTrapN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010058: return "AmdFam10hMmioCfgBaseAddr";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010061: *pfTakesValue = true; return "AmdFam10hPStateCurLimit";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010062: *pfTakesValue = true; return "AmdFam10hPStateControl";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010063: *pfTakesValue = true; return "AmdFam10hPStateStatus";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010064: case 0xc0010065: case 0xc0010066: case 0xc0010067:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010068: case 0xc0010069: case 0xc001006a: case 0xc001006b:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010070: *pfTakesValue = true; return "AmdFam10hCofVidControl";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010071: *pfTakesValue = true; return "AmdFam10hCofVidStatus";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010073: return "AmdFam10hCStateIoBaseAddr";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010074: return "AmdFam10hCpuWatchdogTimer";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync // case 0xc0010075: return "AmdFam15hApmlTdpLimit";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync // case 0xc0010077: return "AmdFam15hCpuPowerInTdp";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync // case 0xc0010078: return "AmdFam15hPowerAveragingPeriod";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync // case 0xc0010079: return "AmdFam15hDramCtrlCmdThrottle";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync // case 0xc0010080: return "AmdFam16hFreqSensFeedbackMonActCnt0";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync // case 0xc0010081: return "AmdFam16hFreqSensFeedbackMonRefCnt0";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010111: return "AmdK8SmmBase"; /** @todo probably misdetected ign/gp due to locking */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010112: return "AmdK8SmmAddr"; /** @todo probably misdetected ign/gp due to locking */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010113: return "AmdK8SmmMask"; /** @todo probably misdetected ign/gp due to locking */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010114: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdK8VmCr" : NULL; /** @todo probably misdetected due to locking */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010115: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdK8IgnNe" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010116: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdK8SmmCtl" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010117: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdK8VmHSavePa" : NULL; /** @todo probably misdetected due to locking */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010118: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm_AMDV ? "AmdFam10hVmLockKey" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010119: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdFam10hSmmLockKey" : NULL; /* Not documented by BKDG, found in netbsd patch. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001011a: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_90nm ? "AmdFam10hLocalSmiStatus" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010140: *pfTakesValue = true; return "AmdFam10hOsVisWrkIdLength";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010141: *pfTakesValue = true; return "AmdFam10hOsVisWrkStatus";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010200: case 0xc0010202: case 0xc0010204: case 0xc0010206:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010208: case 0xc001020a: //case 0xc001020c: case 0xc001020e:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "AmdK8PerfCtlN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010201: case 0xc0010203: case 0xc0010205: case 0xc0010207:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010209: case 0xc001020b: //case 0xc001020d: case 0xc001020f:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "AmdK8PerfCtrN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010230: case 0xc0010232: case 0xc0010234: case 0xc0010236:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc0010238: case 0xc001023a: case 0xc001030c: case 0xc001023e:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "AmdFam16hL2IPerfCtlN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010231: case 0xc0010233: case 0xc0010235: case 0xc0010237:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc0010239: case 0xc001023b: case 0xc001023d: case 0xc001023f:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "AmdFam16hL2IPerfCtrN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010240: case 0xc0010242: case 0xc0010244: case 0xc0010246:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc0010248: case 0xc001024a: case 0xc001024c: case 0xc001024e:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "AmdFam15hNorthbridgePerfCtlN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010241: case 0xc0010243: case 0xc0010245: case 0xc0010247:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0xc0010249: case 0xc001024b: case 0xc001024d: case 0xc001024f:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "AmdFam15hNorthbridgePerfCtrN";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011000: *pfTakesValue = true; return "AmdK7MicrocodeCtl";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011001: *pfTakesValue = true; return "AmdK7ClusterIdMaybe";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011002: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd07hEbax" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011003: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd06hEcx" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011004: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlStd01hEdcx" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011005: return g_enmMicroarch >= kCpumMicroarch_AMD_K8_First ? "AmdK8CpuIdCtlExt01hEdcx" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001100a: return "AmdK7HardwareDebugToolCfgMaybe";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001100b: return "AmdK7FastFlushCountMaybe";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001100c: return "AmdK7NodeId"; /** @todo dunno if this was there is K7 already. Kinda doubt it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011019: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001101a: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001101b: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver ? "AmdK7DrXAddrMaskN" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011023: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg" : "AmdK7BusUnitCfg";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011028: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AmdFam15hFpuCfg" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011029: return g_enmMicroarch >= kCpumMicroarch_AMD_15h_First ? "AmdFam15hDecoderCfg" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001102a: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg2"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync : CPUMMICROARCH_IS_AMD_FAM_10H(g_enmMicroarch) || g_enmMicroarch > kCpumMicroarch_AMD_15h_End
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001102b: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hCombUnitCfg3" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001102c: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hExecUnitCfg" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001102d: return CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch) ? "AmdFam15hLoadStoreCfg2" : NULL;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011031: return "AmdFam10hIbsFetchLinAddr";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011032: return "AmdFam10hIbsFetchPhysAddr";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Names CPUMCPU variables that MSRs corresponds to.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns The variable name @a uMsr corresponds to, NULL if no variable.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR in question.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic const char *getMsrCpumCpuVarName(uint32_t uMsr)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000250: return "GuestMsrs.msr.MtrrFix64K_00000";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000258: return "GuestMsrs.msr.MtrrFix16K_80000";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000259: return "GuestMsrs.msr.MtrrFix16K_A0000";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000268: return "GuestMsrs.msr.MtrrFix4K_C0000";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000269: return "GuestMsrs.msr.MtrrFix4K_C8000";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000026a: return "GuestMsrs.msr.MtrrFix4K_D0000";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000026b: return "GuestMsrs.msr.MtrrFix4K_D8000";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000026c: return "GuestMsrs.msr.MtrrFix4K_E0000";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000026d: return "GuestMsrs.msr.MtrrFix4K_E8000";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000026e: return "GuestMsrs.msr.MtrrFix4K_F0000";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000026f: return "GuestMsrs.msr.MtrrFix4K_F8000";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000002ff: return "GuestMsrs.msr.MtrrDefType";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Checks whether the MSR should read as zero for some reason.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns true if the register should read as zero, false if not.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000088: return true; // "BBL_CR_D0" - RAZ until understood/needed.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000089: return true; // "BBL_CR_D1" - RAZ until understood/needed.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000008a: return true; // "BBL_CR_D2" - RAZ until understood/needed.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Non-zero, but unknown register. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000004a:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000004b:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000004c:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000004d:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000004e:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000004f:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000050:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000051:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000052:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000053:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000054:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000008c:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000008d:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000008e:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000008f:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000090:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011011:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return true;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Gets the skip mask for the given MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns Skip mask (0 means skipping nothing).
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000013c: return 3; /* AES-NI lock bit ++. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001f2: return UINT64_C(0xfffff00f); /* Ia32SmrrPhysBase - Only writable in SMM. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000001f3: return UINT64_C(0xfffff800); /* Ia32SmrrPhysMask - Only writable in SMM. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* these two have lock bits. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* SmmLock effect: */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010112: return UINT64_C(0xfffe0000) | ((RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(uint64_t)UINT32_MAX);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010113: return UINT64_C(0xfffe773f) | ((RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(uint64_t)UINT32_MAX);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010114: return RT_BIT_64(3) /* SVM lock */ | RT_BIT_64(4) /* SvmeDisable */;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Canonical */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011034:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011038:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001103b:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000060: case 0x00000061: case 0x00000062: case 0x00000063:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000064: case 0x00000065: case 0x00000066: case 0x00000067:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000040: case 0x00000041: case 0x00000042: case 0x00000043:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000044: case 0x00000045: case 0x00000046: case 0x00000047:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000600:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (g_enmMicroarch >= kCpumMicroarch_Intel_Core2_First)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Write only bits. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010041: return RT_BIT_64(16); /* FIDVID_CTL.InitFidVid */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Time counters - fudge them to avoid incorrect ignore masks. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000010:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000e7:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000e8:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** queryMsrWriteBadness return values. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsynctypedef enum
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** Not a problem if accessed with care. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** Worse than a bad james bond villain. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Backlisting and graylisting of MSRs which may cause tripple faults.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns Badness factor.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR in question.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic VBCPUREPBADNESS queryMsrWriteBadness(uint32_t uMsr)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo Having trouble in the 0xc0010247,0xc0011006,?? region on Bulldozer. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** @todo Having trouble in the 0xc001100f,0xc001100d,?? region on Opteron
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000050:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000051:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000052:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000053:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000054:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00001006:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00001007:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000120e:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00001233:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00001239:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00001249:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000124a:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00001404:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00001405:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00001413:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000142c: /* Caused rip to be set to 297 or some such weirdness... */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000142e:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00001435:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00001436:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00001438:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000317f:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010010:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010016:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010017:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010018:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010019:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001001a:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001001d:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010064: /* P-state fequency, voltage, ++. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010065: /* P-state fequency, voltage, ++. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010066: /* P-state fequency, voltage, ++. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010067: /* P-state fequency, voltage, ++. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010068: /* P-state fequency, voltage, ++. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0010069: /* P-state fequency, voltage, ++. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001006a: /* P-state fequency, voltage, ++. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001006b: /* P-state fequency, voltage, ++. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001101e:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011021: /* IC_CFG (instruction cache configuration) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011023: /* CU_CFG (combined unit configuration) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc001102c: /* EX_CFG (execution unit configuration) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0011012:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Checks if this might be a VIA dummy register.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns true if it's a dummy, false if it isn't.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param fFlags The flags.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic bool isMsrViaDummy(uint32_t uMsr, uint64_t uValue, uint32_t fFlags)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000010:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000001b:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000c1:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x000000c2:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x0000011e:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000186:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0x00000187:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //case 0x00000200 ... (mtrrs will be detected)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0000080:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0000081:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0000082:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync case 0xc0000083:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (uMsr >= 0x00001200 && uMsr <= 0x00003fff && queryMsrWriteBadness(uMsr) != VBCPUREPBADNESS_MOSTLY_HARMLESS)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return true;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Prints a 64-bit value in the best way.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Prints the newline after an MSR line has been printed.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * This is used as a hook to slow down the output and make sure the remote
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * terminal or/and output file has received the last update before we go and
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * crash probing the next MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic void printMsrNewLine(void)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrWriteOnly(uint32_t uMsr, const char *pszWrFnName, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ? " MFN(%#010x, \"%s\", WriteOnly, %s), /* %s */"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync : " MFN(%#010x, \"%s\", WriteOnly, %s),",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uMsr, getMsrName(uMsr), pszWrFnName, pszAnnotation);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrValueReadOnly(uint32_t uMsr, uint64_t uValue, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" MVO(%#010x, \"%s\"", uMsr, getMsrName(uMsr));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrValueIgnoreWritesNamed(uint32_t uMsr, uint64_t uValue, const char *pszName, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" MVI(%#010x, \"%s\"", uMsr, pszName);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrValueIgnoreWrites(uint32_t uMsr, uint64_t uValue, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return printMsrValueIgnoreWritesNamed(uMsr, uValue, getMsrName(uMsr), pszAnnotation);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrValueExtended(uint32_t uMsr, uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" MVX(%#010x, \"%s\"", uMsr, getMsrName(uMsr));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrRangeValueReadOnly(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" RVO(%#010x, %#010x, \"%s\"", uMsr, uLast, getMsrRangeName(uMsr));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrRangeValueIgnoreWritesNamed(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszName, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" RVI(%#010x, %#010x, \"%s\"", uMsr, uLast, pszName);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrRangeValueIgnoreWrites(uint32_t uMsr, uint32_t uLast, uint64_t uValue, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return printMsrRangeValueIgnoreWritesNamed(uMsr, uLast, uValue, getMsrRangeName(uMsr), pszAnnotation);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrFunction(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" MFN(%#010x, \"%s\", %s, %s),", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrFunctionReadOnly(uint32_t uMsr, const char *pszRdFnName, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" MFO(%#010x, \"%s\", %s),", uMsr, getMsrName(uMsr), pszRdFnName);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrFunctionIgnoreWrites(uint32_t uMsr, const char *pszRdFnName, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" MFI(%#010x, \"%s\", %s),", uMsr, getMsrName(uMsr), pszRdFnName);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrFunctionIgnoreMask(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" MFW(%#010x, \"%s\", %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrFunctionExtended(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, uint64_t uValue,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" MFX(%#010x, \"%s\", %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrFunctionExtendedIdxVal(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName, uint64_t uValue,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" MFX(%#010x, \"%s\", %s, %s, %#x", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, uValue);
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsyncstatic int printMsrFunctionCpumCpu(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName,
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync const char *pszCpumCpuStorage, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_NOT_FOUND, "Missing CPUMCPU member for %#s (%#x)\n", getMsrName(uMsr), uMsr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" MFS(%#010x, \"%s\", %s, %s, %s),", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, pszCpumCpuStorage);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrFunctionCpumCpuEx(uint32_t uMsr, const char *pszRdFnName, const char *pszWrFnName,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync const char *pszCpumCpuStorage, uint64_t fIgnMask, uint64_t fGpMask,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_NOT_FOUND, "Missing CPUMCPU member for %#s (%#x)\n", getMsrName(uMsr), uMsr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" MFZ(%#010x, \"%s\", %s, %s, %s", uMsr, getMsrName(uMsr), pszRdFnName, pszWrFnName, pszCpumCpuStorage);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrRangeFunction(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" RFN(%#010x, %#010x, \"%s\", %s, %s),", uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrRangeFunctionEx(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" RSN(%#010x, %#010x, \"%s\", %s, %s", uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrRangeFunctionExIdxVal(uint32_t uMsr, uint32_t uLast, const char *pszRdFnName, const char *pszWrFnName,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint64_t uValue, uint64_t fIgnMask, uint64_t fGpMask, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" RSN(%#010x, %#010x, \"%s\", %s, %s, %#x",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uMsr, uLast, getMsrRangeName(uMsr), pszRdFnName, pszWrFnName, uValue);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int printMsrAlias(uint32_t uMsr, uint32_t uTarget, const char *pszAnnotation)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" MAL(%#010x, \"%s\", %#010x),", uMsr, getMsrName(uMsr), uTarget);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTStrPrintf(s_szBuf, sizeof(s_szBuf), "value=%#llx", uValue);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTStrPrintf(s_szBuf, sizeof(s_szBuf), "value=%#x`%08x", RT_HI_U32(uValue), RT_LO_U32(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic const char *annotateValueExtra(const char *pszExtra, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTStrPrintf(s_szBuf, sizeof(s_szBuf), "%s value=%#llx", pszExtra, uValue);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTStrPrintf(s_szBuf, sizeof(s_szBuf), "%s value=%#x`%08x", pszExtra, RT_HI_U32(uValue), RT_LO_U32(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic const char *annotateIfMissingBits(uint64_t uValue, uint64_t fBits)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTStrPrintf(s_szBuf, sizeof(s_szBuf), "XXX: Unexpected value %#llx - wanted bits %#llx to be set.", uValue, fBits);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_Generic(uint32_t uMsr, uint32_t fFlags, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync bool fTakesValue = false;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync const char *pszFnName = getMsrFnName(uMsr, &fTakesValue);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* This is what we're here for... */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (fGpMask == 0 && fIgnMask == UINT64_MAX && !fTakesValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunctionIgnoreWrites(uMsr, pszFnName, annotateValue(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (fGpMask == 0 && fIgnMask == 0 && (!fTakesValue || uValue == 0))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValue(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, fTakesValue ? uValue : 0,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrValueIgnoreWrites(uMsr, fReadAsZero ? 0 : uValue, fReadAsZero ? annotateValue(uValue) : NULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrValueExtended(uMsr, fReadAsZero ? 0 : uValue, fIgnMask, fGpMask,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Most likely read-only. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunctionReadOnly(uMsr, pszFnName, annotateValue(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunctionExtended(uMsr, pszFnName, "ReadOnly", uValue, 0, 0, annotateValue(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrValueReadOnly(uMsr, 0, annotateValue(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* These should have special handling, so just do a simple
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync write back same value check to see if it's writable. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValueExtra("Might bite.", uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, uValue, 0, 0,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrValueIgnoreWrites(uMsr, 0, annotateValueExtra("Might bite.", uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrValueIgnoreWrites(uMsr, uValue, "Might bite.");
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunctionReadOnly(uMsr, pszFnName, annotateValueExtra("Might bite.", uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunctionExtended(uMsr, pszFnName, "ReadOnly", uValue, 0, UINT64_MAX,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrValueReadOnly(uMsr, 0, annotateValueExtra("Might bite.", uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrValueReadOnly(uMsr, uValue, "Might bite.");
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Don't try anything with these guys. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunction(uMsr, pszFnName, pszFnName, annotateValueExtra("Villain?", uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunctionExtended(uMsr, pszFnName, pszFnName, uValue, 0, 0,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrValueIgnoreWrites(uMsr, 0, annotateValueExtra("Villain?", uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrValueIgnoreWrites(uMsr, uValue, "Villain?");
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_GenRangeFunctionEx(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, const char *pszRdWrFnName,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint32_t uMsrBase, bool fEarlyEndOk, bool fNoIgnMask, uint64_t fSkipMask, uint32_t *pidxLoop)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Resolve default function name. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_INVALID_PARAMETER, "uMsr=%#x no function name\n", uMsr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Figure the possible register count. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Probe the first register and check that the others exhibit
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync the same characteristics. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = msrProberModifyBasicTests(uMsr, fSkipMask, &fReadOnly0, &fIgnMask0, &fGpMask0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = msrProberModifyBasicTests(paMsrs[i].uMsr, fSkipMask, &fReadOnlyN, &fIgnMaskN, &fGpMaskN);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (!fEarlyEndOk && !isMsrViaDummy(uMsr, paMsrs[i].uValue, paMsrs[i].fFlags))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("MSR %s (%#x) range ended unexpectedly early on %#x: ro=%d ign=%#llx/%#llx gp=%#llx/%#llx [N/0]\n",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fReadOnlyN, fReadOnly0, fIgnMaskN, fIgnMask0, fGpMaskN, fGpMask0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pszAnnotation = "XXX: The range ended earlier than expected!";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Report the range (or single MSR as it might be).
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && (fGpMask0 == 0 || (fGpMask0 == UINT64_MAX && fReadOnly0))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return printMsrFunctionExtendedIdxVal(uMsr, pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync pszAnnotation ? pszAnnotation : annotateValue(paMsrs[0].uValue));
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync return printMsrRangeFunction(uMsr, uMsr + cRegs - 1,
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName, pszAnnotation);
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync return printMsrRangeFunctionExIdxVal(uMsr, uMsr + cRegs - 1, pszRdWrFnName, fReadOnly0 ? "ReadOnly" : pszRdWrFnName,
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync iRange /*uValue*/, fIgnMask0, fGpMask0, pszAnnotation);
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsyncstatic int reportMsr_GenRangeFunction(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, const char *pszRdWrFnName,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return reportMsr_GenRangeFunctionEx(paMsrs, cMsrs, cMax, pszRdWrFnName, paMsrs[0].uMsr, false /*fEarlyEndOk*/, false /*fNoIgnMask*/,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Generic report for an MSR implemented by functions, extended version.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pszRdWrFnName The read/write function name, optional.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The MSR range value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param fSkipMask Mask of bits to skip.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param fNoGpMask Mask of bits to remove from the GP mask after
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pszAnnotate Annotation.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_GenFunctionEx(uint32_t uMsr, const char *pszRdWrFnName, uint32_t uValue,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint64_t fSkipMask, uint64_t fNoGpMask, const char *pszAnnotate)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Resolve default function name. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_INVALID_PARAMETER, "uMsr=%#x no function name\n", uMsr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Probe the register and report. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (fGpMask == UINT64_MAX && uValue == 0 && !msrProberModifyZero(uMsr))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunctionReadOnly(uMsr, pszRdWrFnName, pszAnnotate);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (fIgnMask == UINT64_MAX && fGpMask == 0 && uValue == 0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunctionIgnoreWrites(uMsr, pszRdWrFnName, pszAnnotate);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (fIgnMask != 0 && fGpMask == 0 && uValue == 0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunctionIgnoreMask(uMsr, pszRdWrFnName, NULL, fIgnMask, pszAnnotate);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (fIgnMask == 0 && fGpMask == 0 && uValue == 0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunction(uMsr, pszRdWrFnName, NULL, pszAnnotate);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunctionExtended(uMsr, pszRdWrFnName, NULL, uValue, fIgnMask, fGpMask, pszAnnotate);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Reports a VIA dummy range.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param paMsrs Pointer to the first MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param cMsrs The number of MSRs in the array @a paMsr.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pidxLoop Index variable that should be advanced to the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * last MSR entry in the range.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_ViaDummyRange(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Figure how many. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && isMsrViaDummy(paMsrs[cRegs].uMsr, paMsrs[cRegs].uValue, paMsrs[cRegs].fFlags))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("VIA dummy detection %#llx..%#llx (%#x regs)...\n", uMsr, uMsr + cRegs - 1, cRegs);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Advance. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Report it/them. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTStrPrintf(szName, sizeof(szName), "ZERO_%04x_%04x", RT_HI_U16(uMsr), RT_LO_U16(uMsr));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return printMsrValueIgnoreWritesNamed(uMsr, 0, szName, NULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTStrPrintf(szName, sizeof(szName), "ZERO_%04x_%04x_THRU_%04x_%04x",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RT_HI_U16(uMsr), RT_LO_U16(uMsr), RT_HI_U16(uMsrLast), RT_LO_U16(uMsrLast));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return printMsrRangeValueIgnoreWritesNamed(uMsr, uMsrLast, 0, szName, NULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Special function for reporting the IA32_APIC_BASE register, as it seems to be
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * causing trouble on newer systems.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR number.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_Ia32ApicBase(uint32_t uMsr, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Trouble with the generic treatment of both the "APIC Global Enable" and
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "Enable x2APIC mode" bits on an i7-3820QM running OS X 10.8.5. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return reportMsr_GenFunctionEx(uMsr, "Ia32ApicBase", uValue, fSkipMask, 0, NULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Special function for reporting the IA32_MISC_ENABLE register, as it seems to
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * be causing trouble on newer systems.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR number.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_Ia32MiscEnable(uint32_t uMsr, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ( ( g_enmMicroarch >= kCpumMicroarch_Intel_Core7_Broadwell
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && g_enmMicroarch <= kCpumMicroarch_Intel_Core7_End)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || ( g_enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && g_enmMicroarch <= kCpumMicroarch_Intel_Atom_End)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf("WARNING: IA32_MISC_ENABLE probing needs hacking on this CPU!\n");
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* The no execute related flag is deadly if clear. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, fSkipMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunctionExtended(uMsr, "Ia32MiscEnable", "Ia32MiscEnable", uValue,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Verifies that MTRR type field works correctly in the given MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code (failure if bad MSR behavior).
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param iBit The first bit of the type field (8-bit wide).
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param cExpected The number of types expected - PAT=8, MTRR=7.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int msrVerifyMtrrTypeGPs(uint32_t uMsr, uint32_t iBit, uint32_t cExpected)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync bool fGp = !msrProberModifySimpleGp(uMsr, ~(UINT64_C(0xff) << iBit), (uint64_t)uEndTypes << iBit);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR types %u does not cause a GP as it should. (msr %#x)\n",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR types detected to be %#x (msr %#x). Expected %#x.\n",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals with the variable MTRR MSRs.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param paMsrs Pointer to the first variable MTRR MSR (200h).
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param cMsrs The number of MSRs in the array @a paMsr.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pidxLoop Index variable that should be advanced to the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * last MTRR MSR entry.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_Ia32MtrrPhysBaseMaskN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Count them. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync && !isMsrViaDummy(paMsrs[cRegs].uMsr, paMsrs[cRegs].uValue, paMsrs[cRegs].fFlags) )
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR variable MSR range is odd: cRegs=%#x\n", cRegs);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MTRR variable MSR range is too large: cRegs=%#x\n", cRegs);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Find a disabled register that we can play around with. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync for (iGuineaPig = 0; iGuineaPig < cRegs; iGuineaPig += 2)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (!(paMsrs[iGuineaPig + 1].uValue & RT_BIT_32(11)))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("iGuineaPig=%#x -> %#x\n", iGuineaPig, uMsr + iGuineaPig);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Probe the base. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = msrProberModifyBitChanges(uMsr + iGuineaPig, &fIgnBase, &fGpBase, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = msrVerifyMtrrTypeGPs(uMsr + iGuineaPig, 0, 7);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("fIgnBase=%#llx fGpBase=%#llx\n", fIgnBase, fGpBase);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Probing the mask is relatively straight forward. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = msrProberModifyBitChanges(uMsr + iGuineaPig + 1, &fIgnMask, &fGpMask, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("fIgnMask=%#llx fGpMask=%#llx\n", fIgnMask, fGpMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Validate that the whole range subscribes to the apprimately same GP rules. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= RT_BIT_32(11); /* Always skip the enable bit. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("i=%#x fSkipBase=%#llx fSkipMask=%#llx\n", i, fSkipBase, fSkipMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = msrVerifyMtrrTypeGPs(uMsr + iGuineaPig, 0, 7);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = msrProberModifyBitChanges(uMsr + i, &fIgnBaseN, &fGpBaseN, fSkipBase);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "MTRR PHYS BASE register %#x behaves differently from %#x: ign=%#llx/%#llx gp=%#llx/%#llx (fSkipBase=%#llx)\n",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fIgnBaseN, fIgnBase & ~fSkipBase, fGpBaseN, fGpBase & ~fSkipBase, fSkipBase);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = msrProberModifyBitChanges(uMsr + i + 1, &fIgnMaskN, &fGpMaskN, fSkipMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "MTRR PHYS MASK register %#x behaves differently from %#x: ign=%#llx/%#llx gp=%#llx/%#llx (fSkipMask=%#llx)\n",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fIgnMaskN, fIgnMask & ~fSkipMask, fGpMaskN, fGpMask & ~fSkipMask, fSkipMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Print the whole range. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fGpBase &= ~(uint64_t)0x7; /* Valid type bits, see msrVerifyMtrrTypeGPs(). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync printMsrFunctionExtendedIdxVal(uMsr + i, "Ia32MtrrPhysBaseN", NULL, i / 2, fIgnBase, fGpBase,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync printMsrFunctionExtendedIdxVal(uMsr + i + 1, "Ia32MtrrPhysMaskN", NULL, i / 2, fIgnMask, fGpMask,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals with fixed MTRR and PAT MSRs, checking the 8 memory type fields.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_Ia32MtrrFixedOrPat(uint32_t uMsr)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Had a spot of trouble on an old macbook pro with core2 duo T9900 (penryn)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync running 64-bit win81pe. Not giving PAT such a scrutiny fixes it. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Every 8 bytes is a type, check the type ranges one by one. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = msrVerifyMtrrTypeGPs(uMsr, iBit, 7 + (uMsr == 0x00000277));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return printMsrFunctionCpumCpu(uMsr, NULL, NULL, NULL, NULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals with IA32_MTRR_DEF_TYPE.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = msrProberModifyBitChanges(uMsr, &fIgnMask, &fGpMask, 0x7);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return printMsrFunctionCpumCpuEx(uMsr, NULL, NULL, NULL, fIgnMask, fGpMask, NULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals with the Machine Check (MC) MSRs in the 400h+ area.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param paMsrs Pointer to the first MC MSR (400h).
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param cMsrs The number of MSRs in the array @a paMsr.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pidxLoop Index variable that should be advanced to the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * last MC MSR entry.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_Ia32McCtlStatusAddrMiscN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Count them. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || (cRegs & 3) == 2 /* ADDR may or may not be there, depends on STATUS and CPU. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || (cRegs & 3) == 3 /* MISC may or may not be there, depends on STATUS and CPU. */)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_INVALID_PARAMETER, "MC MSR range is odd: cRegs=%#x\n", cRegs);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Just report them. We don't bother probing here as the CTL format
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync and such seems to be a lot of work to test correctly and changes between
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync cpu generations. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return printMsrRangeFunction(uMsr, uMsr + cRegs - 1, "Ia32McCtlStatusAddrMiscN", NULL, NULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals with the X2APIC msrs.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param paMsrs Pointer to the first X2APIC MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param cMsrs The number of MSRs in the array @a paMsr.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pidxLoop Index variable that should be advanced to the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * last X2APIC MSR entry.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_GenX2Apic(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Advance. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Just emit an X2APIC range. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return printMsrRangeFunction(0x800, 0x8ff, "Ia32X2ApicN", NULL, NULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals carefully with the EFER register.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR number.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The current value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_Amd64Efer(uint32_t uMsr, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* NetBurst prescott 2MB (model 4) hung or triple faulted here. The extra
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync sleep or something seemed to help for some screwed up reason. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync // This doesn't matter:
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //fSkipMask |= MSR_K6_EFER_SCE;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //if (vbCpuRepSupportsLongMode())
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync // fSkipMask |= MSR_K6_EFER_LMA;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync //vbCpuRepDebug("EFER - netburst workaround - ignore SCE & LMA (fSkipMask=%#llx)\n", fSkipMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("EFER - netburst sleep fudge - fSkipMask=%#llx\n", fSkipMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, MSR_K6_EFER_LMA, NULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals with the MC4_MISCn (n >= 1) range and the following reserved MSRs.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param paMsrs Pointer to the first MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param cMsrs The number of MSRs in the array @a paMsr.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pidxLoop Index variable that should be advanced to the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * last MSR entry in the range.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_AmdFam10hMc4MiscN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Count registers. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Probe & report used MSRs. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = msrProberModifyBitChanges(paMsrs[cUsed].uMsr, &fIgnMaskN, &fGpMaskN, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (fIgnMaskN == UINT64_MAX || fGpMaskN == UINT64_MAX)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_NOT_EQUAL, "AmdFam16hMc4MiscN mismatch: fIgn=%#llx/%#llx fGp=%#llx/%#llx uMsr=%#x\n",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fIgnMaskN, fIgnMask, fGpMaskN, fGpMask, paMsrs[cUsed].uMsr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync printMsrRangeFunctionEx(paMsrs[0].uMsr, paMsrs[cUsed - 1].uMsr, "AmdFam10hMc4MiscN", NULL, 0, fIgnMask, fGpMask, NULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Probe & report reserved MSRs. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = msrProberModifyBitChanges(paMsrs[cUsed + cReserved].uMsr, &fIgnMask, &fGpMask, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if ((fIgnMask != UINT64_MAX && fGpMask != UINT64_MAX) || paMsrs[cUsed + cReserved].uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "Unexpected reserved AmdFam16hMc4MiscN: fIgn=%#llx fGp=%#llx uMsr=%#x uValue=%#llx\n",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fIgnMask, fGpMask, paMsrs[cUsed + cReserved].uMsr, paMsrs[cUsed + cReserved].uValue);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync printMsrRangeValueIgnoreWrites(paMsrs[cUsed].uMsr, paMsrs[cUsed + cReserved - 1].uMsr, 0, NULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync printMsrRangeValueReadOnly(paMsrs[cUsed].uMsr, paMsrs[cUsed + cReserved - 1].uMsr, 0, NULL);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals with the AMD PERF_CTL range.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param paMsrs Pointer to the first MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param cMsrs The number of MSRs in the array @a paMsr.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pidxLoop Index variable that should be advanced to the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * last MSR entry in the range.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_AmdK8PerfCtlN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Family 15h (bulldozer +) aliases these registers sparsely onto c001020x. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return reportMsr_GenRangeFunction(paMsrs, cMsrs, 4, "AmdK8PerfCtlN", pidxLoop);
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync * Deals with the AMD PERF_CTR range.
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync * @returns VBox status code.
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync * @param paMsrs Pointer to the first MSR.
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync * @param cMsrs The number of MSRs in the array @a paMsr.
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync * @param pidxLoop Index variable that should be advanced to the
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync * last MSR entry in the range.
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsyncstatic int reportMsr_AmdK8PerfCtrN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Family 15h (bulldozer +) aliases these registers sparsely onto c001020x. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return reportMsr_GenRangeFunction(paMsrs, cMsrs, 4, "AmdK8PerfCtrN", pidxLoop);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals carefully with the SYS_CFG register.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR number.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The current value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_AmdK8SysCfg(uint32_t uMsr, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Bit 21 (MtrrTom2En) is marked reserved in family 0fh, while in family
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync 10h BKDG this changes (as does the document style). Testing this bit
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync causes bulldozer running win64 to restart, thus this special treatment. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Turns out there are more killer bits here, at least on Opteron 2384.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync Skipping all known bits. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_65nm /* Not sure when introduced - harmless? */)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First && g_enmMicroarch < kCpumMicroarch_AMD_15h_First)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (g_enmMicroarch >= kCpumMicroarch_AMD_K8_First && g_enmMicroarch < kCpumMicroarch_AMD_15h_First)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals carefully with the HWCR register.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR number.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The current value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_AmdK8HwCr(uint32_t uMsr, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Trouble on Opteron 2384, skip some of the known bits. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (g_enmMicroarch >= kCpumMicroarch_AMD_K10 && !CPUMMICROARCH_IS_AMD_FAM_11H(g_enmMicroarch))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= RT_BIT(8); /* #IGNNE port emulation */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals carefully with a IORRBasei register.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR number.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The current value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_AmdK8IorrBaseN(uint32_t uMsr, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Skip know bits here, as harm seems to come from messing with them. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & X86_PAGE_4K_BASE_MASK;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010016) / 2, fSkipMask, 0, annotateValue(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals carefully with a IORRMaski register.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR number.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The current value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_AmdK8IorrMaskN(uint32_t uMsr, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Skip know bits here, as harm seems to come from messing with them. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & X86_PAGE_4K_BASE_MASK;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return reportMsr_GenFunctionEx(uMsr, NULL, (uMsr - 0xc0010017) / 2, fSkipMask, 0, annotateValue(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals carefully with a IORRMaski register.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR number.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The current value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_AmdK8TopMemN(uint32_t uMsr, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Skip know bits here, as harm seems to come from messing with them. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint64_t fSkipMask = (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & ~(RT_BIT_64(23) - 1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return reportMsr_GenFunctionEx(uMsr, NULL, uMsr == 0xc001001d, fSkipMask, 0, annotateValue(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals with the AMD P-state config range.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param paMsrs Pointer to the first MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param cMsrs The number of MSRs in the array @a paMsr.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pidxLoop Index variable that should be advanced to the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * last MSR entry in the range.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_AmdFam10hPStateN(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t *pidxLoop)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Count them. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Figure out which bits we should skip when probing. This is based on
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync specs and may need adjusting for real life when handy. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= RT_BIT_64(41) | RT_BIT_64(40); /* IddDiv */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= UINT64_C(0x000000ff00000000); /* IddValue */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= UINT32_C(0xfe000000); /* NbVid - Northbridge VID */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= RT_BIT_32(22); /* NbDid or NbPstate. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver) /* ?? - listed in 10-1Fh model BDKG as well asFam16h */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= UINT32_C(0x0000fe00); /* CpuVid[6:0] */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Probe and report them one by one since we're passing values instead of
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync register indexes to the functions. */
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync int rc = msrProberModifyBitChanges(uMsr + i, &fIgnMask, &fGpMask, fSkipMask);
a1d83f29ade4c8f9fe95fc75d3fb2642f36081c1vboxsync printMsrFunctionExtended(uMsr + i, "AmdFam10hPStateN", NULL, paMsrs[i].uValue, fIgnMask, fGpMask,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Advance. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals carefully with a COFVID control register.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR number.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The current value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_AmdFam10hCofVidControl(uint32_t uMsr, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Skip know bits here, as harm seems to come from messing with them. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= UINT32_C(0xfe000000); /* NbVid - Northbridge VID */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_First) /* Listed in preliminary Fam16h BDKG. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= UINT32_C(0xff000000); /* NbVid - Northbridge VID - includes bit 24 for Fam15h and Fam16h. Odd... */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || g_enmMicroarch >= kCpumMicroarch_AMD_15h_First) /* Listed in preliminary Fam16h BDKG. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= RT_BIT_32(22); /* NbDid or NbPstate. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver) /* ?? - listed in 10-1Fh model BDKG as well asFam16h */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= UINT32_C(0x0000fe00); /* CpuVid[6:0] */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals with the AMD [|L2I_|NB_]PERF_CT[LR] mixed ranges.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Mixed here refers to the control and counter being in mixed in pairs as
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * opposed to them being two separate parallel arrays like in the 0xc0010000
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param paMsrs Pointer to the first MSR.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param cMsrs The number of MSRs in the array @a paMsr.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param cMax The max number of MSRs (not counters).
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pidxLoop Index variable that should be advanced to the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * last MSR entry in the range.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_AmdGenPerfMixedRange(VBCPUREPMSR const *paMsrs, uint32_t cMsrs, uint32_t cMax, uint32_t *pidxLoop)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Count them. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_INVALID_PARAMETER, "PERF range at %#x is odd: cRegs=%#x\n", uMsr, cRegs);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Report them as individual entries, using default names and such. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = msrProberModifyBitChanges(uMsr + i, &fIgnMask, &fGpMask, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync printMsrFunctionExtendedIdxVal(uMsr + i, NULL, NULL, i / 2, fIgnMask, fGpMask, annotateValue(paMsrs[i].uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Advance. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deals carefully with a LS_CFG register.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR number.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The current value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_AmdK7InstrCacheCfg(uint32_t uMsr, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Skip know bits here, as harm seems to come from messing with them. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint64_t fSkipMask = RT_BIT_64(9) /* DIS_SPEC_TLB_RLD */;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= RT_BIT_64(26); /* DIS_WIDEREAD_PWR_SAVE */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= RT_BIT_64(27); /* Unknown killer bit, possibly applicable to other microarchs. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= RT_BIT_64(28); /* Unknown killer bit, possibly applicable to other microarchs. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
e56dcfc21604789f99b06a9353f45ed5205256advboxsync * Deals carefully with a CU_CFG register.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
e56dcfc21604789f99b06a9353f45ed5205256advboxsync * @param uMsr The MSR number.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The current value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_AmdFam15hCombUnitCfg(uint32_t uMsr, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Skip know bits here, as harm seems to come from messing with them. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= RT_BIT_64(46) | RT_BIT_64(45); /* Killer field. Seen bit 46 set, 45 clear. Messing with either means reboot/BSOD. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
e56dcfc21604789f99b06a9353f45ed5205256advboxsync * Deals carefully with a EX_CFG register.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uMsr The MSR number.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param uValue The current value.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int reportMsr_AmdFam15hExecUnitCfg(uint32_t uMsr, uint64_t uValue)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Skip know bits here, as harm seems to come from messing with them. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint64_t fSkipMask = RT_BIT_64(54) /* LateSbzResync */;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fSkipMask |= RT_BIT_64(35); /* Undocumented killer bit. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return reportMsr_GenFunctionEx(uMsr, NULL, uValue, fSkipMask, 0, annotateValue(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int produceMsrReport(VBCPUREPMSR *paMsrs, uint32_t cMsrs)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("produceMsrReport: uMsr=%#x (%s)...\n", uMsr, getMsrNameHandled(uMsr));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Deal with write only regs first to avoid having to avoid them all the time.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * VIA implement MSRs in a interesting way, so we have to select what we
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * want to handle there to avoid making the code below unreadable.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_ViaDummyRange(&paMsrs[i], cMsrs - i, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * This shall be sorted by uMsr as much as possible.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0x00000000 && g_enmVendor == CPUMCPUVENDOR_AMD && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0x00000001 && g_enmVendor == CPUMCPUVENDOR_AMD && g_enmMicroarch >= kCpumMicroarch_AMD_K8_First)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrAlias(uMsr, 0x00000401, NULL); /** @todo not 101% correct on Fam15h and later, 0xc0010015[McstatusWrEn] effect differs. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0x00000040 && g_enmMicroarch <= kCpumMicroarch_Intel_P6_M_Dothan)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchFromToN", &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchToN", uMsr, false,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0x00000060 && g_enmMicroarch >= kCpumMicroarch_Intel_Core_Yonah)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "IntelLastBranchFromN", uMsr, false,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync g_enmMicroarch >= kCpumMicroarch_Intel_Core7_First ? 8 : 4 /*cMax*/,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8 /*cMax*/, "Ia32PerfEvtSelN", &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 2 /*cMax*/, "IntelI7MsrOffCoreResponseN", &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 4 /*cMax*/, "IntelLastBranchFromToN", &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_Ia32MtrrPhysBaseMaskN(&paMsrs[i], cMsrs - i, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 22 /*cMax*/, NULL, 0x00000280, true /*fEarlyEndOk*/, false, 0, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr >= 0x00000309 && uMsr <= 0x0000030b && !g_fIntelNetBurst)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3 /*cMax*/, NULL, 0x00000309, true /*fEarlyEndOk*/, false, 0, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if ((uMsr == 0x000003f8 || uMsr == 0x000003fc || uMsr == 0x0000060a) && !g_fIntelNetBurst)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 4, NULL, uMsr - 3, true, false, 0, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if ((uMsr == 0x000003f9 || uMsr == 0x000003fd || uMsr == 0x0000060b) && !g_fIntelNetBurst)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 6, true, false, 0, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if ((uMsr == 0x000003fa || uMsr == 0x000003fe || uMsr == 0x0000060c) && !g_fIntelNetBurst)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 8, NULL, uMsr - 7, true, false, 0, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_Ia32McCtlStatusAddrMiscN(&paMsrs[i], cMsrs - i, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 8, NULL, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 16, NULL, uMsr, false, false,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenX2Apic(&paMsrs[i], cMsrs - i, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0x00002000 && g_enmVendor == CPUMCPUVENDOR_INTEL)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 0, X86_CR0_PE | X86_CR0_PG, 0,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync annotateIfMissingBits(uValue, X86_CR0_PE | X86_CR0_PE | X86_CR0_ET));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0x00002002 && g_enmVendor == CPUMCPUVENDOR_INTEL)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 2, 0, 0, annotateValue(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0x00002003 && g_enmVendor == CPUMCPUVENDOR_INTEL)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync uint64_t fCr3Mask = (RT_BIT_64(vbCpuRepGetPhysAddrWidth()) - 1) & (X86_CR3_PAE_PAGE_MASK | X86_CR3_AMD64_PAGE_MASK);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fCr3Mask &= X86_CR3_PAGE_MASK | X86_CR3_AMD64_PAGE_MASK;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 3, fCr3Mask, 0, annotateValue(uValue));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0x00002004 && g_enmVendor == CPUMCPUVENDOR_INTEL)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenFunctionEx(uMsr, "IntelP6CrN", 4,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE | X86_CR4_SMXE, 0,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0000082 || uMsr == 0xc0000083 || uMsr == 0xc0000100 || uMsr == 0xc0000101 || uMsr == 0xc0000102)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenFunctionEx(uMsr, NULL, 0, UINT64_C(0xffff800000000000), 0, annotateValue(uValue)); /* Canoncial address hack. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_AmdFam10hMc4MiscN(&paMsrs[i], cMsrs - i, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0010000 && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_AmdK8PerfCtlN(&paMsrs[i], cMsrs - i, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0010004 && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_AmdK8PerfCtrN(&paMsrs[i], cMsrs - i, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0010010 && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0010015 && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if ((uMsr == 0xc0010016 || uMsr == 0xc0010018) && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if ((uMsr == 0xc0010017 || uMsr == 0xc0010019) && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if ((uMsr == 0xc001001a || uMsr == 0xc001001d) && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0010030 && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 6, "AmdK8CpuNameN", &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr >= 0xc0010044 && uMsr <= 0xc001004a && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 7, "AmdK8McCtlMaskN", 0xc0010044, true /*fEarlyEndOk*/, false, 0, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0010050 && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunction(&paMsrs[i], cMsrs - i, 4, "AmdK8SmiOnIoTrapN", &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0010064 && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_AmdFam10hPStateN(&paMsrs[i], cMsrs - i, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0010070 && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_AmdFam10hCofVidControl(uMsr, uValue);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if ((uMsr == 0xc0010118 || uMsr == 0xc0010119) && getMsrFnName(uMsr, NULL) && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = printMsrFunction(uMsr, NULL, NULL, annotateValue(uValue)); /* RAZ, write key. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0010200 && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 12, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0010230 && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 8, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0010240 && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_AmdGenPerfMixedRange(&paMsrs[i], cMsrs - i, 8, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0011019 && g_enmMicroarch >= kCpumMicroarch_AMD_15h_Piledriver && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 3, "AmdK7DrXAddrMaskN", 0xc0011019 - 1,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync false /*fEarlyEndOk*/, false /*fNoIgnMask*/, 0, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0011021 && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0011023 && CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc0011027 && g_enmVendor == CPUMCPUVENDOR_AMD)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = reportMsr_GenRangeFunctionEx(&paMsrs[i], cMsrs - i, 1, "AmdK7DrXAddrMaskN", 0xc0011027,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync false /*fEarlyEndOk*/, false /*fNoIgnMask*/, 0, &i);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync else if (uMsr == 0xc001102c && CPUMMICROARCH_IS_AMD_FAM_15H(g_enmMicroarch))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* generic handling. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Custom MSR hacking & probing.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Called when the '-d' option is given.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns VBox status code.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int hackingMsrs(void)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("\nhackingMsrs:\n"); RTStrmFlush(g_pDebugOut); RTThreadSleep(2000);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("%#x: msrProberModifyNoChange -> %RTbool\n", uMsr, msrProberModifyNoChange(uMsr));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("%#x: msrProberModifyBit 30 -> %d\n", uMsr, msrProberModifyBit(uMsr, 30));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("%#x: msrProberModifyZero -> %RTbool\n", uMsr, msrProberModifyZero(uMsr));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("%#x: bit=%02u -> %d\n", msrProberModifyBit(uMsr, i));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Try for a triple fault... */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int probeMsrs(bool fHacking, const char *pszNameC, const char *pszCpuDesc,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Initialize the mask. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTStrCopy(pszMsrMask, cbMsrMask, "UINT32_MAX /** @todo */");
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Are MSRs supported by the CPU?
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || !(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_MSR) )
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("Skipping MSR probing, CPUID indicates there isn't any MSR support.\n");
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Initialize the support library and check if we can read MSRs.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("warning: Unable to initialize the support library (%Rrc), skipping MSR detection.\n", rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = SUPR3MsrProberRead(MSR_IA32_TSC, NIL_RTCPUID, &uValue, &fGp);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("warning: MSR probing not supported by the support driver (%Rrc), skipping MSR detection.\n", rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("MSR_IA32_TSC: %#llx fGp=%RTbool\n", uValue, fGp);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = SUPR3MsrProberRead(0xdeadface, NIL_RTCPUID, &uValue, &fGp);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("0xdeadface: %#llx fGp=%RTbool rc=%Rrc\n", uValue, fGp, rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Initialize globals we use.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMCpuIdExSlow(0, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_NOT_SUPPORTED, "Invalid std CPUID range: %#x\n", uEax);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync g_enmVendor = CPUMR3CpuIdDetectVendorEx(uEax, uEbx, uEcx, uEdx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync g_enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(g_enmVendor,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMGetCpuModel(uEax, g_enmVendor == CPUMCPUVENDOR_INTEL),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync g_fIntelNetBurst = CPUMMICROARCH_IS_INTEL_NETBURST(g_enmMicroarch);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Do the probing.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Determine the MSR mask. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTStrPrintf(pszMsrMask, cbMsrMask, "UINT32_C(%#x)", fMsrMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Detect MSR. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Probe the MSRs and spit out the database table. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "#ifndef CPUM_DB_STANDALONE\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " * MSR ranges for %s.\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "static CPUMMSRRANGE const g_aMsrRanges_%s[] = \n{\n",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "#endif /* !CPUM_DB_STANDALONE */\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int produceCpuIdArray(const char *pszNameC, const char *pszCpuDesc)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Collect the data.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(rc, "CPUMR3CollectCpuIdInfo failed: %Rrc\n", rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Dump the array.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "#ifndef CPUM_DB_STANDALONE\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " * CPUID leaves for %s.\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "static CPUMCPUIDLEAF const g_aCpuIdLeaves_%s[] = \n{\n",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" { %#010x, %#010x, ", paLeaves[i].uLeaf, paLeaves[i].uSubLeaf);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf("%#010x, ", paLeaves[i].fSubLeafMask);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync paLeaves[i].uEax, paLeaves[i].uEbx, paLeaves[i].uEcx, paLeaves[i].uEdx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (paLeaves[i].fFlags & CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepPrintf(" | CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED");
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync fFlags &= ~CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(rc, "Unknown CPUID flags %#x\n", fFlags);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "#endif /* !CPUM_DB_STANDALONE */\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic const char *cpuVendorToString(CPUMCPUVENDOR enmCpuVendor)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return "invalid-cpu-vendor";
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncstatic int produceCpuReport(void)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Figure the cpu vendor.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_NOT_SUPPORTED, "No CPUID support.\n");
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMCpuIdExSlow(0, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_NOT_SUPPORTED, "Invalid std CPUID range: %#x\n", uEax);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync CPUMCPUVENDOR enmVendor = CPUMR3CpuIdDetectVendorEx(uEax, uEbx, uEcx, uEdx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(VERR_NOT_IMPLEMENTED, "Unknown CPU vendor: %.4s%.4s%.4s\n", &uEbx, &uEdx, &uEcx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("CPU Vendor: %s - %.4s%.4s%.4s\n", CPUMR3CpuVendorName(enmVendor), &uEbx, &uEdx, &uEcx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Determine the micro arch.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync CPUMMICROARCH enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Generate a name.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMCpuIdExSlow(0x80000000, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (ASMIsValidExtRange(uEax) && uEax >= UINT32_C(0x80000004))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Get the raw name and strip leading spaces. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMCpuIdExSlow(0x80000002, 0, 0, 0, &szNameRaw[0 + 0], &szNameRaw[4 + 0], &szNameRaw[8 + 0], &szNameRaw[12 + 0]);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMCpuIdExSlow(0x80000003, 0, 0, 0, &szNameRaw[0 + 16], &szNameRaw[4 + 16], &szNameRaw[8 + 16], &szNameRaw[12 + 16]);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMCpuIdExSlow(0x80000004, 0, 0, 0, &szNameRaw[0 + 32], &szNameRaw[4 + 32], &szNameRaw[8 + 32], &szNameRaw[12 + 32]);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Reduce the name. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync static const char * const s_apszSuffixes[] =
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync for (uint32_t i = 0; i < RT_ELEMENTS(s_apszSuffixes); i++)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync static const char * const s_apszWords[] =
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "(TM)", "(tm)", "(R)", "(r)", "Processor", "CPU", "@",
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync for (uint32_t i = 0; i < RT_ELEMENTS(s_apszWords); i++)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync while ((pszHit = strstr(pszName, pszWord)) != NULL)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync memmove(pszHit, pszHit + cchWord, strlen(pszHit + cchWord) + 1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync memmove(psz + 1, psz + cchBlanks, strlen(psz + cchBlanks) + 1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* Make it C/C++ acceptable. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync unsigned offDst = 0;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (ch == '_' && offDst > 0 && szNameC[offDst - 1] == '_')
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTStrPrintf(szNameC, sizeof(szNameC), "%s_%u_%u_%u", cpuVendorToString(enmVendor), ASMGetCpuFamily(uEax),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL), ASMGetCpuStepping(uEax));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Print a file header, if we're not outputting to stdout (assumption being
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * that stdout is used while hacking the reporter and too much output is
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * unwanted).
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTTimeSpecToString(RTTimeNow(&Now), szNow, sizeof(szNow));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "/** @file\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " * CPU database entry \"%s\".\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " * Generated at %s by VBoxCpuReport v%sr%s on %s.%s.\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " * Copyright (C) 2013 Oracle Corporation\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " * This file is part of VirtualBox Open Source Edition (OSE), as\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " * available from http://www.virtualbox.org. This file is free software;\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " * you can redistribute it and/or modify it under the terms of the GNU\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " * General Public License (GPL) as published by the Free Software\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " * Foundation, in version 2 as it comes in the \"COPYING\" file of the\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " * VirtualBox OSE distribution. VirtualBox OSE is distributed in the\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "#ifndef VBOX_CPUDB_%s\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "#define VBOX_CPUDB_%s\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync szNow, RTBldCfgVersion(), RTBldCfgRevisionStr(), RTBldCfgTarget(), RTBldCfgTargetArch(),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Extract CPUID based data.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = CPUMR3CpuIdDetectUnknownLeafMethod(&enmUnknownMethod, &DefUnknown);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return RTMsgErrorRc(rc, "CPUMR3DetectCpuIdUnknownMethod failed: %Rrc\n", rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync vbCpuRepDebug("enmUnknownMethod=%s\n", CPUMR3CpuIdUnknownLeafMethodName(enmUnknownMethod));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Do the MSRs, if we can.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync probeMsrs(false /*fHacking*/, szNameC, pszCpuDesc, szMsrMask, sizeof(szMsrMask));
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Emit the CPUMDBENTRY record.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMCpuIdExSlow(1, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " * Database entry for %s.\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "static CPUMDBENTRY const g_Entry_%s = \n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.pszName = */ \"%s\",\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.pszFullName = */ \"%s\",\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.enmVendor = */ CPUMCPUVENDOR_%s,\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.uFamily = */ %u,\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.uModel = */ %u,\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.uStepping = */ %u,\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.enmMicroarch = */ kCpumMicroarch_%s,\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.fFlags = */ 0,\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.cMaxPhysAddrWidth= */ %u,\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.paCpuIdLeaves = */ NULL_ALONE(g_aCpuIdLeaves_%s),\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.cCpuIdLeaves = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_%s)),\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.enmUnknownCpuId = */ CPUMUKNOWNCPUID_%s,\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.DefUnknownCpuId = */ { %#010x, %#010x, %#010x, %#010x },\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.fMsrMask = */ %s,\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.cMsrRanges = */ ZERO_ALONE(RT_ELEMENTS(g_aMsrRanges_%s)),\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync " /*.paMsrRanges = */ NULL_ALONE(g_aMsrRanges_%s),\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync "#endif /* !VBOX_DB_%s */\n"
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ASMGetCpuModel(uEax, enmVendor == CPUMCPUVENDOR_INTEL),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync CPUMR3CpuIdUnknownLeafMethodName(enmUnknownMethod),
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Argument parsing?
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTGetOptInit(&State, argc, argv, &s_aOptions[0], RT_ELEMENTS(s_aOptions), 1, RTGETOPTINIT_FLAGS_OPTS_FIRST);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync while ((iOpt = RTGetOpt(&State, &ValueUnion)) != 0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTPrintf("Usage: VBoxCpuReport [-m|--msrs-only] [-d|--msrs-dev] [-h|--help] [-V|--version] [-o filename.h] [-l debug.log]\n");
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTPrintf("Internal tool for gathering information to the VMM CPU database.\n");
cce0c6096dee0c5353bb74431dc47b05f87a1c6dvboxsync RTPrintf("%sr%s\n", RTBldCfgVersion(), RTBldCfgRevisionStr());
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Open the alternative debug log stream.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (RTFileExists(pszDebugOut) && !RTSymlinkExists(pszDebugOut))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTFileRename(pszDebugOut, szOld, RTFILEMOVE_FLAGS_REPLACE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTMsgError("Error opening '%s': %Rrc", pszDebugOut, rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Do the requested job.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /* switch output file. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync if (RTFileExists(pszOutput) && !RTSymlinkExists(pszOutput))
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTFileRename(pszOutput, szOld, RTFILEMOVE_FLAGS_REPLACE);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync RTMsgError("Error opening '%s': %Rrc", pszOutput, rc);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync rc = probeMsrs(enmOp == kCpuReportOp_MsrsHacking, NULL, NULL, NULL, 0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Close the output files.