553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncfrom __future__ import print_function;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync__copyright__ = \

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync__version__ = "$Revision$";

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncimport io;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncimport os;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncfrom optparse import OptionParser

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncimport random;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncimport sys;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncRTEXITCODE_SUCCESS = 0;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncRTEXITCODE_SYNTAX = 2;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsyncUINT8_MAX = 0xff

c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsyncUINT16_MAX = 0xffff

c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsyncUINT32_MAX = 0xffffffff

c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsyncUINT64_MAX = 0xffffffffffffffff

c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsyncdef RT_BIT_32(iBit): # pylint: disable=C0103

c10a6f0c7041e4d1ee50ad38425aab9d43c55522vboxsync """ 32-bit one bit mask. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return 1 << iBit;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncdef RT_BIT_64(iBit): # pylint: disable=C0103

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync """ 64-bit one bit mask. """

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync return 1 << iBit;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsyncX86_MODRM_RM_MASK = 0x07;

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsyncX86_MODRM_REG_MASK = 0x38;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsyncX86_MODRM_REG_SMASK = 0x07;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_MODRM_REG_SHIFT = 3;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_MODRM_MOD_MASK = 0xc0;

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsyncX86_MODRM_MOD_SMASK = 0x03;

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsyncX86_MODRM_MOD_SHIFT = 6;

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_SIB_BASE_MASK = 0x07;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_SIB_INDEX_MASK = 0x38;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_SIB_INDEX_SMASK = 0x07;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_SIB_INDEX_SHIFT = 3;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_SIB_SCALE_MASK = 0xc0;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_SIB_SCALE_SMASK = 0x03;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_SIB_SCALE_SHIFT = 6;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_OP_PRF_CS = 0x2e;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_OP_PRF_SS = 0x36;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_OP_PRF_DS = 0x3e;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_OP_PRF_ES = 0x26;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_OP_PRF_FS = 0x64;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_OP_PRF_GS = 0x65;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_OP_PRF_SIZE_OP = 0x66;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_OP_PRF_SIZE_ADDR = 0x67;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_OP_PRF_LOCK = 0xf0;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_OP_PRF_REPZ = 0xf2;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_OP_PRF_REPNZ = 0xf3;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_OP_REX_B = 0x41;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_OP_REX_X = 0x42;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_OP_REX_R = 0x44;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_OP_REX_W = 0x48;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsyncX86_GREG_xAX = 0

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_GREG_xCX = 1

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_GREG_xDX = 2

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_GREG_xBX = 3

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_GREG_xSP = 4

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_GREG_xBP = 5

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_GREG_xSI = 6

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_GREG_xDI = 7

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_GREG_x8 = 8

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_GREG_x9 = 9

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_GREG_x10 = 10

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_GREG_x11 = 11

ffb50166c9adb4ae583b914d405197035cf890advboxsyncX86_GREG_x12 = 12

ffb50166c9adb4ae583b914d405197035cf890advboxsyncX86_GREG_x13 = 13

ffb50166c9adb4ae583b914d405197035cf890advboxsyncX86_GREG_x14 = 14

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncX86_GREG_x15 = 15

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncg_asGRegs64NoSp = ('rax', 'rcx', 'rdx', 'rbx', None, 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncg_asGRegs64 = ('rax', 'rcx', 'rdx', 'rbx', 'rsp', 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncg_asGRegs32NoSp = ('eax', 'ecx', 'edx', 'ebx', None, 'ebp', 'esi', 'edi',

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync 'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncg_asGRegs32 = ('eax', 'ecx', 'edx', 'ebx', 'esp', 'ebp', 'esi', 'edi',

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync 'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncg_asGRegs16NoSp = ('ax', 'cx', 'dx', 'bx', None, 'bp', 'si', 'di',

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync 'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncg_asGRegs16 = ('ax', 'cx', 'dx', 'bx', 'sp', 'bp', 'si', 'di',

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync 'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncg_asGRegs8 = ('al', 'cl', 'dl', 'bl', 'ah', 'ch', 'dh', 'bh');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncg_asGRegs8Rex = ('al', 'cl', 'dl', 'bl', 'spl', 'bpl', 'sil', 'dil',

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync 'r8b', 'r9b', 'r10b', 'r11b', 'r12b', 'r13b', 'r14b', 'r15b',

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync 'ah', 'ch', 'dh', 'bh');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncg_oMyRand = random.SystemRandom()

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncdef randU16():

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Unsigned 16-bit random number. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return g_oMyRand.getrandbits(16);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncdef randU32():

248c89033c87fed7229aa29bbbc4f4698fb13687vboxsync """ Unsigned 32-bit random number. """

248c89033c87fed7229aa29bbbc4f4698fb13687vboxsync return g_oMyRand.getrandbits(32);

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncdef randU64():

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Unsigned 64-bit random number. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return g_oMyRand.getrandbits(64);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncdef randUxx(cBits):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Unsigned 8-, 16-, 32-, or 64-bit random number. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return g_oMyRand.getrandbits(cBits);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncdef randUxxList(cBits, cElements):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ List of unsigned 8-, 16-, 32-, or 64-bit random numbers. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return [randUxx(cBits) for _ in range(cElements)];

b4d7b4dbcc45b8bde7502aa129440d92d7ffd038vboxsync

b4d7b4dbcc45b8bde7502aa129440d92d7ffd038vboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncdef calcRexPrefixForTwoModRmRegs(iReg, iRm, bOtherRexPrefixes = 0):

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync """

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync bRex = bOtherRexPrefixes;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if iReg >= 8:

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync bRex |= X86_OP_REX_R;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if iRm >= 8:

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync bRex |= X86_OP_REX_B;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if bRex == 0:

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync return [];

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync return [bRex,];

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsyncdef calcModRmForTwoRegs(iReg, iRm):

3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync """

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync bRm = (0x3 << X86_MODRM_MOD_SHIFT) \

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync | ((iReg << X86_MODRM_REG_SHIFT) & X86_MODRM_REG_MASK) \

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync | (iRm & X86_MODRM_RM_MASK);

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync return [bRm,];

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync

cd5df721f068659172f3bf95de8fedeb465f057dvboxsync

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsyncdef convU32ToSigned(u32):

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync """ Converts a 32-bit unsigned value to 32-bit signed. """

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if u32 < 0x80000000:

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync return u32;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync return u32 - UINT32_MAX - 1;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsyncdef rotateLeftUxx(cBits, uVal, cShift):

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync """ Rotate a xx-bit wide unsigned number to the left. """

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync assert cShift < cBits;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync if cBits == 16:

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync uMask = UINT16_MAX;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync elif cBits == 32:

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync uMask = UINT32_MAX;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync elif cBits == 64:

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync uMask = UINT64_MAX;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync else:

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync assert cBits == 8;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync uMask = UINT8_MAX;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync uVal &= uMask;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync uRet = (uVal << cShift) & uMask;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync uRet |= (uVal >> (cBits - cShift));

3fb3de312d1ff675e0f7cc62a7d46cbb1d5d9353vboxsync return uRet;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsyncdef rotateRightUxx(cBits, uVal, cShift):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Rotate a xx-bit wide unsigned number to the right. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync assert cShift < cBits;

11b175175a0ed424b8e8354acda681ad0adde0f8vboxsync

11b175175a0ed424b8e8354acda681ad0adde0f8vboxsync if cBits == 16:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uMask = UINT16_MAX;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync elif cBits == 32:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uMask = UINT32_MAX;

11b175175a0ed424b8e8354acda681ad0adde0f8vboxsync elif cBits == 64:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uMask = UINT64_MAX;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync assert cBits == 8;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uMask = UINT8_MAX;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uVal &= uMask;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uRet = (uVal >> cShift);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uRet |= (uVal << (cBits - cShift)) & uMask;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return uRet;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncdef gregName(iReg, cBits, fRexByteRegs = True):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Gets the name of a general register by index and width. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cBits == 64:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return g_asGRegs64[iReg];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cBits == 32:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return g_asGRegs32[iReg];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cBits == 16:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return g_asGRegs16[iReg];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync assert cBits == 8;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if fRexByteRegs:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return g_asGRegs8Rex[iReg];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return g_asGRegs8[iReg];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncclass TargetEnv(object):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ## @name CPU Modes

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ## @{

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ksCpuMode_Real = 'real';

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ksCpuMode_Protect = 'prot';

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ksCpuMode_Paged = 'paged';

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ksCpuMode_Long = 'long';

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ksCpuMode_V86 = 'v86';

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ## @}

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ## @name Instruction set.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ## @{

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ksInstrSet_16 = '16';

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ksInstrSet_32 = '32';

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ksInstrSet_64 = '64';

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ## @}

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def __init__(self, sName,

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync sInstrSet = ksInstrSet_32,

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync sCpuMode = ksCpuMode_Paged,

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync iRing = 3,

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.sName = sName;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.sInstrSet = sInstrSet;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.sCpuMode = sCpuMode;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.iRing = iRing;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.asGRegs = g_asGRegs64 if self.is64Bit() else g_asGRegs32;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.asGRegsNoSp = g_asGRegs64NoSp if self.is64Bit() else g_asGRegs32NoSp;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def isUsingIprt(self):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Whether it's an IPRT environment or not. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return self.sName.startswith('iprt');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def is64Bit(self):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Whether it's a 64-bit environment or not. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return self.sInstrSet == self.ksInstrSet_64;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def getDefOpBits(self):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Get the default operand size as a bit count. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if self.sInstrSet == self.ksInstrSet_16:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return 16;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return 32;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def getDefOpBytes(self):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Get the default operand size as a byte count. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return self.getDefOpBits() / 8;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def getMaxOpBits(self):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Get the max operand size as a bit count. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if self.sInstrSet == self.ksInstrSet_64:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return 64;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return 32;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def getMaxOpBytes(self):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Get the max operand size as a byte count. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return self.getMaxOpBits() / 8;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def getDefAddrBits(self):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Get the default address size as a bit count. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if self.sInstrSet == self.ksInstrSet_16:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return 16;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if self.sInstrSet == self.ksInstrSet_32:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return 32;

5c9a5681751a936cd9fe7e98d9f30de34bc99372vboxsync return 64;

5c9a5681751a936cd9fe7e98d9f30de34bc99372vboxsync

5c9a5681751a936cd9fe7e98d9f30de34bc99372vboxsync def getDefAddrBytes(self):

5c9a5681751a936cd9fe7e98d9f30de34bc99372vboxsync """ Get the default address size as a byte count. """

cd5df721f068659172f3bf95de8fedeb465f057dvboxsync return self.getDefAddrBits() / 8;

cd5df721f068659172f3bf95de8fedeb465f057dvboxsync

5c9a5681751a936cd9fe7e98d9f30de34bc99372vboxsync def getGRegCount(self, cbEffBytes = 4):

5c9a5681751a936cd9fe7e98d9f30de34bc99372vboxsync """ Get the number of general registers. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if self.sInstrSet == self.ksInstrSet_64:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cbEffBytes == 1:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync return 16 + 4;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync return 16;

b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync return 8;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync def randGRegNoSp(self, cbEffBytes = 4):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync """ Returns a random general register number, excluding the SP register. """

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync iReg = randU16() % self.getGRegCount(cbEffBytes);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync while iReg == X86_GREG_xSP:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync iReg = randU16() % self.getGRegCount(cbEffBytes);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync return iReg;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync def randGRegNoSpList(self, cItems, cbEffBytes = 4):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync """ List of randGRegNoSp values. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync aiRegs = [];

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync for i in range(cItems):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync aiRegs.append(self.randGRegNoSp(cbEffBytes));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return aiRegs;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def getAddrModes(self):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Gets a list of addressing mode (16, 32, or/and 64). """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if self.sInstrSet == self.ksInstrSet_16:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return [16, 32];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if self.sInstrSet == self.ksInstrSet_32:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return [32, 16];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return [64, 32];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def is8BitHighGReg(self, cbEffOp, iGReg):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync """ Checks if the given register is a high 8-bit general register (AH, CH, DH or BH). """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync assert cbEffOp in [1, 2, 4, 8];

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if cbEffOp == 1:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if iGReg >= 16:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iGReg >= 4 and not self.is64Bit():

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return False;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncg_dTargetEnvs = {

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync 'iprt-r3-32': TargetEnv('iprt-r3-32', TargetEnv.ksInstrSet_32, TargetEnv.ksCpuMode_Protect, 3),

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync 'iprt-r3-64': TargetEnv('iprt-r3-64', TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long, 3),

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync};

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncclass InstrTestBase(object):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """

ebe46865faa75932265b29148843c6c54ffcb6a4vboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def __init__(self, sName, sInstr = None):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.sName = sName;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.sInstr = sInstr if sInstr else sName.split()[0];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def isApplicable(self, oGen):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync _ = oGen;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def generateTest(self, oGen, sTestFnName):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(';; @todo not implemented. This is for the linter: %s, %s\n' % (oGen, sTestFnName));

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def generateInputs(self, cbEffOp, cbMaxOp, oGen, fLong = False):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Generate a list of inputs. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if fLong:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync #

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # Try do extremes as well as different ranges of random numbers.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync #

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync auRet = [0, 1, ];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cbMaxOp >= 1:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync auRet += [ UINT8_MAX / 2, UINT8_MAX / 2 + 1, UINT8_MAX ];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cbMaxOp >= 2:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync auRet += [ UINT16_MAX / 2, UINT16_MAX / 2 + 1, UINT16_MAX ];

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if cbMaxOp >= 4:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync auRet += [ UINT32_MAX / 2, UINT32_MAX / 2 + 1, UINT32_MAX ];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cbMaxOp >= 8:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync auRet += [ UINT64_MAX / 2, UINT64_MAX / 2 + 1, UINT64_MAX ];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for cBits, cValues in ( (8, 4), (16, 4), (32, 8), (64, 8) ):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cBits < cbMaxOp * 8:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync auRet += randUxxList(cBits, cValues);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync cWanted = 16;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for cBits, cValues in ( (8, 8), (16, 8), (24, 2), (32, 16), (40, 1), (48, 1), (56, 1), (64, 16) ):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cBits < cbMaxOp * 8:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync auRet += randUxxList(cBits, cValues);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync cWanted = 64;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync for cBits, cValues in ( (8, 16), (16, 16), (24, 4), (32, 64), (40, 4), (48, 4), (56, 4), (64, 64) ):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if cBits < cbMaxOp * 8:

b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync auRet += randUxxList(cBits, cValues);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync cWanted = 168;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if len(auRet) < cWanted:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync auRet += randUxxList(cbEffOp * 8, cWanted - len(auRet));

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync else:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync #

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync # Short list, just do some random numbers.

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync #

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync auRet = [];

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync auRet += randUxxList(cbMaxOp, 1);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync auRet += randUxxList(cbMaxOp, 2);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync auRet = [];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for cBits in (8, 16, 32, 64):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cBits < cbMaxOp * 8:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync auRet += randUxxList(cBits, 1);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return auRet;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncclass InstrTest_MemOrGreg_2_Greg(InstrTestBase):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def __init__(self, sName, fnCalcResult, sInstr = None, acbOpVars = None):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync InstrTestBase.__init__(self, sName, sInstr);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.fnCalcResult = fnCalcResult;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.acbOpVars = [ 1, 2, 4, 8 ] if not acbOpVars else list(acbOpVars);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ## @name Test Instruction Writers

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ## @{

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Writes the instruction with two general registers as operands. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync fRexByteRegs = oGen.oTarget.is64Bit();

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' %s %s, %s\n'

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync % (self.sInstr, gregName(iOp1, cbEffOp * 8, fRexByteRegs), gregName(iOp2, cbEffOp * 8, fRexByteRegs),));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def writeInstrGregPureRM(self, cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen):

cd5df721f068659172f3bf95de8fedeb465f057dvboxsync """ Writes the instruction with two general registers as operands. """

cd5df721f068659172f3bf95de8fedeb465f057dvboxsync oGen.write(' ');

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if iOp2 == 13 and iMod == 0 and cAddrBits == 64:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write('altrexb '); # Alternative encoding for rip relative addressing.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cbEffOp == 8:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write('%s %s, [' % (self.sInstr, g_asGRegs64[iOp1],));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync elif cbEffOp == 4:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write('%s %s, [' % (self.sInstr, g_asGRegs32[iOp1],));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync elif cbEffOp == 2:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write('%s %s, [' % (self.sInstr, g_asGRegs16[iOp1],));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync elif cbEffOp == 1:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write('%s %s, [' % (self.sInstr, g_asGRegs8Rex[iOp1],));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync assert False;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if (iOp2 == 5 or iOp2 == 13) and iMod == 0:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.write('VBINSTST_NAME(g_u%sData)' % (cbEffOp * 8,))

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if oGen.oTarget.is64Bit():

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.write(' wrt rip');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iMod == 1:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write('byte %d + ' % (offDisp,));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync elif iMod == 2:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.write('dword %d + ' % (offDisp,));

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync else:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync assert iMod == 0;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cAddrBits == 64:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(g_asGRegs64[iOp2]);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync elif cAddrBits == 32:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(g_asGRegs32[iOp2]);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync elif cAddrBits == 16:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync assert False; ## @todo implement 16-bit addressing.

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync else:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync assert False, str(cAddrBits);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.write(']\n');

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync return True;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def writeInstrGregSibLabel(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync """ Writes the instruction taking a register and a label (base only w/o reg), SIB form. """

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync assert offDisp is None; assert iBaseReg in [5, 13]; assert iIndexReg == 4; assert cAddrBits != 16;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if cAddrBits == 64:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync # Note! Cannot test this in 64-bit mode in any sensible way because the disp is 32-bit

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync # and we cannot (yet) make assumtions about where we're loaded.

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync ## @todo Enable testing this in environments where we can make assumptions (boot sector).

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP]\n'

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync % ( self.sInstr, gregName(iOp1, cbEffOp * 8), cbEffOp * 8,));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' altsibx%u %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP]\n'

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync % ( iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), cbEffOp * 8,));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def writeInstrGregSibScaledReg(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Writes the instruction taking a register and disp+scaled register (no base reg), SIB form. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync assert iBaseReg in [5, 13]; assert iIndexReg != 4; assert cAddrBits != 16;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # Note! Using altsibxN to force scaled encoding. This is only really a

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # necessity for iScale=1, but doesn't hurt for the rest.

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.write(' altsibx%u %s %s, [%s * %#x'

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync % (iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), gregName(iIndexReg, cAddrBits), iScale,));

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if offDisp is not None:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.write(' + %#x' % (offDisp,));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(']\n');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync _ = iBaseReg;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def writeInstrGregSibBase(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Writes the instruction taking a register and base only (with reg), SIB form. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' altsibx%u %s %s, [%s'

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync % (iScale, self.sInstr, gregName(iOp1, cbEffOp * 8), gregName(iBaseReg, cAddrBits),));

cd5df721f068659172f3bf95de8fedeb465f057dvboxsync if offDisp is not None:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' + %#x' % (offDisp,));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(']\n');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync _ = iIndexReg;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def writeInstrGregSibBaseAndScaledReg(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Writes tinstruction taking a register and full featured SIB form address. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # Note! From the looks of things, yasm will encode the following instructions the same way:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # mov eax, [rsi*1 + rbx]

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # mov eax, [rbx + rsi*1]

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # So, when there are two registers involved, the '*1' selects

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # which is index and which is base.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' %s %s, [%s + %s * %u'

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync % ( self.sInstr, gregName(iOp1, cbEffOp * 8),

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync gregName(iBaseReg, cAddrBits), gregName(iIndexReg, cAddrBits), iScale,));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if offDisp is not None:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' + %#x' % (offDisp,));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(']\n');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ## @}

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ## @name Memory setups

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ## @{

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def generateMemSetupReadByLabel(self, oGen, cbEffOp, uInput):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Sets up memory for a memory read. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.pushConst(uInput);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def generateMemSetupReadByReg(self, oGen, cAddrBits, cbEffOp, iReg1, uInput, offDisp = None):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Sets up memory for a memory read indirectly addressed thru one register and optional displacement. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.pushConst(uInput);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' call VBINSTST_NAME(%s)\n'

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iBaseReg = iReg1, offDisp = offDisp),));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iReg1],));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def generateMemSetupReadByScaledReg(self, oGen, cAddrBits, cbEffOp, iIndexReg, iScale, uInput, offDisp = None):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Sets up memory for a memory read indirectly addressed thru one register and optional displacement. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.pushConst(uInput);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' call VBINSTST_NAME(%s)\n'

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, offDisp = offDisp, iIndexReg = iIndexReg, iScale = iScale),));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iIndexReg],));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def generateMemSetupReadByBaseAndScaledReg(self, oGen, cAddrBits, cbEffOp, iBaseReg, iIndexReg, iScale, uInput, offDisp):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Sets up memory for a memory read indirectly addressed thru two registers with optional displacement. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.pushConst(uInput);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' call VBINSTST_NAME(%s)\n'

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iBaseReg = iBaseReg, offDisp = offDisp,

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync iIndexReg = iIndexReg, iScale = iScale),));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iIndexReg],));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iBaseReg],));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def generateMemSetupPureRM(self, oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp = None):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Sets up memory for a pure R/M addressed read, iOp2 being the R/M value. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.pushConst(uInput);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync assert offDisp is None or iMod != 0;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if (iOp2 != 5 and iOp2 != 13) or iMod != 0:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' call VBINSTST_NAME(%s)\n'

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iOp2, offDisp),));

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync else:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ## @}

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def generateOneStdTestGregGreg(self, oGen, cbEffOp, cbMaxOp, iOp1, iOp1X, iOp2, iOp2X, uInput, uResult):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Generate one standard instr greg,greg test. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

c99b597540585068d22dde4c9f74730305f24097vboxsync oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2X], uInput,));

c99b597540585068d22dde4c9f74730305f24097vboxsync if iOp1X != iOp2X:

c99b597540585068d22dde4c9f74730305f24097vboxsync oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2X],));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.writeInstrGregGreg(cbEffOp, iOp1, iOp2, oGen);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.pushConst(uResult);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1X, iOp2X if iOp1X != iOp2X else None),));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync _ = cbMaxOp;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def generateOneStdTestGregGreg8BitHighPain(self, oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ High 8-bit registers are a real pain! """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync assert oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) or oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # Figure out the register indexes of the max op sized regs involved.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync iOp1X = iOp1 & 3;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync iOp2X = iOp2 & 3;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' ; iOp1=%u iOp1X=%u iOp2=%u iOp2X=%u\n' % (iOp1, iOp1X, iOp2, iOp2X,));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # Calculate unshifted result.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iOp1X != iOp2X:

4171ffb38eb8720b2ae9a8d13e95103ab26cfd12vboxsync uCur = oGen.auRegValues[iOp1X];

4171ffb38eb8720b2ae9a8d13e95103ab26cfd12vboxsync if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uCur = rotateRightUxx(cbMaxOp * 8, uCur, 8);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uCur = uInput;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) != oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uCur = rotateRightUxx(cbMaxOp * 8, uCur, 8);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else:

c99b597540585068d22dde4c9f74730305f24097vboxsync uCur = rotateLeftUxx(cbMaxOp * 8, uCur, 8);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uResult = self.fnCalcResult(cbEffOp, uInput, uCur, oGen);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

cd5df721f068659172f3bf95de8fedeb465f057dvboxsync

cd5df721f068659172f3bf95de8fedeb465f057dvboxsync # Rotate the input and/or result to match their max-op-sized registers.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uInput = rotateLeftUxx(cbMaxOp * 8, uInput, 8);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync uResult = rotateLeftUxx(cbMaxOp * 8, uResult, 8);

b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync # Hand it over to an overridable worker method.

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync return self.generateOneStdTestGregGreg(oGen, cbEffOp, cbMaxOp, iOp1, iOp1X, iOp2, iOp2X, uInput, uResult);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync def generateOneStdTestGregMemNoSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iOp2, uInput, uResult):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync """ Generate mode 0, 1 and 2 test for the R/M=iOp2. """

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if cAddrBits == 16:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync _ = cbMaxOp;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync else:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync iMod = 0; # No disp, except for i=5.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, None, oGen);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.pushConst(uResult);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iOp2 != 5 and iOp2 != 13:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync iMod = 1;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for offDisp in oGen.getDispForMod(iMod):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.pushConst(uResult);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync iMod = 2;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync for offDisp in oGen.getDispForMod(iMod):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.pushConst(uResult);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync return True;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync def generateOneStdTestGregMemSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iMod, # pylint: disable=R0913

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync iBaseReg, iIndexReg, iScale, uInput, uResult):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync """ Generate one SIB variations. """

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync for offDisp in oGen.getDispForMod(iMod, cbEffOp):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if ((iBaseReg == 5 or iBaseReg == 13) and iMod == 0):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if iIndexReg == 4:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if cAddrBits == 64:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync continue; # skipping.

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync self.generateMemSetupReadByLabel(oGen, cbEffOp, uInput);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.writeInstrGregSibLabel(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync sChecker = oGen.needGRegChecker(iOp1);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

510567648d46488f4166e5f69ffffe3eeeeec4d9vboxsync self.generateMemSetupReadByScaledReg(oGen, cAddrBits, cbEffOp, iIndexReg, iScale, uInput, offDisp);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.writeInstrGregSibScaledReg(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);

510567648d46488f4166e5f69ffffe3eeeeec4d9vboxsync sChecker = oGen.needGRegChecker(iOp1, iIndexReg);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if iIndexReg == 4:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.generateMemSetupReadByReg(oGen, cAddrBits, cbEffOp, iBaseReg, uInput, offDisp);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.writeInstrGregSibBase(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync sChecker = oGen.needGRegChecker(iOp1, iBaseReg);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync else:

b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync if iIndexReg == iBaseReg and iScale == 1 and offDisp is not None and (offDisp & 1):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if offDisp < 0: offDisp += 1;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync else: offDisp -= 1;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync self.generateMemSetupReadByBaseAndScaledReg(oGen, cAddrBits, cbEffOp, iBaseReg,

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync iIndexReg, iScale, uInput, offDisp);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync self.writeInstrGregSibBaseAndScaledReg(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync sChecker = oGen.needGRegChecker(iOp1, iBaseReg, iIndexReg);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.pushConst(uResult);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync oGen.write(' call VBINSTST_NAME(%s)\n' % (sChecker,));

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync _ = cbMaxOp;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync return True;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def generateStdTestGregMemSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, auInputs):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """ Generate all SIB variations for the given iOp1 (reg) value. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync assert cAddrBits in [32, 64];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for _ in oGen.oSibBaseRange:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.iSibBaseReg = (oGen.iSibBaseReg + 1) % oGen.oTarget.getGRegCount(cAddrBits / 8);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if oGen.iSibBaseReg == X86_GREG_xSP: # no RSP testing atm.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync continue;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for _ in oGen.oSibIndexRange:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.iSibIndexReg = (oGen.iSibIndexReg + 1) % oGen.oTarget.getGRegCount(cAddrBits / 8);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for iMod in [0, 1, 2]:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if oGen.iSibBaseReg == iOp1 and ((oGen.iSibBaseReg != 5 and oGen.iSibBaseReg != 13) or iMod != 0) \

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync and cAddrBits != cbMaxOp:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync continue; # Don't know the high bit of the address ending up the result - skip it for now.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if oGen.iSibIndexReg == iOp1 and oGen.iSibIndexReg != 4 and cAddrBits != cbMaxOp:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync continue; # Don't know the high bit of the address ending up the result - skip it for now.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for _ in oGen.oSibScaleRange:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.iSibScale *= 2;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if oGen.iSibScale > 8:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.iSibScale = 1;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for uInput in auInputs:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.newSubTest();

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[iOp1], oGen);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.generateOneStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iMod,

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.iSibBaseReg, oGen.iSibIndexReg, oGen.iSibScale,

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uInput, uResult);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def generateStandardTests(self, oGen):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync """ Generate standard tests. """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # Parameters.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync cbDefOp = oGen.oTarget.getDefOpBytes();

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync cbMaxOp = oGen.oTarget.getMaxOpBytes();

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync auShortInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync auLongInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen, fLong = True);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync iLongOp1 = oGen.oTarget.randGRegNoSp();

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync iLongOp2 = oGen.oTarget.randGRegNoSp();

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oOp2Range = None;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oOp2Range = [iLongOp2,];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # Register tests

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if True:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for cbEffOp in self.acbOpVars:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cbEffOp > cbMaxOp:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync continue;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oOp2Range = range(oGen.oTarget.getGRegCount(cbEffOp));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oOp2Range = [iLongOp2,];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write('; cbEffOp=%u\n' % (cbEffOp,));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

5c9a5681751a936cd9fe7e98d9f30de34bc99372vboxsync for iOp1 in range(oGen.oTarget.getGRegCount(cbEffOp)):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iOp1 == X86_GREG_xSP:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync continue; # Cannot test xSP atm.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for iOp2 in oOp2Range:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if (iOp2 >= 16 and iOp1 in range(4, 16)) \

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync or (iOp1 >= 16 and iOp2 in range(4, 16)):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync continue; # Any REX encoding turns AH,CH,DH,BH regs into SPL,BPL,SIL,DIL.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iOp2 == X86_GREG_xSP:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync continue; # Cannot test xSP atm.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write('; iOp2=%u cbEffOp=%u\n' % (iOp2, cbEffOp));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for uInput in (auLongInputs if iOp1 == iLongOp1 and iOp2 == iLongOp2 else auShortInputs):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.newSubTest();

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if not oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) and not oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uCur = oGen.auRegValues[iOp1 & 15] if iOp1 != iOp2 else uInput;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uResult = self.fnCalcResult(cbEffOp, uInput, uCur, oGen);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.generateOneStdTestGregGreg(oGen, cbEffOp, cbMaxOp, iOp1, iOp1 & 15, iOp2, iOp2 & 15,

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uInput, uResult);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.generateOneStdTestGregGreg8BitHighPain(oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # Memory test.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if True:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for cAddrBits in oGen.oTarget.getAddrModes():

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for cbEffOp in self.acbOpVars:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cbEffOp > cbMaxOp:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync continue;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oOp1MemRange = range(oGen.oTarget.getGRegCount());

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oOp2MemRange = range(oGen.oTarget.getGRegCount(cAddrBits / 8))

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oOp1MemRange = [iLongOp1,];

cd5df721f068659172f3bf95de8fedeb465f057dvboxsync oOp2MemRange = [iLongOp2,];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oOp1MemRange = oGen.oTarget.randGRegNoSpList(3 if oGen.oTarget.is64Bit() else 1, cbEffOp);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oOp2MemRange = oGen.oTarget.randGRegNoSpList(3 + (cAddrBits == 64) * 2, cAddrBits / 8);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iLongOp2 not in oOp1MemRange:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oOp1MemRange.append(iLongOp2);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cAddrBits != 16 and 4 not in oOp2MemRange:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oOp2MemRange.append(4)

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for iOp1 in oOp1MemRange:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iOp1 == X86_GREG_xSP:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync continue; # Cannot test xSP atm.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iOp1 > 15:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync continue; ## TODO AH,CH,DH,BH

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync auInputs = auLongInputs if iOp1 == iLongOp1 else auShortInputs;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for iOp2 in oOp2MemRange:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iOp2 != 4 or cAddrBits == 16:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync for uInput in auInputs:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.newSubTest();

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iOp1 == iOp2 and iOp2 != 5 and iOp2 != 13 and cbEffOp != cbMaxOp:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync continue; # Don't know the high bit of the address ending up the result - skip it for now.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[iOp1 & 15], oGen);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.generateOneStdTestGregMemNoSib(oGen, cAddrBits, cbEffOp, cbMaxOp,

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync iOp1, iOp2, uInput, uResult);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # SIB.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.generateStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, auInputs);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync break;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync break;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def generateTest(self, oGen, sTestFnName):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write('VBINSTST_BEGINPROC %s\n' % (sTestFnName,));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync #oGen.write(' int3\n');

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync self.generateStandardTests(oGen);

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync #oGen.write(' int3\n');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write(' ret\n');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync oGen.write('VBINSTST_ENDPROC %s\n' % (sTestFnName,));

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncclass InstrTest_Mov_Gv_Ev(InstrTest_MemOrGreg_2_Greg):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def __init__(self):

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync InstrTest_MemOrGreg_2_Greg.__init__(self, 'mov Gv,Ev', self.calc_mov);

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync @staticmethod

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync def calc_mov(cbEffOp, uInput, uCur, oGen):

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync """ Calculates the result of a mov instruction."""

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync if cbEffOp == 8:

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync return uInput & UINT64_MAX;

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync if cbEffOp == 4:

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync return uInput & UINT32_MAX;

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync if cbEffOp == 2:

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync return (uCur & 0xffffffffffff0000) | (uInput & UINT16_MAX);

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync assert cbEffOp == 1; _ = oGen;

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync return (uCur & 0xffffffffffffff00) | (uInput & UINT8_MAX);

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsyncclass InstrTest_MovSxD_Gv_Ev(InstrTest_MemOrGreg_2_Greg):

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync """

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync def __init__(self):

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync InstrTest_MemOrGreg_2_Greg.__init__(self, 'movsxd Gv,Ev', self.calc_movsxd, acbOpVars = [ 8, 4, 2, ]);

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen):

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync if cbEffOp == 8:

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs64[iOp1], g_asGRegs32[iOp2]));

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync elif cbEffOp == 4 or cbEffOp == 2:

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync abInstr = [];

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync if cbEffOp != oGen.oTarget.getDefOpBytes():

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync abInstr.append(X86_OP_PRF_SIZE_OP);

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync abInstr += calcRexPrefixForTwoModRmRegs(iOp1, iOp2);

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync abInstr.append(0x63);

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync abInstr += calcModRmForTwoRegs(iOp1, iOp2);

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync oGen.writeInstrBytes(abInstr);

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync else:

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync assert False;

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync assert False;

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync return True;

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync

2e4df4fd9eace3c61be68bb5eb12a93f9a79334dvboxsync def isApplicable(self, oGen):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return oGen.oTarget.is64Bit();

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync @staticmethod

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def calc_movsxd(cbEffOp, uInput, uCur, oGen):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync _ = oGen;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cbEffOp == 8 and (uInput & RT_BIT_32(31)):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return (UINT32_MAX << 32) | (uInput & UINT32_MAX);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if cbEffOp == 2:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return (uCur & 0xffffffffffff0000) | (uInput & 0xffff);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return uInput & UINT32_MAX;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncg_aoInstructionTests = [

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync InstrTest_Mov_Gv_Ev(),

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync #InstrTest_MovSxD_Gv_Ev(),

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsyncclass InstructionTestGen(object):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync ## @name Test size

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ## @{

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ksTestSize_Large = 'large';

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ksTestSize_Medium = 'medium';

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ksTestSize_Tiny = 'tiny';

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync ## @}

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync kasTestSizes = ( ksTestSize_Large, ksTestSize_Medium, ksTestSize_Tiny );

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def __init__(self, oOptions):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.oOptions = oOptions;

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync self.oTarget = g_dTargetEnvs[oOptions.sTargetEnv];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # Calculate the number of output files.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.cFiles = 1;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if len(g_aoInstructionTests) > self.oOptions.cInstrPerFile:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.cFiles = len(g_aoInstructionTests) / self.oOptions.cInstrPerFile;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if self.cFiles * self.oOptions.cInstrPerFile < len(g_aoInstructionTests):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.cFiles += 1;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # Fix the known register values.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.au64Regs = randUxxList(64, 16);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.au32Regs = [(self.au64Regs[i] & UINT32_MAX) for i in range(8)];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.au16Regs = [(self.au64Regs[i] & UINT16_MAX) for i in range(8)];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.auRegValues = self.au64Regs if self.oTarget.is64Bit() else self.au32Regs;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # Declare state variables used while generating.

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.oFile = sys.stderr;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.iFile = -1;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.sFile = '';

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.dCheckFns = dict();

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.dMemSetupFns = dict();

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.d64BitConsts = dict();

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync # State variables used while generating test convenientely placed here (lazy bird)...

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.iSibBaseReg = 0;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync self.iSibIndexReg = 0;

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync self.iSibScale = 1;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if self.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.oSibBaseRange = range(1);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync self.oSibIndexRange = range(2);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync self.oSibScaleRange = range(1);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync elif self.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.oSibBaseRange = range(5);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.oSibIndexRange = range(4);

ffb50166c9adb4ae583b914d405197035cf890advboxsync self.oSibScaleRange = range(2);

ffb50166c9adb4ae583b914d405197035cf890advboxsync else:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.oSibBaseRange = range(8);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.oSibIndexRange = range(9);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.oSibScaleRange = range(4);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync #

462e60a19d02a99b2b1a5c08dff74bb0808d707cvboxsync # Methods used by instruction tests.

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync #

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync def write(self, sText):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync """ Writes to the current output file. """

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync return self.oFile.write(unicode(sText));

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync def writeln(self, sText):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync """ Writes a line to the current output file. """

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync self.write(sText);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync return self.write('\n');

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync def writeInstrBytes(self, abInstr):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync """

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync self.write(' db %#04x' % (abInstr[0],));

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync for i in range(1, len(abInstr)):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync self.write(', %#04x' % (abInstr[i],));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return self.write('\n');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def newSubTest(self):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.write(' mov dword [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) xWrtRIP], __LINE__\n');

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def needGRegChecker(self, iReg1, iReg2 = None, iReg3 = None):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iReg2 is not None:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iReg3 is not None:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync sName = '%s_%s_%s' % (self.oTarget.asGRegs[iReg1], self.oTarget.asGRegs[iReg2], self.oTarget.asGRegs[iReg3],);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync else:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync sName = '%s_%s' % (self.oTarget.asGRegs[iReg1], self.oTarget.asGRegs[iReg2],);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync else:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync sName = '%s' % (self.oTarget.asGRegs[iReg1],);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync assert iReg3 is None;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if sName in self.dCheckFns:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync self.dCheckFns[sName] += 1;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync else:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync self.dCheckFns[sName] = 1;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync return 'Common_Check_' + sName;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync def needGRegMemSetup(self, cAddrBits, cbEffOp, iBaseReg = None, offDisp = None, iIndexReg = None, iScale = 1):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync """

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync sName = '%ubit_U%u' % (cAddrBits, cbEffOp * 8,);

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iBaseReg is not None:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync sName += '_%s' % (gregName(iBaseReg, cAddrBits),);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync sName += '_x%u' % (iScale,);

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if iIndexReg is not None:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync sName += '_%s' % (gregName(iIndexReg, cAddrBits),);

b8bb9c9f6b8ebfd0a7d6df0c0289f9fe80241750vboxsync if offDisp is not None:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync sName += '_%#010x' % (offDisp & UINT32_MAX, );

d3b1b01528fe21777281edf167f8deca06f86e39vboxsync if sName in self.dMemSetupFns:

d3b1b01528fe21777281edf167f8deca06f86e39vboxsync self.dMemSetupFns[sName] += 1;

d3b1b01528fe21777281edf167f8deca06f86e39vboxsync else:

d3b1b01528fe21777281edf167f8deca06f86e39vboxsync self.dMemSetupFns[sName] = 1;

d3b1b01528fe21777281edf167f8deca06f86e39vboxsync return 'Common_MemSetup_' + sName;

d3b1b01528fe21777281edf167f8deca06f86e39vboxsync

d3b1b01528fe21777281edf167f8deca06f86e39vboxsync def need64BitConstant(self, uVal):

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync """

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync assert uVal >= 0 and uVal <= UINT64_MAX;

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync if uVal in self.d64BitConsts:

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync self.d64BitConsts[uVal] += 1;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.d64BitConsts[uVal] = 1;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return 'g_u64Const_0x%016x' % (uVal, );

5050fc8de0b121eab1b738d7c1007cde4903284dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def pushConst(self, uResult):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if self.oTarget.is64Bit() and uResult >= 0x80000000:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.write(' push qword [%s wrt rip]\n' % (self.need64BitConstant(uResult),));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync self.write(' push dword 0x%x\n' % (uResult,));

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync return True;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def getDispForMod(self, iMod, cbAlignment = 1):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync assert cbAlignment in [1, 2, 4, 8];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync if iMod == 0:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync aoffDisp = [ None, ];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync elif iMod == 1:

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync aoffDisp = [ 127 & ~(cbAlignment - 1), -128 ];

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync elif iMod == 2:

0dd3967035b8a02985920baa57f948dc542b9388vboxsync aoffDisp = [ 2147483647 & ~(cbAlignment - 1), -2147483648 ];

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync else: assert False;

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync return aoffDisp;

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync #

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync # Internal machinery.

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync #

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync def _calcTestFunctionName(self, oInstrTest, iInstrTest):

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync """

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync sName = 'TestInstr%03u_%s' % (iInstrTest, oInstrTest.sName);

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync return sName.replace(',', '_').replace(' ', '_').replace('%', '_');

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync def _generateFileHeader(self, ):

553a2f0d8ef91a6dad8de4eef206ff093af53a5dvboxsync """

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync self.write('; $Id$\n'

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync ';; @file %s\n'

0dd3967035b8a02985920baa57f948dc542b9388vboxsync '; Autogenerate by %s %s. DO NOT EDIT\n'

0dd3967035b8a02985920baa57f948dc542b9388vboxsync ';\n'

0dd3967035b8a02985920baa57f948dc542b9388vboxsync '\n'

0dd3967035b8a02985920baa57f948dc542b9388vboxsync ';\n'

0dd3967035b8a02985920baa57f948dc542b9388vboxsync '; Headers\n'

0dd3967035b8a02985920baa57f948dc542b9388vboxsync ';\n'

6475559a7e0e52892efbab4fbdedc879f6866109vboxsync '%%include "env-%s.mac"\n'

0dd3967035b8a02985920baa57f948dc542b9388vboxsync % ( os.path.basename(self.sFile),

0dd3967035b8a02985920baa57f948dc542b9388vboxsync os.path.basename(__file__), __version__[11:-1],

0dd3967035b8a02985920baa57f948dc542b9388vboxsync self.oTarget.sName,

6475559a7e0e52892efbab4fbdedc879f6866109vboxsync ) );

6475559a7e0e52892efbab4fbdedc879f6866109vboxsync # Target environment specific init stuff.

6475559a7e0e52892efbab4fbdedc879f6866109vboxsync

6475559a7e0e52892efbab4fbdedc879f6866109vboxsync #

6475559a7e0e52892efbab4fbdedc879f6866109vboxsync # Global variables.

6475559a7e0e52892efbab4fbdedc879f6866109vboxsync #

0dd3967035b8a02985920baa57f948dc542b9388vboxsync self.write('\n\n'

0dd3967035b8a02985920baa57f948dc542b9388vboxsync ';\n'

0dd3967035b8a02985920baa57f948dc542b9388vboxsync '; Globals\n'

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync ';\n');

c89333d3e41e439ed9e74768000edc399d3e72e6vboxsync self.write('VBINSTST_BEGINDATA\n'

750df3fe104e01cadbc3d5bd20243055d283d4e5vboxsync 'VBINSTST_GLOBALNAME_EX g_pvLow16Mem4K, data hidden\n'